2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
34 #include "devicetree.h"
38 #define DRIVER_NAME "pinctrl-single"
39 #define PCS_OFF_DISABLED ~0U
42 * struct pcs_func_vals - mux function register offset and value pair
43 * @reg: register virtual address
44 * @val: register value
47 struct pcs_func_vals {
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
55 * and value, enable, disable, mask
56 * @param: config parameter
57 * @val: user input bits in the pinconf register
58 * @enable: enable bits in the pinconf register
59 * @disable: disable bits in the pinconf register
60 * @mask: mask bits in the register value
62 struct pcs_conf_vals {
63 enum pin_config_param param;
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
72 * @name: property name in DTS file
73 * @param: config parameter
75 struct pcs_conf_type {
77 enum pin_config_param param;
81 * struct pcs_function - pinctrl function
82 * @name: pinctrl function name
83 * @vals: register and vals array
84 * @nvals: number of entries in vals array
85 * @pgnames: array of pingroup names the function uses
86 * @npgnames: number of pingroup names the function uses
87 * @conf: array of pin configurations
88 * @nconfs: number of pin configurations available
93 struct pcs_func_vals *vals;
97 struct pcs_conf_vals *conf;
99 struct list_head node;
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
104 * @offset: offset base of pins
105 * @npins: number pins with the same mux value of gpio function
106 * @gpiofunc: mux value of gpio function
109 struct pcs_gpiofunc_range {
113 struct list_head node;
117 * struct pcs_data - wrapper for data needed by pinctrl framework
119 * @cur: index to current element
121 * REVISIT: We should be able to drop this eventually by adding
122 * support for registering pins individually in the pinctrl
123 * framework for those drivers that don't need a static array.
126 struct pinctrl_pin_desc *pa;
131 * struct pcs_soc_data - SoC specific settings
132 * @flags: initial SoC specific PCS_FEAT_xxx values
133 * @irq: optional interrupt for the controller
134 * @irq_enable_mask: optional SoC specific interrupt enable mask
135 * @irq_status_mask: optional SoC specific interrupt status mask
136 * @rearm: optional SoC specific wake-up rearm function
138 struct pcs_soc_data {
141 unsigned irq_enable_mask;
142 unsigned irq_status_mask;
147 * struct pcs_device - pinctrl device instance
149 * @base: virtual address of the controller
150 * @saved_vals: saved values for the controller
151 * @size: size of the ioremapped area
153 * @np: device tree node
154 * @pctl: pin controller device
155 * @flags: mask of PCS_FEAT_xxx values
156 * @missing_nr_pinctrl_cells: for legacy binding, may go away
157 * @socdata: soc specific data
158 * @lock: spinlock for register access
159 * @mutex: mutex protecting the lists
160 * @width: bits per mux register
161 * @fmask: function register mask
162 * @fshift: function register shift
163 * @foff: value to turn mux off
164 * @fmax: max number of functions in fmask
165 * @bits_per_mux: number of bits per mux
166 * @bits_per_pin: number of bits per pin
167 * @pins: physical pins on the SoC
168 * @gpiofuncs: list of gpio functions
169 * @irqs: list of interrupt registers
170 * @chip: chip container for this instance
171 * @domain: IRQ domain for this instance
172 * @desc: pin controller descriptor
173 * @read: register read function to use
174 * @write: register write function to use
177 struct resource *res;
182 struct device_node *np;
183 struct pinctrl_dev *pctl;
185 #define PCS_CONTEXT_LOSS_OFF (1 << 3)
186 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
187 #define PCS_FEAT_IRQ (1 << 1)
188 #define PCS_FEAT_PINCONF (1 << 0)
189 struct property *missing_nr_pinctrl_cells;
190 struct pcs_soc_data socdata;
199 unsigned bits_per_pin;
200 struct pcs_data pins;
201 struct list_head gpiofuncs;
202 struct list_head irqs;
203 struct irq_chip chip;
204 struct irq_domain *domain;
205 struct pinctrl_desc desc;
206 unsigned (*read)(void __iomem *reg);
207 void (*write)(unsigned val, void __iomem *reg);
210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
215 unsigned long *config);
216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
217 unsigned long *configs, unsigned num_configs);
219 static enum pin_config_param pcs_bias[] = {
220 PIN_CONFIG_BIAS_PULL_DOWN,
221 PIN_CONFIG_BIAS_PULL_UP,
225 * This lock class tells lockdep that irqchip core that this single
226 * pinctrl can be in a different category than its parents, so it won't
227 * report false recursion.
229 static struct lock_class_key pcs_lock_class;
231 /* Class for the IRQ request mutex */
232 static struct lock_class_key pcs_request_class;
235 * REVISIT: Reads and writes could eventually use regmap or something
236 * generic. But at least on omaps, some mux registers are performance
237 * critical as they may need to be remuxed every time before and after
238 * idle. Adding tests for register access width for every read and
239 * write like regmap is doing is not desired, and caching the registers
240 * does not help in this case.
243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
278 if (pcs->bits_per_mux) {
279 unsigned int pin_offset_bytes;
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
282 return (pin_offset_bytes / mux_bytes) * mux_bytes;
285 return pin * mux_bytes;
288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
294 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
298 struct pcs_device *pcs;
300 unsigned long offset;
303 pcs = pinctrl_dev_get_drvdata(pctldev);
305 offset = pcs_pin_reg_offset_get(pcs, pin);
306 val = pcs->read(pcs->base + offset);
308 if (pcs->bits_per_mux)
309 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
311 pa = pcs->res->start + offset;
313 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
316 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
317 struct pinctrl_map *map, unsigned num_maps)
319 struct pcs_device *pcs;
321 pcs = pinctrl_dev_get_drvdata(pctldev);
322 devm_kfree(pcs->dev, map);
325 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
326 struct device_node *np_config,
327 struct pinctrl_map **map, unsigned *num_maps);
329 static const struct pinctrl_ops pcs_pinctrl_ops = {
330 .get_groups_count = pinctrl_generic_get_group_count,
331 .get_group_name = pinctrl_generic_get_group_name,
332 .get_group_pins = pinctrl_generic_get_group_pins,
333 .pin_dbg_show = pcs_pin_dbg_show,
334 .dt_node_to_map = pcs_dt_node_to_map,
335 .dt_free_map = pcs_dt_free_map,
338 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
339 struct pcs_function **func)
341 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
342 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
343 const struct pinctrl_setting_mux *setting;
344 struct function_desc *function;
347 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
348 setting = pdesc->mux_setting;
351 fselector = setting->func;
352 function = pinmux_generic_get_function(pctldev, fselector);
353 *func = function->data;
355 dev_err(pcs->dev, "%s could not find function%i\n",
356 __func__, fselector);
362 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
365 struct pcs_device *pcs;
366 struct function_desc *function;
367 struct pcs_function *func;
370 pcs = pinctrl_dev_get_drvdata(pctldev);
371 /* If function mask is null, needn't enable it. */
374 function = pinmux_generic_get_function(pctldev, fselector);
375 func = function->data;
379 dev_dbg(pcs->dev, "enabling %s function%i\n",
380 func->name, fselector);
382 for (i = 0; i < func->nvals; i++) {
383 struct pcs_func_vals *vals;
387 vals = &func->vals[i];
388 raw_spin_lock_irqsave(&pcs->lock, flags);
389 val = pcs->read(vals->reg);
391 if (pcs->bits_per_mux)
397 val |= (vals->val & mask);
398 pcs->write(val, vals->reg);
399 raw_spin_unlock_irqrestore(&pcs->lock, flags);
405 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
406 struct pinctrl_gpio_range *range, unsigned pin)
408 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
409 struct pcs_gpiofunc_range *frange = NULL;
410 struct list_head *pos, *tmp;
413 /* If function mask is null, return directly. */
417 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
420 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
421 if (pin >= frange->offset + frange->npins
422 || pin < frange->offset)
425 offset = pcs_pin_reg_offset_get(pcs, pin);
427 if (pcs->bits_per_mux) {
428 int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
430 data = pcs->read(pcs->base + offset);
431 data &= ~(pcs->fmask << pin_shift);
432 data |= frange->gpiofunc << pin_shift;
433 pcs->write(data, pcs->base + offset);
435 data = pcs->read(pcs->base + offset);
437 data |= frange->gpiofunc;
438 pcs->write(data, pcs->base + offset);
445 static const struct pinmux_ops pcs_pinmux_ops = {
446 .get_functions_count = pinmux_generic_get_function_count,
447 .get_function_name = pinmux_generic_get_function_name,
448 .get_function_groups = pinmux_generic_get_function_groups,
449 .set_mux = pcs_set_mux,
450 .gpio_request_enable = pcs_request_gpio,
453 /* Clear BIAS value */
454 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
456 unsigned long config;
458 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
459 config = pinconf_to_config_packed(pcs_bias[i], 0);
460 pcs_pinconf_set(pctldev, pin, &config, 1);
465 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
466 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
468 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
470 unsigned long config;
473 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
474 config = pinconf_to_config_packed(pcs_bias[i], 0);
475 if (!pcs_pinconf_get(pctldev, pin, &config))
483 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
484 unsigned pin, unsigned long *config)
486 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
487 struct pcs_function *func;
488 enum pin_config_param param;
489 unsigned offset = 0, data = 0, i, j, ret;
491 ret = pcs_get_function(pctldev, pin, &func);
495 for (i = 0; i < func->nconfs; i++) {
496 param = pinconf_to_config_param(*config);
497 if (param == PIN_CONFIG_BIAS_DISABLE) {
498 if (pcs_pinconf_bias_disable(pctldev, pin)) {
504 } else if (param != func->conf[i].param) {
508 offset = pin * (pcs->width / BITS_PER_BYTE);
509 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
510 switch (func->conf[i].param) {
512 case PIN_CONFIG_BIAS_PULL_DOWN:
513 case PIN_CONFIG_BIAS_PULL_UP:
514 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
515 if ((data != func->conf[i].enable) ||
516 (data == func->conf[i].disable))
521 case PIN_CONFIG_INPUT_SCHMITT:
522 for (j = 0; j < func->nconfs; j++) {
523 switch (func->conf[j].param) {
524 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
525 if (data != func->conf[j].enable)
534 case PIN_CONFIG_DRIVE_STRENGTH:
535 case PIN_CONFIG_SLEW_RATE:
536 case PIN_CONFIG_LOW_POWER_MODE:
546 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
547 unsigned pin, unsigned long *configs,
548 unsigned num_configs)
550 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
551 struct pcs_function *func;
552 unsigned offset = 0, shift = 0, i, data, ret;
556 ret = pcs_get_function(pctldev, pin, &func);
560 for (j = 0; j < num_configs; j++) {
561 for (i = 0; i < func->nconfs; i++) {
562 if (pinconf_to_config_param(configs[j])
563 != func->conf[i].param)
566 offset = pin * (pcs->width / BITS_PER_BYTE);
567 data = pcs->read(pcs->base + offset);
568 arg = pinconf_to_config_argument(configs[j]);
569 switch (func->conf[i].param) {
571 case PIN_CONFIG_INPUT_SCHMITT:
572 case PIN_CONFIG_DRIVE_STRENGTH:
573 case PIN_CONFIG_SLEW_RATE:
574 case PIN_CONFIG_LOW_POWER_MODE:
575 shift = ffs(func->conf[i].mask) - 1;
576 data &= ~func->conf[i].mask;
577 data |= (arg << shift) & func->conf[i].mask;
580 case PIN_CONFIG_BIAS_DISABLE:
581 pcs_pinconf_clear_bias(pctldev, pin);
583 case PIN_CONFIG_BIAS_PULL_DOWN:
584 case PIN_CONFIG_BIAS_PULL_UP:
586 pcs_pinconf_clear_bias(pctldev, pin);
588 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
589 data &= ~func->conf[i].mask;
591 data |= func->conf[i].enable;
593 data |= func->conf[i].disable;
598 pcs->write(data, pcs->base + offset);
602 if (i >= func->nconfs)
604 } /* for each config */
609 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
610 unsigned group, unsigned long *config)
612 const unsigned *pins;
613 unsigned npins, old = 0;
616 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
619 for (i = 0; i < npins; i++) {
620 if (pcs_pinconf_get(pctldev, pins[i], config))
622 /* configs do not match between two pins */
623 if (i && (old != *config))
630 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
631 unsigned group, unsigned long *configs,
632 unsigned num_configs)
634 const unsigned *pins;
638 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
641 for (i = 0; i < npins; i++) {
642 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
648 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
649 struct seq_file *s, unsigned pin)
653 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
654 struct seq_file *s, unsigned selector)
658 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
660 unsigned long config)
662 pinconf_generic_dump_config(pctldev, s, config);
665 static const struct pinconf_ops pcs_pinconf_ops = {
666 .pin_config_get = pcs_pinconf_get,
667 .pin_config_set = pcs_pinconf_set,
668 .pin_config_group_get = pcs_pinconf_group_get,
669 .pin_config_group_set = pcs_pinconf_group_set,
670 .pin_config_dbg_show = pcs_pinconf_dbg_show,
671 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
672 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
677 * pcs_add_pin() - add a pin to the static per controller pin array
678 * @pcs: pcs driver instance
679 * @offset: register offset from base
681 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
683 struct pcs_soc_data *pcs_soc = &pcs->socdata;
684 struct pinctrl_pin_desc *pin;
688 if (i >= pcs->desc.npins) {
689 dev_err(pcs->dev, "too many pins, max %i\n",
694 if (pcs_soc->irq_enable_mask) {
697 val = pcs->read(pcs->base + offset);
698 if (val & pcs_soc->irq_enable_mask) {
699 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
700 (unsigned long)pcs->res->start + offset, val);
701 val &= ~pcs_soc->irq_enable_mask;
702 pcs->write(val, pcs->base + offset);
706 pin = &pcs->pins.pa[i];
714 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
715 * @pcs: pcs driver instance
717 * In case of errors, resources are freed in pcs_free_resources.
719 * If your hardware needs holes in the address space, then just set
720 * up multiple driver instances.
722 static int pcs_allocate_pin_table(struct pcs_device *pcs)
724 int mux_bytes, nr_pins, i;
725 int num_pins_in_register = 0;
727 mux_bytes = pcs->width / BITS_PER_BYTE;
729 if (pcs->bits_per_mux) {
730 pcs->bits_per_pin = fls(pcs->fmask);
731 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
732 num_pins_in_register = pcs->width / pcs->bits_per_pin;
734 nr_pins = pcs->size / mux_bytes;
737 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
738 pcs->pins.pa = devm_kcalloc(pcs->dev,
739 nr_pins, sizeof(*pcs->pins.pa),
744 pcs->desc.pins = pcs->pins.pa;
745 pcs->desc.npins = nr_pins;
747 for (i = 0; i < pcs->desc.npins; i++) {
751 offset = pcs_pin_reg_offset_get(pcs, i);
752 res = pcs_add_pin(pcs, offset);
754 dev_err(pcs->dev, "error adding pins: %i\n", res);
763 * pcs_add_function() - adds a new function to the function list
764 * @pcs: pcs driver instance
765 * @fcn: new function allocated
766 * @name: name of the function
767 * @vals: array of mux register value pairs used by the function
768 * @nvals: number of mux register value pairs
769 * @pgnames: array of pingroup names for the function
770 * @npgnames: number of pingroup names
772 * Caller must take care of locking.
774 static int pcs_add_function(struct pcs_device *pcs,
775 struct pcs_function **fcn,
777 struct pcs_func_vals *vals,
779 const char **pgnames,
780 unsigned int npgnames)
782 struct pcs_function *function;
785 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
789 function->vals = vals;
790 function->nvals = nvals;
792 selector = pinmux_generic_add_function(pcs->pctl, name,
796 devm_kfree(pcs->dev, function);
806 * pcs_get_pin_by_offset() - get a pin index based on the register offset
807 * @pcs: pcs driver instance
808 * @offset: register offset from the base
810 * Note that this is OK as long as the pins are in a static array.
812 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
816 if (offset >= pcs->size) {
817 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
822 if (pcs->bits_per_mux)
823 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
825 index = offset / (pcs->width / BITS_PER_BYTE);
831 * check whether data matches enable bits or disable bits
832 * Return value: 1 for matching enable bits, 0 for matching disable bits,
833 * and negative value for matching failure.
835 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
841 else if (data == disable)
846 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
847 unsigned value, unsigned enable, unsigned disable,
850 (*conf)->param = param;
851 (*conf)->val = value;
852 (*conf)->enable = enable;
853 (*conf)->disable = disable;
854 (*conf)->mask = mask;
858 static void add_setting(unsigned long **setting, enum pin_config_param param,
861 **setting = pinconf_to_config_packed(param, arg);
865 /* add pinconf setting with 2 parameters */
866 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
867 const char *name, enum pin_config_param param,
868 struct pcs_conf_vals **conf, unsigned long **settings)
870 unsigned value[2], shift;
873 ret = of_property_read_u32_array(np, name, value, 2);
876 /* set value & mask */
877 value[0] &= value[1];
878 shift = ffs(value[1]) - 1;
879 /* skip enable & disable */
880 add_config(conf, param, value[0], 0, 0, value[1]);
881 add_setting(settings, param, value[0] >> shift);
884 /* add pinconf setting with 4 parameters */
885 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
886 const char *name, enum pin_config_param param,
887 struct pcs_conf_vals **conf, unsigned long **settings)
892 /* value to set, enable, disable, mask */
893 ret = of_property_read_u32_array(np, name, value, 4);
897 dev_err(pcs->dev, "mask field of the property can't be 0\n");
900 value[0] &= value[3];
901 value[1] &= value[3];
902 value[2] &= value[3];
903 ret = pcs_config_match(value[0], value[1], value[2]);
905 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
906 add_config(conf, param, value[0], value[1], value[2], value[3]);
907 add_setting(settings, param, ret);
910 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
911 struct pcs_function *func,
912 struct pinctrl_map **map)
915 struct pinctrl_map *m = *map;
916 int i = 0, nconfs = 0;
917 unsigned long *settings = NULL, *s = NULL;
918 struct pcs_conf_vals *conf = NULL;
919 static const struct pcs_conf_type prop2[] = {
920 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
921 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
922 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
923 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
925 static const struct pcs_conf_type prop4[] = {
926 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
927 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
928 { "pinctrl-single,input-schmitt-enable",
929 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
932 /* If pinconf isn't supported, don't parse properties in below. */
933 if (!PCS_HAS_PINCONF)
936 /* cacluate how much properties are supported in current node */
937 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
938 if (of_find_property(np, prop2[i].name, NULL))
941 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
942 if (of_find_property(np, prop4[i].name, NULL))
948 func->conf = devm_kcalloc(pcs->dev,
949 nconfs, sizeof(struct pcs_conf_vals),
953 func->nconfs = nconfs;
954 conf = &(func->conf[0]);
956 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
962 for (i = 0; i < ARRAY_SIZE(prop2); i++)
963 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
965 for (i = 0; i < ARRAY_SIZE(prop4); i++)
966 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
968 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
969 m->data.configs.group_or_pin = np->name;
970 m->data.configs.configs = settings;
971 m->data.configs.num_configs = nconfs;
976 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
977 * @pcs: pinctrl driver instance
978 * @np: device node of the mux entry
980 * @num_maps: number of map
981 * @pgnames: pingroup names
983 * Note that this binding currently supports only sets of one register + value.
985 * Also note that this driver tries to avoid understanding pin and function
986 * names because of the extra bloat they would cause especially in the case of
987 * a large number of pins. This driver just sets what is specified for the board
988 * in the .dts file. Further user space debugging tools can be developed to
989 * decipher the pin and function names using debugfs.
991 * If you are concerned about the boot time, set up the static pins in
992 * the bootloader, and only set up selected pins as device tree entries.
994 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
995 struct device_node *np,
996 struct pinctrl_map **map,
998 const char **pgnames)
1000 const char *name = "pinctrl-single,pins";
1001 struct pcs_func_vals *vals;
1002 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1003 struct pcs_function *function = NULL;
1005 rows = pinctrl_count_index_with_args(np, name);
1007 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1011 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1015 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1019 for (i = 0; i < rows; i++) {
1020 struct of_phandle_args pinctrl_spec;
1021 unsigned int offset;
1024 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1028 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1029 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1030 pinctrl_spec.args_count);
1034 offset = pinctrl_spec.args[0];
1035 vals[found].reg = pcs->base + offset;
1037 switch (pinctrl_spec.args_count) {
1039 vals[found].val = pinctrl_spec.args[1];
1042 vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1046 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1047 pinctrl_spec.np, offset, vals[found].val);
1049 pin = pcs_get_pin_by_offset(pcs, offset);
1052 "could not add functions for %pOFn %ux\n",
1056 pins[found++] = pin;
1059 pgnames[0] = np->name;
1060 mutex_lock(&pcs->mutex);
1061 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1068 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1074 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1075 (*map)->data.mux.group = np->name;
1076 (*map)->data.mux.function = np->name;
1078 if (PCS_HAS_PINCONF && function) {
1079 res = pcs_parse_pinconf(pcs, np, function, map);
1082 else if (res == -ENOTSUPP)
1085 goto free_pingroups;
1089 mutex_unlock(&pcs->mutex);
1094 pinctrl_generic_remove_group(pcs->pctl, gsel);
1097 pinmux_generic_remove_function(pcs->pctl, fsel);
1099 mutex_unlock(&pcs->mutex);
1100 devm_kfree(pcs->dev, pins);
1103 devm_kfree(pcs->dev, vals);
1108 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1109 struct device_node *np,
1110 struct pinctrl_map **map,
1112 const char **pgnames)
1114 const char *name = "pinctrl-single,bits";
1115 struct pcs_func_vals *vals;
1116 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1118 struct pcs_function *function = NULL;
1120 rows = pinctrl_count_index_with_args(np, name);
1122 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1126 npins_in_row = pcs->width / pcs->bits_per_pin;
1128 vals = devm_kzalloc(pcs->dev,
1129 array3_size(rows, npins_in_row, sizeof(*vals)),
1134 pins = devm_kzalloc(pcs->dev,
1135 array3_size(rows, npins_in_row, sizeof(*pins)),
1140 for (i = 0; i < rows; i++) {
1141 struct of_phandle_args pinctrl_spec;
1142 unsigned offset, val;
1143 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1144 unsigned pin_num_from_lsb;
1147 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1151 if (pinctrl_spec.args_count < 3) {
1152 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1153 pinctrl_spec.args_count);
1157 /* Index plus two value cells */
1158 offset = pinctrl_spec.args[0];
1159 val = pinctrl_spec.args[1];
1160 mask = pinctrl_spec.args[2];
1162 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1163 pinctrl_spec.np, offset, val, mask);
1165 /* Parse pins in each row from LSB */
1167 bit_pos = __ffs(mask);
1168 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1169 mask_pos = ((pcs->fmask) << bit_pos);
1170 val_pos = val & mask_pos;
1171 submask = mask & mask_pos;
1173 if ((mask & mask_pos) == 0) {
1175 "Invalid mask for %pOFn at 0x%x\n",
1182 if (submask != mask_pos) {
1184 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1185 submask, np, offset);
1189 vals[found].mask = submask;
1190 vals[found].reg = pcs->base + offset;
1191 vals[found].val = val_pos;
1193 pin = pcs_get_pin_by_offset(pcs, offset);
1196 "could not add functions for %pOFn %ux\n",
1200 pins[found++] = pin + pin_num_from_lsb;
1204 pgnames[0] = np->name;
1205 mutex_lock(&pcs->mutex);
1206 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1213 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1219 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1220 (*map)->data.mux.group = np->name;
1221 (*map)->data.mux.function = np->name;
1223 if (PCS_HAS_PINCONF) {
1224 dev_err(pcs->dev, "pinconf not supported\n");
1226 goto free_pingroups;
1230 mutex_unlock(&pcs->mutex);
1235 pinctrl_generic_remove_group(pcs->pctl, gsel);
1238 pinmux_generic_remove_function(pcs->pctl, fsel);
1240 mutex_unlock(&pcs->mutex);
1241 devm_kfree(pcs->dev, pins);
1244 devm_kfree(pcs->dev, vals);
1249 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1250 * @pctldev: pinctrl instance
1251 * @np_config: device tree pinmux entry
1252 * @map: array of map entries
1253 * @num_maps: number of maps
1255 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1256 struct device_node *np_config,
1257 struct pinctrl_map **map, unsigned *num_maps)
1259 struct pcs_device *pcs;
1260 const char **pgnames;
1263 pcs = pinctrl_dev_get_drvdata(pctldev);
1265 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1266 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1272 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1278 if (pcs->bits_per_mux) {
1279 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1282 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1287 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1290 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1299 devm_kfree(pcs->dev, pgnames);
1301 devm_kfree(pcs->dev, *map);
1307 * pcs_irq_free() - free interrupt
1308 * @pcs: pcs driver instance
1310 static void pcs_irq_free(struct pcs_device *pcs)
1312 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1314 if (pcs_soc->irq < 0)
1318 irq_domain_remove(pcs->domain);
1320 if (PCS_QUIRK_HAS_SHARED_IRQ)
1321 free_irq(pcs_soc->irq, pcs_soc);
1323 irq_set_chained_handler(pcs_soc->irq, NULL);
1327 * pcs_free_resources() - free memory used by this driver
1328 * @pcs: pcs driver instance
1330 static void pcs_free_resources(struct pcs_device *pcs)
1333 pinctrl_unregister(pcs->pctl);
1335 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1336 if (pcs->missing_nr_pinctrl_cells)
1337 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1341 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1343 const char *propname = "pinctrl-single,gpio-range";
1344 const char *cellname = "#pinctrl-single,gpio-range-cells";
1345 struct of_phandle_args gpiospec;
1346 struct pcs_gpiofunc_range *range;
1349 for (i = 0; ; i++) {
1350 ret = of_parse_phandle_with_args(node, propname, cellname,
1352 /* Do not treat it as error. Only treat it as end condition. */
1357 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1362 range->offset = gpiospec.args[0];
1363 range->npins = gpiospec.args[1];
1364 range->gpiofunc = gpiospec.args[2];
1365 mutex_lock(&pcs->mutex);
1366 list_add_tail(&range->node, &pcs->gpiofuncs);
1367 mutex_unlock(&pcs->mutex);
1373 * struct pcs_interrupt
1374 * @reg: virtual address of interrupt register
1375 * @hwirq: hardware irq number
1376 * @irq: virtual irq number
1379 struct pcs_interrupt {
1381 irq_hw_number_t hwirq;
1383 struct list_head node;
1387 * pcs_irq_set() - enables or disables an interrupt
1388 * @pcs_soc: SoC specific settings
1390 * @enable: enable or disable the interrupt
1392 * Note that this currently assumes one interrupt per pinctrl
1393 * register that is typically used for wake-up events.
1395 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1396 int irq, const bool enable)
1398 struct pcs_device *pcs;
1399 struct list_head *pos;
1402 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1403 list_for_each(pos, &pcs->irqs) {
1404 struct pcs_interrupt *pcswi;
1407 pcswi = list_entry(pos, struct pcs_interrupt, node);
1408 if (irq != pcswi->irq)
1411 soc_mask = pcs_soc->irq_enable_mask;
1412 raw_spin_lock(&pcs->lock);
1413 mask = pcs->read(pcswi->reg);
1418 pcs->write(mask, pcswi->reg);
1420 /* flush posted write */
1421 mask = pcs->read(pcswi->reg);
1422 raw_spin_unlock(&pcs->lock);
1430 * pcs_irq_mask() - mask pinctrl interrupt
1431 * @d: interrupt data
1433 static void pcs_irq_mask(struct irq_data *d)
1435 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1437 pcs_irq_set(pcs_soc, d->irq, false);
1441 * pcs_irq_unmask() - unmask pinctrl interrupt
1442 * @d: interrupt data
1444 static void pcs_irq_unmask(struct irq_data *d)
1446 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1448 pcs_irq_set(pcs_soc, d->irq, true);
1452 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1453 * @d: interrupt data
1454 * @state: wake-up state
1456 * Note that this should be called only for suspend and resume.
1457 * For runtime PM, the wake-up events should be enabled by default.
1459 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1470 * pcs_irq_handle() - common interrupt handler
1471 * @pcs_soc: SoC specific settings
1473 * Note that this currently assumes we have one interrupt bit per
1474 * mux register. This interrupt is typically used for wake-up events.
1475 * For more complex interrupts different handlers can be specified.
1477 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1479 struct pcs_device *pcs;
1480 struct list_head *pos;
1483 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1484 list_for_each(pos, &pcs->irqs) {
1485 struct pcs_interrupt *pcswi;
1488 pcswi = list_entry(pos, struct pcs_interrupt, node);
1489 raw_spin_lock(&pcs->lock);
1490 mask = pcs->read(pcswi->reg);
1491 raw_spin_unlock(&pcs->lock);
1492 if (mask & pcs_soc->irq_status_mask) {
1493 generic_handle_irq(irq_find_mapping(pcs->domain,
1503 * pcs_irq_handler() - handler for the shared interrupt case
1507 * Use this for cases where multiple instances of
1508 * pinctrl-single share a single interrupt like on omaps.
1510 static irqreturn_t pcs_irq_handler(int irq, void *d)
1512 struct pcs_soc_data *pcs_soc = d;
1514 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1518 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1519 * @desc: interrupt descriptor
1521 * Use this if you have a separate interrupt for each
1522 * pinctrl-single instance.
1524 static void pcs_irq_chain_handler(struct irq_desc *desc)
1526 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1527 struct irq_chip *chip;
1529 chip = irq_desc_get_chip(desc);
1530 chained_irq_enter(chip, desc);
1531 pcs_irq_handle(pcs_soc);
1532 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1533 chained_irq_exit(chip, desc);
1536 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1537 irq_hw_number_t hwirq)
1539 struct pcs_soc_data *pcs_soc = d->host_data;
1540 struct pcs_device *pcs;
1541 struct pcs_interrupt *pcswi;
1543 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1544 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1548 pcswi->reg = pcs->base + hwirq;
1549 pcswi->hwirq = hwirq;
1552 mutex_lock(&pcs->mutex);
1553 list_add_tail(&pcswi->node, &pcs->irqs);
1554 mutex_unlock(&pcs->mutex);
1556 irq_set_chip_data(irq, pcs_soc);
1557 irq_set_chip_and_handler(irq, &pcs->chip,
1559 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1560 irq_set_noprobe(irq);
1565 static const struct irq_domain_ops pcs_irqdomain_ops = {
1566 .map = pcs_irqdomain_map,
1567 .xlate = irq_domain_xlate_onecell,
1571 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1572 * @pcs: pcs driver instance
1573 * @np: device node pointer
1575 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1576 struct device_node *np)
1578 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1579 const char *name = "pinctrl";
1582 if (!pcs_soc->irq_enable_mask ||
1583 !pcs_soc->irq_status_mask) {
1588 INIT_LIST_HEAD(&pcs->irqs);
1589 pcs->chip.name = name;
1590 pcs->chip.irq_ack = pcs_irq_mask;
1591 pcs->chip.irq_mask = pcs_irq_mask;
1592 pcs->chip.irq_unmask = pcs_irq_unmask;
1593 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1595 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1598 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1599 IRQF_SHARED | IRQF_NO_SUSPEND |
1607 irq_set_chained_handler_and_data(pcs_soc->irq,
1608 pcs_irq_chain_handler,
1613 * We can use the register offset as the hardirq
1614 * number as irq_domain_add_simple maps them lazily.
1615 * This way we can easily support more than one
1616 * interrupt per function if needed.
1618 num_irqs = pcs->size;
1620 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1624 irq_set_chained_handler(pcs_soc->irq, NULL);
1632 static int pcs_save_context(struct pcs_device *pcs)
1639 mux_bytes = pcs->width / BITS_PER_BYTE;
1641 if (!pcs->saved_vals) {
1642 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1643 if (!pcs->saved_vals)
1647 switch (pcs->width) {
1649 regsl = pcs->saved_vals;
1650 for (i = 0; i < pcs->size; i += mux_bytes)
1651 *regsl++ = pcs->read(pcs->base + i);
1654 regsw = pcs->saved_vals;
1655 for (i = 0; i < pcs->size; i += mux_bytes)
1656 *regsw++ = pcs->read(pcs->base + i);
1659 regshw = pcs->saved_vals;
1660 for (i = 0; i < pcs->size; i += mux_bytes)
1661 *regshw++ = pcs->read(pcs->base + i);
1668 static void pcs_restore_context(struct pcs_device *pcs)
1675 mux_bytes = pcs->width / BITS_PER_BYTE;
1677 switch (pcs->width) {
1679 regsl = pcs->saved_vals;
1680 for (i = 0; i < pcs->size; i += mux_bytes)
1681 pcs->write(*regsl++, pcs->base + i);
1684 regsw = pcs->saved_vals;
1685 for (i = 0; i < pcs->size; i += mux_bytes)
1686 pcs->write(*regsw++, pcs->base + i);
1689 regshw = pcs->saved_vals;
1690 for (i = 0; i < pcs->size; i += mux_bytes)
1691 pcs->write(*regshw++, pcs->base + i);
1696 static int pinctrl_single_suspend(struct platform_device *pdev,
1699 struct pcs_device *pcs;
1701 pcs = platform_get_drvdata(pdev);
1705 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1708 ret = pcs_save_context(pcs);
1713 return pinctrl_force_sleep(pcs->pctl);
1716 static int pinctrl_single_resume(struct platform_device *pdev)
1718 struct pcs_device *pcs;
1720 pcs = platform_get_drvdata(pdev);
1724 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1725 pcs_restore_context(pcs);
1727 return pinctrl_force_default(pcs->pctl);
1732 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1733 * @pcs: pinctrl driver instance
1734 * @np: device tree node
1735 * @cells: number of cells
1737 * Handle legacy binding with no #pinctrl-cells. This should be
1738 * always two pinctrl-single,bit-per-mux and one for others.
1739 * At some point we may want to consider removing this.
1741 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1742 struct device_node *np,
1746 const char *name = "#pinctrl-cells";
1750 error = of_property_read_u32(np, name, &val);
1754 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1757 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1761 p->length = sizeof(__be32);
1762 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1765 *(__be32 *)p->value = cpu_to_be32(cells);
1767 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1771 pcs->missing_nr_pinctrl_cells = p;
1773 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1774 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1780 static int pcs_probe(struct platform_device *pdev)
1782 struct device_node *np = pdev->dev.of_node;
1783 struct pcs_pdata *pdata;
1784 struct resource *res;
1785 struct pcs_device *pcs;
1786 const struct pcs_soc_data *soc;
1789 soc = of_device_get_match_data(&pdev->dev);
1793 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1797 pcs->dev = &pdev->dev;
1799 raw_spin_lock_init(&pcs->lock);
1800 mutex_init(&pcs->mutex);
1801 INIT_LIST_HEAD(&pcs->gpiofuncs);
1802 pcs->flags = soc->flags;
1803 memcpy(&pcs->socdata, soc, sizeof(*soc));
1805 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1808 dev_err(pcs->dev, "register width not specified\n");
1813 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1816 pcs->fshift = __ffs(pcs->fmask);
1817 pcs->fmax = pcs->fmask >> pcs->fshift;
1819 /* If mask property doesn't exist, function mux is invalid. */
1825 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1828 pcs->foff = PCS_OFF_DISABLED;
1830 pcs->bits_per_mux = of_property_read_bool(np,
1831 "pinctrl-single,bit-per-mux");
1832 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1833 pcs->bits_per_mux ? 2 : 1);
1835 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1840 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1842 dev_err(pcs->dev, "could not get resource\n");
1846 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1847 resource_size(res), DRIVER_NAME);
1849 dev_err(pcs->dev, "could not get mem_region\n");
1853 pcs->size = resource_size(pcs->res);
1854 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1856 dev_err(pcs->dev, "could not ioremap\n");
1860 platform_set_drvdata(pdev, pcs);
1862 switch (pcs->width) {
1864 pcs->read = pcs_readb;
1865 pcs->write = pcs_writeb;
1868 pcs->read = pcs_readw;
1869 pcs->write = pcs_writew;
1872 pcs->read = pcs_readl;
1873 pcs->write = pcs_writel;
1879 pcs->desc.name = DRIVER_NAME;
1880 pcs->desc.pctlops = &pcs_pinctrl_ops;
1881 pcs->desc.pmxops = &pcs_pinmux_ops;
1882 if (PCS_HAS_PINCONF)
1883 pcs->desc.confops = &pcs_pinconf_ops;
1884 pcs->desc.owner = THIS_MODULE;
1886 ret = pcs_allocate_pin_table(pcs);
1890 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1892 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1896 ret = pcs_add_gpio_func(np, pcs);
1900 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1901 if (pcs->socdata.irq)
1902 pcs->flags |= PCS_FEAT_IRQ;
1904 /* We still need auxdata for some omaps for PRM interrupts */
1905 pdata = dev_get_platdata(&pdev->dev);
1908 pcs->socdata.rearm = pdata->rearm;
1910 pcs->socdata.irq = pdata->irq;
1911 pcs->flags |= PCS_FEAT_IRQ;
1916 ret = pcs_irq_init_chained_handler(pcs, np);
1918 dev_warn(pcs->dev, "initialized with no interrupts\n");
1921 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1923 return pinctrl_enable(pcs->pctl);
1926 pcs_free_resources(pcs);
1931 static int pcs_remove(struct platform_device *pdev)
1933 struct pcs_device *pcs = platform_get_drvdata(pdev);
1938 pcs_free_resources(pcs);
1943 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1944 .flags = PCS_QUIRK_SHARED_IRQ,
1945 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1946 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1949 static const struct pcs_soc_data pinctrl_single_dra7 = {
1950 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1951 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1954 static const struct pcs_soc_data pinctrl_single_am437x = {
1955 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1956 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1957 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1960 static const struct pcs_soc_data pinctrl_single = {
1963 static const struct pcs_soc_data pinconf_single = {
1964 .flags = PCS_FEAT_PINCONF,
1967 static const struct of_device_id pcs_of_match[] = {
1968 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1969 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1970 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1971 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1972 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1973 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1974 { .compatible = "pinconf-single", .data = &pinconf_single },
1977 MODULE_DEVICE_TABLE(of, pcs_of_match);
1979 static struct platform_driver pcs_driver = {
1981 .remove = pcs_remove,
1983 .name = DRIVER_NAME,
1984 .of_match_table = pcs_of_match,
1987 .suspend = pinctrl_single_suspend,
1988 .resume = pinctrl_single_resume,
1992 module_platform_driver(pcs_driver);
1994 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1995 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1996 MODULE_LICENSE("GPL v2");