2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/init.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
61 enum rockchip_pinctrl_type {
74 * Encode variants of iomux registers into a type variable
76 #define IOMUX_GPIO_ONLY BIT(0)
77 #define IOMUX_WIDTH_4BIT BIT(1)
78 #define IOMUX_SOURCE_PMU BIT(2)
79 #define IOMUX_UNROUTED BIT(3)
80 #define IOMUX_WIDTH_3BIT BIT(4)
83 * @type: iomux variant using IOMUX_* constants
84 * @offset: if initialized to -1 it will be autocalculated, by specifying
85 * an initial offset value the relevant source offset can be reset
86 * to a new value for autocalculating the following iomux registers.
88 struct rockchip_iomux {
94 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
96 enum rockchip_pin_drv_type {
97 DRV_TYPE_IO_DEFAULT = 0,
98 DRV_TYPE_IO_1V8_OR_3V0,
100 DRV_TYPE_IO_1V8_3V0_AUTO,
101 DRV_TYPE_IO_3V3_ONLY,
106 * enum type index corresponding to rockchip_pull_list arrays index.
108 enum rockchip_pin_pull_type {
109 PULL_TYPE_IO_DEFAULT = 0,
110 PULL_TYPE_IO_1V8_ONLY,
115 * @drv_type: drive strength variant using rockchip_perpin_drv_type
116 * @offset: if initialized to -1 it will be autocalculated, by specifying
117 * an initial offset value the relevant source offset can be reset
118 * to a new value for autocalculating the following drive strength
119 * registers. if used chips own cal_drv func instead to calculate
120 * registers offset, the variant could be ignored.
122 struct rockchip_drv {
123 enum rockchip_pin_drv_type drv_type;
128 * @reg_base: register base of the gpio bank
129 * @reg_pull: optional separate register for additional pull settings
130 * @clk: clock of the gpio bank
131 * @irq: interrupt of the gpio bank
132 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
133 * @pin_base: first pin number
134 * @nr_pins: number of pins in this bank
135 * @name: name of the bank
136 * @bank_num: number of the bank, to account for holes
137 * @iomux: array describing the 4 iomux sources of the bank
138 * @drv: array describing the 4 drive strength sources of the bank
139 * @pull_type: array describing the 4 pull type sources of the bank
140 * @valid: is all necessary information present
141 * @of_node: dt node of this bank
142 * @drvdata: common pinctrl basedata
143 * @domain: irqdomain of the gpio bank
144 * @gpio_chip: gpiolib chip
145 * @grange: gpio range
146 * @slock: spinlock for the gpio bank
147 * @route_mask: bits describing the routing pins of per bank
149 struct rockchip_pin_bank {
150 void __iomem *reg_base;
151 struct regmap *regmap_pull;
159 struct rockchip_iomux iomux[4];
160 struct rockchip_drv drv[4];
161 enum rockchip_pin_pull_type pull_type[4];
163 struct device_node *of_node;
164 struct rockchip_pinctrl *drvdata;
165 struct irq_domain *domain;
166 struct gpio_chip gpio_chip;
167 struct pinctrl_gpio_range grange;
168 raw_spinlock_t slock;
169 u32 toggle_edge_mode;
174 #define PIN_BANK(id, pins, label) \
187 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
193 { .type = iom0, .offset = -1 }, \
194 { .type = iom1, .offset = -1 }, \
195 { .type = iom2, .offset = -1 }, \
196 { .type = iom3, .offset = -1 }, \
200 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
212 { .drv_type = type0, .offset = -1 }, \
213 { .drv_type = type1, .offset = -1 }, \
214 { .drv_type = type2, .offset = -1 }, \
215 { .drv_type = type3, .offset = -1 }, \
219 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
220 drv2, drv3, pull0, pull1, \
233 { .drv_type = drv0, .offset = -1 }, \
234 { .drv_type = drv1, .offset = -1 }, \
235 { .drv_type = drv2, .offset = -1 }, \
236 { .drv_type = drv3, .offset = -1 }, \
238 .pull_type[0] = pull0, \
239 .pull_type[1] = pull1, \
240 .pull_type[2] = pull2, \
241 .pull_type[3] = pull3, \
244 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
245 iom2, iom3, drv0, drv1, drv2, \
246 drv3, offset0, offset1, \
253 { .type = iom0, .offset = -1 }, \
254 { .type = iom1, .offset = -1 }, \
255 { .type = iom2, .offset = -1 }, \
256 { .type = iom3, .offset = -1 }, \
259 { .drv_type = drv0, .offset = offset0 }, \
260 { .drv_type = drv1, .offset = offset1 }, \
261 { .drv_type = drv2, .offset = offset2 }, \
262 { .drv_type = drv3, .offset = offset3 }, \
266 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
267 label, iom0, iom1, iom2, \
268 iom3, drv0, drv1, drv2, \
269 drv3, offset0, offset1, \
270 offset2, offset3, pull0, \
271 pull1, pull2, pull3) \
277 { .type = iom0, .offset = -1 }, \
278 { .type = iom1, .offset = -1 }, \
279 { .type = iom2, .offset = -1 }, \
280 { .type = iom3, .offset = -1 }, \
283 { .drv_type = drv0, .offset = offset0 }, \
284 { .drv_type = drv1, .offset = offset1 }, \
285 { .drv_type = drv2, .offset = offset2 }, \
286 { .drv_type = drv3, .offset = offset3 }, \
288 .pull_type[0] = pull0, \
289 .pull_type[1] = pull1, \
290 .pull_type[2] = pull2, \
291 .pull_type[3] = pull3, \
295 * struct rockchip_mux_recalced_data: represent a pin iomux data.
298 * @bit: index at register.
299 * @reg: register offset.
302 struct rockchip_mux_recalced_data {
311 * struct rockchip_mux_recalced_data: represent a pin iomux data.
312 * @bank_num: bank number.
313 * @pin: index at register or used to calc index.
314 * @func: the min pin.
315 * @route_offset: the max pin.
316 * @route_val: the register offset.
318 struct rockchip_mux_route_data {
328 struct rockchip_pin_ctrl {
329 struct rockchip_pin_bank *pin_banks;
333 enum rockchip_pinctrl_type type;
338 struct rockchip_mux_recalced_data *iomux_recalced;
340 struct rockchip_mux_route_data *iomux_routes;
343 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
344 int pin_num, struct regmap **regmap,
346 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
347 int pin_num, struct regmap **regmap,
349 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
350 int pin_num, struct regmap **regmap,
354 struct rockchip_pin_config {
356 unsigned long *configs;
357 unsigned int nconfigs;
361 * struct rockchip_pin_group: represent group of pins of a pinmux function.
362 * @name: name of the pin group, used to lookup the group.
363 * @pins: the pins included in this group.
364 * @npins: number of pins included in this group.
365 * @func: the mux function number to be programmed when selected.
366 * @configs: the config values to be set for each pin
367 * @nconfigs: number of configs for each pin
369 struct rockchip_pin_group {
373 struct rockchip_pin_config *data;
377 * struct rockchip_pmx_func: represent a pin function.
378 * @name: name of the pin function, used to lookup the function.
379 * @groups: one or more names of pin groups that provide this function.
380 * @num_groups: number of groups included in @groups.
382 struct rockchip_pmx_func {
388 struct rockchip_pinctrl {
389 struct regmap *regmap_base;
391 struct regmap *regmap_pull;
392 struct regmap *regmap_pmu;
394 struct rockchip_pin_ctrl *ctrl;
395 struct pinctrl_desc pctl;
396 struct pinctrl_dev *pctl_dev;
397 struct rockchip_pin_group *groups;
398 unsigned int ngroups;
399 struct rockchip_pmx_func *functions;
400 unsigned int nfunctions;
403 static struct regmap_config rockchip_regmap_config = {
409 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
410 const struct rockchip_pinctrl *info,
415 for (i = 0; i < info->ngroups; i++) {
416 if (!strcmp(info->groups[i].name, name))
417 return &info->groups[i];
424 * given a pin number that is local to a pin controller, find out the pin bank
425 * and the register base of the pin bank.
427 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
430 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
432 while (pin >= (b->pin_base + b->nr_pins))
438 static struct rockchip_pin_bank *bank_num_to_bank(
439 struct rockchip_pinctrl *info,
442 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
445 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
446 if (b->bank_num == num)
450 return ERR_PTR(-EINVAL);
454 * Pinctrl_ops handling
457 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
459 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461 return info->ngroups;
464 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
467 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
469 return info->groups[selector].name;
472 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
473 unsigned selector, const unsigned **pins,
476 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
478 if (selector >= info->ngroups)
481 *pins = info->groups[selector].pins;
482 *npins = info->groups[selector].npins;
487 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
488 struct device_node *np,
489 struct pinctrl_map **map, unsigned *num_maps)
491 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
492 const struct rockchip_pin_group *grp;
493 struct pinctrl_map *new_map;
494 struct device_node *parent;
499 * first find the group of this node and check if we need to create
500 * config maps for pins
502 grp = pinctrl_name_to_group(info, np->name);
504 dev_err(info->dev, "unable to find group for node %s\n",
509 map_num += grp->npins;
511 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
519 parent = of_get_parent(np);
524 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
525 new_map[0].data.mux.function = parent->name;
526 new_map[0].data.mux.group = np->name;
529 /* create config map */
531 for (i = 0; i < grp->npins; i++) {
532 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
533 new_map[i].data.configs.group_or_pin =
534 pin_get_name(pctldev, grp->pins[i]);
535 new_map[i].data.configs.configs = grp->data[i].configs;
536 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
539 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
540 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
545 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
546 struct pinctrl_map *map, unsigned num_maps)
551 static const struct pinctrl_ops rockchip_pctrl_ops = {
552 .get_groups_count = rockchip_get_groups_count,
553 .get_group_name = rockchip_get_group_name,
554 .get_group_pins = rockchip_get_group_pins,
555 .dt_node_to_map = rockchip_dt_node_to_map,
556 .dt_free_map = rockchip_dt_free_map,
563 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
627 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
661 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
683 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
684 int *reg, u8 *bit, int *mask)
686 struct rockchip_pinctrl *info = bank->drvdata;
687 struct rockchip_pin_ctrl *ctrl = info->ctrl;
688 struct rockchip_mux_recalced_data *data;
691 for (i = 0; i < ctrl->niomux_recalced; i++) {
692 data = &ctrl->iomux_recalced[i];
693 if (data->num == bank->bank_num &&
698 if (i >= ctrl->niomux_recalced)
706 static struct rockchip_mux_route_data px30_mux_route_data[] = {
712 .route_offset = 0x184,
713 .route_val = BIT(16 + 7),
719 .route_offset = 0x184,
720 .route_val = BIT(16 + 7) | BIT(7),
726 .route_offset = 0x184,
727 .route_val = BIT(16 + 8),
733 .route_offset = 0x184,
734 .route_val = BIT(16 + 8) | BIT(8),
740 .route_offset = 0x184,
741 .route_val = BIT(16 + 10),
747 .route_offset = 0x184,
748 .route_val = BIT(16 + 10) | BIT(10),
754 .route_offset = 0x184,
755 .route_val = BIT(16 + 9),
761 .route_offset = 0x184,
762 .route_val = BIT(16 + 9) | BIT(9),
766 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
772 .route_offset = 0x144,
773 .route_val = BIT(16 + 3) | BIT(16 + 4),
779 .route_offset = 0x144,
780 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
786 .route_offset = 0x144,
787 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
793 .route_offset = 0x144,
794 .route_val = BIT(16 + 5),
800 .route_offset = 0x144,
801 .route_val = BIT(16 + 5) | BIT(5),
807 .route_offset = 0x144,
808 .route_val = BIT(16 + 6),
814 .route_offset = 0x144,
815 .route_val = BIT(16 + 6) | BIT(6),
819 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
825 .route_offset = 0x50,
826 .route_val = BIT(16),
832 .route_offset = 0x50,
833 .route_val = BIT(16) | BIT(0),
839 .route_offset = 0x50,
840 .route_val = BIT(16 + 1),
846 .route_offset = 0x50,
847 .route_val = BIT(16 + 1) | BIT(1),
853 .route_offset = 0x50,
854 .route_val = BIT(16 + 2),
860 .route_offset = 0x50,
861 .route_val = BIT(16 + 2) | BIT(2),
867 .route_offset = 0x50,
868 .route_val = BIT(16 + 3),
874 .route_offset = 0x50,
875 .route_val = BIT(16 + 3) | BIT(3),
881 .route_offset = 0x50,
882 .route_val = BIT(16 + 4),
888 .route_offset = 0x50,
889 .route_val = BIT(16 + 4) | BIT(4),
895 .route_offset = 0x50,
896 .route_val = BIT(16 + 5),
902 .route_offset = 0x50,
903 .route_val = BIT(16 + 5) | BIT(5),
909 .route_offset = 0x50,
910 .route_val = BIT(16 + 7),
916 .route_offset = 0x50,
917 .route_val = BIT(16 + 7) | BIT(7),
923 .route_offset = 0x50,
924 .route_val = BIT(16 + 8),
930 .route_offset = 0x50,
931 .route_val = BIT(16 + 8) | BIT(8),
937 .route_offset = 0x50,
938 .route_val = BIT(16 + 11),
944 .route_offset = 0x50,
945 .route_val = BIT(16 + 11) | BIT(11),
949 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
951 /* edphdmi_cecinoutt1 */
955 .route_offset = 0x264,
956 .route_val = BIT(16 + 12) | BIT(12),
958 /* edphdmi_cecinout */
962 .route_offset = 0x264,
963 .route_val = BIT(16 + 12),
967 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
973 .route_offset = 0x50,
974 .route_val = BIT(16) | BIT(16 + 1),
980 .route_offset = 0x50,
981 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
987 .route_offset = 0x50,
988 .route_val = BIT(16 + 2) | BIT(2),
990 /* gmac-m1-optimized_rxd3 */
994 .route_offset = 0x50,
995 .route_val = BIT(16 + 10) | BIT(10),
1001 .route_offset = 0x50,
1002 .route_val = BIT(16 + 3),
1008 .route_offset = 0x50,
1009 .route_val = BIT(16 + 3) | BIT(3),
1015 .route_offset = 0x50,
1016 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1022 .route_offset = 0x50,
1023 .route_val = BIT(16 + 6),
1029 .route_offset = 0x50,
1030 .route_val = BIT(16 + 6) | BIT(6),
1036 .route_offset = 0x50,
1037 .route_val = BIT(16 + 7) | BIT(7),
1043 .route_offset = 0x50,
1044 .route_val = BIT(16 + 8) | BIT(8),
1050 .route_offset = 0x50,
1051 .route_val = BIT(16 + 9) | BIT(9),
1055 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1061 .route_offset = 0xe21c,
1062 .route_val = BIT(16 + 10) | BIT(16 + 11),
1068 .route_offset = 0xe21c,
1069 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1075 .route_offset = 0xe21c,
1076 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1082 .route_offset = 0xe21c,
1083 .route_val = BIT(16 + 14),
1089 .route_offset = 0xe21c,
1090 .route_val = BIT(16 + 14) | BIT(14),
1094 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1095 int mux, u32 *reg, u32 *value)
1097 struct rockchip_pinctrl *info = bank->drvdata;
1098 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1099 struct rockchip_mux_route_data *data;
1102 for (i = 0; i < ctrl->niomux_routes; i++) {
1103 data = &ctrl->iomux_routes[i];
1104 if ((data->bank_num == bank->bank_num) &&
1105 (data->pin == pin) && (data->func == mux))
1109 if (i >= ctrl->niomux_routes)
1112 *reg = data->route_offset;
1113 *value = data->route_val;
1118 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1120 struct rockchip_pinctrl *info = bank->drvdata;
1121 int iomux_num = (pin / 8);
1122 struct regmap *regmap;
1124 int reg, ret, mask, mux_type;
1130 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1131 dev_err(info->dev, "pin %d is unrouted\n", pin);
1135 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1136 return RK_FUNC_GPIO;
1138 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1139 ? info->regmap_pmu : info->regmap_base;
1141 /* get basic quadrupel of mux registers and the correct reg inside */
1142 mux_type = bank->iomux[iomux_num].type;
1143 reg = bank->iomux[iomux_num].offset;
1144 if (mux_type & IOMUX_WIDTH_4BIT) {
1147 bit = (pin % 4) * 4;
1149 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1152 bit = (pin % 8 % 5) * 3;
1155 bit = (pin % 8) * 2;
1159 if (bank->recalced_mask & BIT(pin))
1160 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1162 ret = regmap_read(regmap, reg, &val);
1166 return ((val >> bit) & mask);
1169 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1172 struct rockchip_pinctrl *info = bank->drvdata;
1173 int iomux_num = (pin / 8);
1178 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1179 dev_err(info->dev, "pin %d is unrouted\n", pin);
1183 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1184 if (mux != RK_FUNC_GPIO) {
1186 "pin %d only supports a gpio mux\n", pin);
1195 * Set a new mux function for a pin.
1197 * The register is divided into the upper and lower 16 bit. When changing
1198 * a value, the previous register value is not read and changed. Instead
1199 * it seems the changed bits are marked in the upper 16 bit, while the
1200 * changed value gets set in the same offset in the lower 16 bit.
1201 * All pin settings seem to be 2 bit wide in both the upper and lower
1203 * @bank: pin bank to change
1204 * @pin: pin to change
1205 * @mux: new mux function to set
1207 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1209 struct rockchip_pinctrl *info = bank->drvdata;
1210 int iomux_num = (pin / 8);
1211 struct regmap *regmap;
1212 int reg, ret, mask, mux_type;
1214 u32 data, rmask, route_reg, route_val;
1216 ret = rockchip_verify_mux(bank, pin, mux);
1220 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1223 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1224 bank->bank_num, pin, mux);
1226 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1227 ? info->regmap_pmu : info->regmap_base;
1229 /* get basic quadrupel of mux registers and the correct reg inside */
1230 mux_type = bank->iomux[iomux_num].type;
1231 reg = bank->iomux[iomux_num].offset;
1232 if (mux_type & IOMUX_WIDTH_4BIT) {
1235 bit = (pin % 4) * 4;
1237 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1240 bit = (pin % 8 % 5) * 3;
1243 bit = (pin % 8) * 2;
1247 if (bank->recalced_mask & BIT(pin))
1248 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1250 if (bank->route_mask & BIT(pin)) {
1251 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1253 ret = regmap_write(regmap, route_reg, route_val);
1259 data = (mask << (bit + 16));
1260 rmask = data | (data >> 16);
1261 data |= (mux & mask) << bit;
1262 ret = regmap_update_bits(regmap, reg, rmask, data);
1267 #define PX30_PULL_PMU_OFFSET 0x10
1268 #define PX30_PULL_GRF_OFFSET 0x60
1269 #define PX30_PULL_BITS_PER_PIN 2
1270 #define PX30_PULL_PINS_PER_REG 8
1271 #define PX30_PULL_BANK_STRIDE 16
1273 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1274 int pin_num, struct regmap **regmap,
1277 struct rockchip_pinctrl *info = bank->drvdata;
1279 /* The first 32 pins of the first bank are located in PMU */
1280 if (bank->bank_num == 0) {
1281 *regmap = info->regmap_pmu;
1282 *reg = PX30_PULL_PMU_OFFSET;
1284 *regmap = info->regmap_base;
1285 *reg = PX30_PULL_GRF_OFFSET;
1287 /* correct the offset, as we're starting with the 2nd bank */
1289 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1292 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1293 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1294 *bit *= PX30_PULL_BITS_PER_PIN;
1297 #define PX30_DRV_PMU_OFFSET 0x20
1298 #define PX30_DRV_GRF_OFFSET 0xf0
1299 #define PX30_DRV_BITS_PER_PIN 2
1300 #define PX30_DRV_PINS_PER_REG 8
1301 #define PX30_DRV_BANK_STRIDE 16
1303 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1304 int pin_num, struct regmap **regmap,
1307 struct rockchip_pinctrl *info = bank->drvdata;
1309 /* The first 32 pins of the first bank are located in PMU */
1310 if (bank->bank_num == 0) {
1311 *regmap = info->regmap_pmu;
1312 *reg = PX30_DRV_PMU_OFFSET;
1314 *regmap = info->regmap_base;
1315 *reg = PX30_DRV_GRF_OFFSET;
1317 /* correct the offset, as we're starting with the 2nd bank */
1319 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1322 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1323 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1324 *bit *= PX30_DRV_BITS_PER_PIN;
1327 #define PX30_SCHMITT_PMU_OFFSET 0x38
1328 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1329 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1330 #define PX30_SCHMITT_BANK_STRIDE 16
1331 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1333 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1335 struct regmap **regmap,
1338 struct rockchip_pinctrl *info = bank->drvdata;
1341 if (bank->bank_num == 0) {
1342 *regmap = info->regmap_pmu;
1343 *reg = PX30_SCHMITT_PMU_OFFSET;
1344 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1346 *regmap = info->regmap_base;
1347 *reg = PX30_SCHMITT_GRF_OFFSET;
1348 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1349 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1352 *reg += ((pin_num / pins_per_reg) * 4);
1353 *bit = pin_num % pins_per_reg;
1358 #define RV1108_PULL_PMU_OFFSET 0x10
1359 #define RV1108_PULL_OFFSET 0x110
1360 #define RV1108_PULL_PINS_PER_REG 8
1361 #define RV1108_PULL_BITS_PER_PIN 2
1362 #define RV1108_PULL_BANK_STRIDE 16
1364 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1365 int pin_num, struct regmap **regmap,
1368 struct rockchip_pinctrl *info = bank->drvdata;
1370 /* The first 24 pins of the first bank are located in PMU */
1371 if (bank->bank_num == 0) {
1372 *regmap = info->regmap_pmu;
1373 *reg = RV1108_PULL_PMU_OFFSET;
1375 *reg = RV1108_PULL_OFFSET;
1376 *regmap = info->regmap_base;
1377 /* correct the offset, as we're starting with the 2nd bank */
1379 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1382 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1383 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1384 *bit *= RV1108_PULL_BITS_PER_PIN;
1387 #define RV1108_DRV_PMU_OFFSET 0x20
1388 #define RV1108_DRV_GRF_OFFSET 0x210
1389 #define RV1108_DRV_BITS_PER_PIN 2
1390 #define RV1108_DRV_PINS_PER_REG 8
1391 #define RV1108_DRV_BANK_STRIDE 16
1393 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1394 int pin_num, struct regmap **regmap,
1397 struct rockchip_pinctrl *info = bank->drvdata;
1399 /* The first 24 pins of the first bank are located in PMU */
1400 if (bank->bank_num == 0) {
1401 *regmap = info->regmap_pmu;
1402 *reg = RV1108_DRV_PMU_OFFSET;
1404 *regmap = info->regmap_base;
1405 *reg = RV1108_DRV_GRF_OFFSET;
1407 /* correct the offset, as we're starting with the 2nd bank */
1409 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1412 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1413 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1414 *bit *= RV1108_DRV_BITS_PER_PIN;
1417 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1418 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1419 #define RV1108_SCHMITT_BANK_STRIDE 8
1420 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1421 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1423 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1425 struct regmap **regmap,
1428 struct rockchip_pinctrl *info = bank->drvdata;
1431 if (bank->bank_num == 0) {
1432 *regmap = info->regmap_pmu;
1433 *reg = RV1108_SCHMITT_PMU_OFFSET;
1434 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1436 *regmap = info->regmap_base;
1437 *reg = RV1108_SCHMITT_GRF_OFFSET;
1438 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1439 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1441 *reg += ((pin_num / pins_per_reg) * 4);
1442 *bit = pin_num % pins_per_reg;
1447 #define RK2928_PULL_OFFSET 0x118
1448 #define RK2928_PULL_PINS_PER_REG 16
1449 #define RK2928_PULL_BANK_STRIDE 8
1451 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1452 int pin_num, struct regmap **regmap,
1455 struct rockchip_pinctrl *info = bank->drvdata;
1457 *regmap = info->regmap_base;
1458 *reg = RK2928_PULL_OFFSET;
1459 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1460 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1462 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1465 #define RK3128_PULL_OFFSET 0x118
1467 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1468 int pin_num, struct regmap **regmap,
1471 struct rockchip_pinctrl *info = bank->drvdata;
1473 *regmap = info->regmap_base;
1474 *reg = RK3128_PULL_OFFSET;
1475 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1476 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1478 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1481 #define RK3188_PULL_OFFSET 0x164
1482 #define RK3188_PULL_BITS_PER_PIN 2
1483 #define RK3188_PULL_PINS_PER_REG 8
1484 #define RK3188_PULL_BANK_STRIDE 16
1485 #define RK3188_PULL_PMU_OFFSET 0x64
1487 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1488 int pin_num, struct regmap **regmap,
1491 struct rockchip_pinctrl *info = bank->drvdata;
1493 /* The first 12 pins of the first bank are located elsewhere */
1494 if (bank->bank_num == 0 && pin_num < 12) {
1495 *regmap = info->regmap_pmu ? info->regmap_pmu
1496 : bank->regmap_pull;
1497 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1498 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1499 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1500 *bit *= RK3188_PULL_BITS_PER_PIN;
1502 *regmap = info->regmap_pull ? info->regmap_pull
1503 : info->regmap_base;
1504 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1506 /* correct the offset, as it is the 2nd pull register */
1508 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1509 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1512 * The bits in these registers have an inverse ordering
1513 * with the lowest pin being in bits 15:14 and the highest
1516 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1517 *bit *= RK3188_PULL_BITS_PER_PIN;
1521 #define RK3288_PULL_OFFSET 0x140
1522 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1523 int pin_num, struct regmap **regmap,
1526 struct rockchip_pinctrl *info = bank->drvdata;
1528 /* The first 24 pins of the first bank are located in PMU */
1529 if (bank->bank_num == 0) {
1530 *regmap = info->regmap_pmu;
1531 *reg = RK3188_PULL_PMU_OFFSET;
1533 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1534 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1535 *bit *= RK3188_PULL_BITS_PER_PIN;
1537 *regmap = info->regmap_base;
1538 *reg = RK3288_PULL_OFFSET;
1540 /* correct the offset, as we're starting with the 2nd bank */
1542 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1543 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1545 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1546 *bit *= RK3188_PULL_BITS_PER_PIN;
1550 #define RK3288_DRV_PMU_OFFSET 0x70
1551 #define RK3288_DRV_GRF_OFFSET 0x1c0
1552 #define RK3288_DRV_BITS_PER_PIN 2
1553 #define RK3288_DRV_PINS_PER_REG 8
1554 #define RK3288_DRV_BANK_STRIDE 16
1556 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1557 int pin_num, struct regmap **regmap,
1560 struct rockchip_pinctrl *info = bank->drvdata;
1562 /* The first 24 pins of the first bank are located in PMU */
1563 if (bank->bank_num == 0) {
1564 *regmap = info->regmap_pmu;
1565 *reg = RK3288_DRV_PMU_OFFSET;
1567 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1568 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1569 *bit *= RK3288_DRV_BITS_PER_PIN;
1571 *regmap = info->regmap_base;
1572 *reg = RK3288_DRV_GRF_OFFSET;
1574 /* correct the offset, as we're starting with the 2nd bank */
1576 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1577 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1579 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1580 *bit *= RK3288_DRV_BITS_PER_PIN;
1584 #define RK3228_PULL_OFFSET 0x100
1586 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1587 int pin_num, struct regmap **regmap,
1590 struct rockchip_pinctrl *info = bank->drvdata;
1592 *regmap = info->regmap_base;
1593 *reg = RK3228_PULL_OFFSET;
1594 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1595 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1597 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1598 *bit *= RK3188_PULL_BITS_PER_PIN;
1601 #define RK3228_DRV_GRF_OFFSET 0x200
1603 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1604 int pin_num, struct regmap **regmap,
1607 struct rockchip_pinctrl *info = bank->drvdata;
1609 *regmap = info->regmap_base;
1610 *reg = RK3228_DRV_GRF_OFFSET;
1611 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1612 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1614 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1615 *bit *= RK3288_DRV_BITS_PER_PIN;
1618 #define RK3368_PULL_GRF_OFFSET 0x100
1619 #define RK3368_PULL_PMU_OFFSET 0x10
1621 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1622 int pin_num, struct regmap **regmap,
1625 struct rockchip_pinctrl *info = bank->drvdata;
1627 /* The first 32 pins of the first bank are located in PMU */
1628 if (bank->bank_num == 0) {
1629 *regmap = info->regmap_pmu;
1630 *reg = RK3368_PULL_PMU_OFFSET;
1632 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1633 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1634 *bit *= RK3188_PULL_BITS_PER_PIN;
1636 *regmap = info->regmap_base;
1637 *reg = RK3368_PULL_GRF_OFFSET;
1639 /* correct the offset, as we're starting with the 2nd bank */
1641 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1642 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1644 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1645 *bit *= RK3188_PULL_BITS_PER_PIN;
1649 #define RK3368_DRV_PMU_OFFSET 0x20
1650 #define RK3368_DRV_GRF_OFFSET 0x200
1652 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1653 int pin_num, struct regmap **regmap,
1656 struct rockchip_pinctrl *info = bank->drvdata;
1658 /* The first 32 pins of the first bank are located in PMU */
1659 if (bank->bank_num == 0) {
1660 *regmap = info->regmap_pmu;
1661 *reg = RK3368_DRV_PMU_OFFSET;
1663 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1664 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1665 *bit *= RK3288_DRV_BITS_PER_PIN;
1667 *regmap = info->regmap_base;
1668 *reg = RK3368_DRV_GRF_OFFSET;
1670 /* correct the offset, as we're starting with the 2nd bank */
1672 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1673 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1675 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1676 *bit *= RK3288_DRV_BITS_PER_PIN;
1680 #define RK3399_PULL_GRF_OFFSET 0xe040
1681 #define RK3399_PULL_PMU_OFFSET 0x40
1682 #define RK3399_DRV_3BITS_PER_PIN 3
1684 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1685 int pin_num, struct regmap **regmap,
1688 struct rockchip_pinctrl *info = bank->drvdata;
1690 /* The bank0:16 and bank1:32 pins are located in PMU */
1691 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1692 *regmap = info->regmap_pmu;
1693 *reg = RK3399_PULL_PMU_OFFSET;
1695 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1697 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1698 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1699 *bit *= RK3188_PULL_BITS_PER_PIN;
1701 *regmap = info->regmap_base;
1702 *reg = RK3399_PULL_GRF_OFFSET;
1704 /* correct the offset, as we're starting with the 3rd bank */
1706 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1707 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1709 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1710 *bit *= RK3188_PULL_BITS_PER_PIN;
1714 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1715 int pin_num, struct regmap **regmap,
1718 struct rockchip_pinctrl *info = bank->drvdata;
1719 int drv_num = (pin_num / 8);
1721 /* The bank0:16 and bank1:32 pins are located in PMU */
1722 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1723 *regmap = info->regmap_pmu;
1725 *regmap = info->regmap_base;
1727 *reg = bank->drv[drv_num].offset;
1728 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1729 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1730 *bit = (pin_num % 8) * 3;
1732 *bit = (pin_num % 8) * 2;
1735 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1736 { 2, 4, 8, 12, -1, -1, -1, -1 },
1737 { 3, 6, 9, 12, -1, -1, -1, -1 },
1738 { 5, 10, 15, 20, -1, -1, -1, -1 },
1739 { 4, 6, 8, 10, 12, 14, 16, 18 },
1740 { 4, 7, 10, 13, 16, 19, 22, 26 }
1743 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1746 struct rockchip_pinctrl *info = bank->drvdata;
1747 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1748 struct regmap *regmap;
1750 u32 data, temp, rmask_bits;
1752 int drv_type = bank->drv[pin_num / 8].drv_type;
1754 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1757 case DRV_TYPE_IO_1V8_3V0_AUTO:
1758 case DRV_TYPE_IO_3V3_ONLY:
1759 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1762 /* regular case, nothing to do */
1766 * drive-strength offset is special, as it is
1767 * spread over 2 registers
1769 ret = regmap_read(regmap, reg, &data);
1773 ret = regmap_read(regmap, reg + 0x4, &temp);
1778 * the bit data[15] contains bit 0 of the value
1779 * while temp[1:0] contains bits 2 and 1
1786 return rockchip_perpin_drv_list[drv_type][data];
1788 /* setting fully enclosed in the second register */
1793 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1799 case DRV_TYPE_IO_DEFAULT:
1800 case DRV_TYPE_IO_1V8_OR_3V0:
1801 case DRV_TYPE_IO_1V8_ONLY:
1802 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1805 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1810 ret = regmap_read(regmap, reg, &data);
1815 data &= (1 << rmask_bits) - 1;
1817 return rockchip_perpin_drv_list[drv_type][data];
1820 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1821 int pin_num, int strength)
1823 struct rockchip_pinctrl *info = bank->drvdata;
1824 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1825 struct regmap *regmap;
1827 u32 data, rmask, rmask_bits, temp;
1829 int drv_type = bank->drv[pin_num / 8].drv_type;
1831 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1832 bank->bank_num, pin_num, strength);
1834 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1837 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1838 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1841 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1842 ret = rockchip_perpin_drv_list[drv_type][i];
1848 dev_err(info->dev, "unsupported driver strength %d\n",
1854 case DRV_TYPE_IO_1V8_3V0_AUTO:
1855 case DRV_TYPE_IO_3V3_ONLY:
1856 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1859 /* regular case, nothing to do */
1863 * drive-strength offset is special, as it is spread
1864 * over 2 registers, the bit data[15] contains bit 0
1865 * of the value while temp[1:0] contains bits 2 and 1
1867 data = (ret & 0x1) << 15;
1868 temp = (ret >> 0x1) & 0x3;
1870 rmask = BIT(15) | BIT(31);
1872 ret = regmap_update_bits(regmap, reg, rmask, data);
1876 rmask = 0x3 | (0x3 << 16);
1877 temp |= (0x3 << 16);
1879 ret = regmap_update_bits(regmap, reg, rmask, temp);
1883 /* setting fully enclosed in the second register */
1888 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1893 case DRV_TYPE_IO_DEFAULT:
1894 case DRV_TYPE_IO_1V8_OR_3V0:
1895 case DRV_TYPE_IO_1V8_ONLY:
1896 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1899 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1904 /* enable the write to the equivalent lower bits */
1905 data = ((1 << rmask_bits) - 1) << (bit + 16);
1906 rmask = data | (data >> 16);
1907 data |= (ret << bit);
1909 ret = regmap_update_bits(regmap, reg, rmask, data);
1914 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1916 PIN_CONFIG_BIAS_DISABLE,
1917 PIN_CONFIG_BIAS_PULL_UP,
1918 PIN_CONFIG_BIAS_PULL_DOWN,
1919 PIN_CONFIG_BIAS_BUS_HOLD
1922 PIN_CONFIG_BIAS_DISABLE,
1923 PIN_CONFIG_BIAS_PULL_DOWN,
1924 PIN_CONFIG_BIAS_DISABLE,
1925 PIN_CONFIG_BIAS_PULL_UP
1929 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1931 struct rockchip_pinctrl *info = bank->drvdata;
1932 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1933 struct regmap *regmap;
1934 int reg, ret, pull_type;
1938 /* rk3066b does support any pulls */
1939 if (ctrl->type == RK3066B)
1940 return PIN_CONFIG_BIAS_DISABLE;
1942 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1944 ret = regmap_read(regmap, reg, &data);
1948 switch (ctrl->type) {
1951 return !(data & BIT(bit))
1952 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1953 : PIN_CONFIG_BIAS_DISABLE;
1960 pull_type = bank->pull_type[pin_num / 8];
1962 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1964 return rockchip_pull_list[pull_type][data];
1966 dev_err(info->dev, "unsupported pinctrl type\n");
1971 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1972 int pin_num, int pull)
1974 struct rockchip_pinctrl *info = bank->drvdata;
1975 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1976 struct regmap *regmap;
1977 int reg, ret, i, pull_type;
1981 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1982 bank->bank_num, pin_num, pull);
1984 /* rk3066b does support any pulls */
1985 if (ctrl->type == RK3066B)
1986 return pull ? -EINVAL : 0;
1988 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1990 switch (ctrl->type) {
1993 data = BIT(bit + 16);
1994 if (pull == PIN_CONFIG_BIAS_DISABLE)
1996 ret = regmap_write(regmap, reg, data);
2004 pull_type = bank->pull_type[pin_num / 8];
2006 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2008 if (rockchip_pull_list[pull_type][i] == pull) {
2015 dev_err(info->dev, "unsupported pull setting %d\n",
2020 /* enable the write to the equivalent lower bits */
2021 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2022 rmask = data | (data >> 16);
2023 data |= (ret << bit);
2025 ret = regmap_update_bits(regmap, reg, rmask, data);
2028 dev_err(info->dev, "unsupported pinctrl type\n");
2035 #define RK3328_SCHMITT_BITS_PER_PIN 1
2036 #define RK3328_SCHMITT_PINS_PER_REG 16
2037 #define RK3328_SCHMITT_BANK_STRIDE 8
2038 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2040 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2042 struct regmap **regmap,
2045 struct rockchip_pinctrl *info = bank->drvdata;
2047 *regmap = info->regmap_base;
2048 *reg = RK3328_SCHMITT_GRF_OFFSET;
2050 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2051 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2052 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2057 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2059 struct rockchip_pinctrl *info = bank->drvdata;
2060 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2061 struct regmap *regmap;
2066 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2070 ret = regmap_read(regmap, reg, &data);
2078 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2079 int pin_num, int enable)
2081 struct rockchip_pinctrl *info = bank->drvdata;
2082 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2083 struct regmap *regmap;
2088 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2089 bank->bank_num, pin_num, enable);
2091 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2095 /* enable the write to the equivalent lower bits */
2096 data = BIT(bit + 16) | (enable << bit);
2097 rmask = BIT(bit + 16) | BIT(bit);
2099 return regmap_update_bits(regmap, reg, rmask, data);
2103 * Pinmux_ops handling
2106 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2108 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2110 return info->nfunctions;
2113 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2116 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2118 return info->functions[selector].name;
2121 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2122 unsigned selector, const char * const **groups,
2123 unsigned * const num_groups)
2125 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2127 *groups = info->functions[selector].groups;
2128 *num_groups = info->functions[selector].ngroups;
2133 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2136 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2137 const unsigned int *pins = info->groups[group].pins;
2138 const struct rockchip_pin_config *data = info->groups[group].data;
2139 struct rockchip_pin_bank *bank;
2142 dev_dbg(info->dev, "enable function %s group %s\n",
2143 info->functions[selector].name, info->groups[group].name);
2146 * for each pin in the pin group selected, program the corresponding
2147 * pin function number in the config register.
2149 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2150 bank = pin_to_bank(info, pins[cnt]);
2151 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2158 /* revert the already done pin settings */
2159 for (cnt--; cnt >= 0; cnt--)
2160 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2168 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2170 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2174 ret = clk_enable(bank->clk);
2176 dev_err(bank->drvdata->dev,
2177 "failed to enable clock for bank %s\n", bank->name);
2180 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2181 clk_disable(bank->clk);
2183 return !(data & BIT(offset));
2187 * The calls to gpio_direction_output() and gpio_direction_input()
2188 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2189 * function called from the gpiolib interface).
2191 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2192 int pin, bool input)
2194 struct rockchip_pin_bank *bank;
2196 unsigned long flags;
2199 bank = gpiochip_get_data(chip);
2201 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2205 clk_enable(bank->clk);
2206 raw_spin_lock_irqsave(&bank->slock, flags);
2208 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2209 /* set bit to 1 for output, 0 for input */
2214 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2216 raw_spin_unlock_irqrestore(&bank->slock, flags);
2217 clk_disable(bank->clk);
2222 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2223 struct pinctrl_gpio_range *range,
2224 unsigned offset, bool input)
2226 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2227 struct gpio_chip *chip;
2231 pin = offset - chip->base;
2232 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2233 offset, range->name, pin, input ? "input" : "output");
2235 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2239 static const struct pinmux_ops rockchip_pmx_ops = {
2240 .get_functions_count = rockchip_pmx_get_funcs_count,
2241 .get_function_name = rockchip_pmx_get_func_name,
2242 .get_function_groups = rockchip_pmx_get_groups,
2243 .set_mux = rockchip_pmx_set,
2244 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2248 * Pinconf_ops handling
2251 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2252 enum pin_config_param pull)
2254 switch (ctrl->type) {
2257 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2258 pull == PIN_CONFIG_BIAS_DISABLE);
2260 return pull ? false : true;
2267 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2273 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2274 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2276 /* set the pin config settings for a specified pin */
2277 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2278 unsigned long *configs, unsigned num_configs)
2280 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2281 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2282 enum pin_config_param param;
2287 for (i = 0; i < num_configs; i++) {
2288 param = pinconf_to_config_param(configs[i]);
2289 arg = pinconf_to_config_argument(configs[i]);
2292 case PIN_CONFIG_BIAS_DISABLE:
2293 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2298 case PIN_CONFIG_BIAS_PULL_UP:
2299 case PIN_CONFIG_BIAS_PULL_DOWN:
2300 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2301 case PIN_CONFIG_BIAS_BUS_HOLD:
2302 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2308 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2313 case PIN_CONFIG_OUTPUT:
2314 rockchip_gpio_set(&bank->gpio_chip,
2315 pin - bank->pin_base, arg);
2316 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2317 pin - bank->pin_base, false);
2321 case PIN_CONFIG_DRIVE_STRENGTH:
2322 /* rk3288 is the first with per-pin drive-strength */
2323 if (!info->ctrl->drv_calc_reg)
2326 rc = rockchip_set_drive_perpin(bank,
2327 pin - bank->pin_base, arg);
2331 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2332 if (!info->ctrl->schmitt_calc_reg)
2335 rc = rockchip_set_schmitt(bank,
2336 pin - bank->pin_base, arg);
2344 } /* for each config */
2349 /* get the pin config settings for a specified pin */
2350 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2351 unsigned long *config)
2353 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2354 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2355 enum pin_config_param param = pinconf_to_config_param(*config);
2360 case PIN_CONFIG_BIAS_DISABLE:
2361 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2366 case PIN_CONFIG_BIAS_PULL_UP:
2367 case PIN_CONFIG_BIAS_PULL_DOWN:
2368 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2369 case PIN_CONFIG_BIAS_BUS_HOLD:
2370 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2373 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2378 case PIN_CONFIG_OUTPUT:
2379 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2380 if (rc != RK_FUNC_GPIO)
2383 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2389 case PIN_CONFIG_DRIVE_STRENGTH:
2390 /* rk3288 is the first with per-pin drive-strength */
2391 if (!info->ctrl->drv_calc_reg)
2394 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2400 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2401 if (!info->ctrl->schmitt_calc_reg)
2404 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2415 *config = pinconf_to_config_packed(param, arg);
2420 static const struct pinconf_ops rockchip_pinconf_ops = {
2421 .pin_config_get = rockchip_pinconf_get,
2422 .pin_config_set = rockchip_pinconf_set,
2426 static const struct of_device_id rockchip_bank_match[] = {
2427 { .compatible = "rockchip,gpio-bank" },
2428 { .compatible = "rockchip,rk3188-gpio-bank0" },
2432 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2433 struct device_node *np)
2435 struct device_node *child;
2437 for_each_child_of_node(np, child) {
2438 if (of_match_node(rockchip_bank_match, child))
2442 info->ngroups += of_get_child_count(child);
2446 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2447 struct rockchip_pin_group *grp,
2448 struct rockchip_pinctrl *info,
2451 struct rockchip_pin_bank *bank;
2458 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2460 /* Initialise group */
2461 grp->name = np->name;
2464 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2465 * do sanity check and calculate pins number
2467 list = of_get_property(np, "rockchip,pins", &size);
2468 /* we do not check return since it's safe node passed down */
2469 size /= sizeof(*list);
2470 if (!size || size % 4) {
2471 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2475 grp->npins = size / 4;
2477 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2479 grp->data = devm_kcalloc(info->dev,
2481 sizeof(struct rockchip_pin_config),
2483 if (!grp->pins || !grp->data)
2486 for (i = 0, j = 0; i < size; i += 4, j++) {
2487 const __be32 *phandle;
2488 struct device_node *np_config;
2490 num = be32_to_cpu(*list++);
2491 bank = bank_num_to_bank(info, num);
2493 return PTR_ERR(bank);
2495 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2496 grp->data[j].func = be32_to_cpu(*list++);
2502 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2503 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2504 &grp->data[j].configs, &grp->data[j].nconfigs);
2512 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2513 struct rockchip_pinctrl *info,
2516 struct device_node *child;
2517 struct rockchip_pmx_func *func;
2518 struct rockchip_pin_group *grp;
2520 static u32 grp_index;
2523 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2525 func = &info->functions[index];
2527 /* Initialise function */
2528 func->name = np->name;
2529 func->ngroups = of_get_child_count(np);
2530 if (func->ngroups <= 0)
2533 func->groups = devm_kcalloc(info->dev,
2534 func->ngroups, sizeof(char *), GFP_KERNEL);
2538 for_each_child_of_node(np, child) {
2539 func->groups[i] = child->name;
2540 grp = &info->groups[grp_index++];
2541 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2551 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2552 struct rockchip_pinctrl *info)
2554 struct device *dev = &pdev->dev;
2555 struct device_node *np = dev->of_node;
2556 struct device_node *child;
2560 rockchip_pinctrl_child_count(info, np);
2562 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2563 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2565 info->functions = devm_kcalloc(dev,
2567 sizeof(struct rockchip_pmx_func),
2569 if (!info->functions)
2572 info->groups = devm_kcalloc(dev,
2574 sizeof(struct rockchip_pin_group),
2581 for_each_child_of_node(np, child) {
2582 if (of_match_node(rockchip_bank_match, child))
2585 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2587 dev_err(&pdev->dev, "failed to parse function\n");
2596 static int rockchip_pinctrl_register(struct platform_device *pdev,
2597 struct rockchip_pinctrl *info)
2599 struct pinctrl_desc *ctrldesc = &info->pctl;
2600 struct pinctrl_pin_desc *pindesc, *pdesc;
2601 struct rockchip_pin_bank *pin_bank;
2605 ctrldesc->name = "rockchip-pinctrl";
2606 ctrldesc->owner = THIS_MODULE;
2607 ctrldesc->pctlops = &rockchip_pctrl_ops;
2608 ctrldesc->pmxops = &rockchip_pmx_ops;
2609 ctrldesc->confops = &rockchip_pinconf_ops;
2611 pindesc = devm_kcalloc(&pdev->dev,
2612 info->ctrl->nr_pins, sizeof(*pindesc),
2617 ctrldesc->pins = pindesc;
2618 ctrldesc->npins = info->ctrl->nr_pins;
2621 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2622 pin_bank = &info->ctrl->pin_banks[bank];
2623 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2625 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2626 pin_bank->name, pin);
2631 ret = rockchip_pinctrl_parse_dt(pdev, info);
2635 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2636 if (IS_ERR(info->pctl_dev)) {
2637 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2638 return PTR_ERR(info->pctl_dev);
2641 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2642 pin_bank = &info->ctrl->pin_banks[bank];
2643 pin_bank->grange.name = pin_bank->name;
2644 pin_bank->grange.id = bank;
2645 pin_bank->grange.pin_base = pin_bank->pin_base;
2646 pin_bank->grange.base = pin_bank->gpio_chip.base;
2647 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2648 pin_bank->grange.gc = &pin_bank->gpio_chip;
2649 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2659 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2661 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2662 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2663 unsigned long flags;
2666 clk_enable(bank->clk);
2667 raw_spin_lock_irqsave(&bank->slock, flags);
2670 data &= ~BIT(offset);
2672 data |= BIT(offset);
2675 raw_spin_unlock_irqrestore(&bank->slock, flags);
2676 clk_disable(bank->clk);
2680 * Returns the level of the pin for input direction and setting of the DR
2681 * register for output gpios.
2683 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2685 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2688 clk_enable(bank->clk);
2689 data = readl(bank->reg_base + GPIO_EXT_PORT);
2690 clk_disable(bank->clk);
2697 * gpiolib gpio_direction_input callback function. The setting of the pin
2698 * mux function as 'gpio input' will be handled by the pinctrl subsystem
2701 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2703 return pinctrl_gpio_direction_input(gc->base + offset);
2707 * gpiolib gpio_direction_output callback function. The setting of the pin
2708 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2711 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2712 unsigned offset, int value)
2714 rockchip_gpio_set(gc, offset, value);
2715 return pinctrl_gpio_direction_output(gc->base + offset);
2718 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2719 unsigned int offset, bool enable)
2721 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2722 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2723 unsigned long flags;
2726 clk_enable(bank->clk);
2727 raw_spin_lock_irqsave(&bank->slock, flags);
2731 data |= BIT(offset);
2733 data &= ~BIT(offset);
2736 raw_spin_unlock_irqrestore(&bank->slock, flags);
2737 clk_disable(bank->clk);
2741 * gpiolib set_config callback function. The setting of the pin
2742 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2745 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2746 unsigned long config)
2748 enum pin_config_param param = pinconf_to_config_param(config);
2751 case PIN_CONFIG_INPUT_DEBOUNCE:
2752 rockchip_gpio_set_debounce(gc, offset, true);
2754 * Rockchip's gpio could only support up to one period
2755 * of the debounce clock(pclk), which is far away from
2756 * satisftying the requirement, as pclk is usually near
2757 * 100MHz shared by all peripherals. So the fact is it
2758 * has crippled debounce capability could only be useful
2759 * to prevent any spurious glitches from waking up the system
2760 * if the gpio is conguired as wakeup interrupt source. Let's
2761 * still return -ENOTSUPP as before, to make sure the caller
2762 * of gpiod_set_debounce won't change its behaviour.
2770 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2771 * and a virtual IRQ, if not already present.
2773 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2775 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2781 clk_enable(bank->clk);
2782 virq = irq_create_mapping(bank->domain, offset);
2783 clk_disable(bank->clk);
2785 return (virq) ? : -ENXIO;
2788 static const struct gpio_chip rockchip_gpiolib_chip = {
2789 .request = gpiochip_generic_request,
2790 .free = gpiochip_generic_free,
2791 .set = rockchip_gpio_set,
2792 .get = rockchip_gpio_get,
2793 .get_direction = rockchip_gpio_get_direction,
2794 .direction_input = rockchip_gpio_direction_input,
2795 .direction_output = rockchip_gpio_direction_output,
2796 .set_config = rockchip_gpio_set_config,
2797 .to_irq = rockchip_gpio_to_irq,
2798 .owner = THIS_MODULE,
2802 * Interrupt handling
2805 static void rockchip_irq_demux(struct irq_desc *desc)
2807 struct irq_chip *chip = irq_desc_get_chip(desc);
2808 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2811 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2813 chained_irq_enter(chip, desc);
2815 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2818 unsigned int irq, virq;
2822 virq = irq_linear_revmap(bank->domain, irq);
2825 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2829 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2832 * Triggering IRQ on both rising and falling edge
2833 * needs manual intervention.
2835 if (bank->toggle_edge_mode & BIT(irq)) {
2836 u32 data, data_old, polarity;
2837 unsigned long flags;
2839 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2841 raw_spin_lock_irqsave(&bank->slock, flags);
2843 polarity = readl_relaxed(bank->reg_base +
2845 if (data & BIT(irq))
2846 polarity &= ~BIT(irq);
2848 polarity |= BIT(irq);
2850 bank->reg_base + GPIO_INT_POLARITY);
2852 raw_spin_unlock_irqrestore(&bank->slock, flags);
2855 data = readl_relaxed(bank->reg_base +
2857 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2860 generic_handle_irq(virq);
2863 chained_irq_exit(chip, desc);
2866 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2868 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2869 struct rockchip_pin_bank *bank = gc->private;
2870 u32 mask = BIT(d->hwirq);
2874 unsigned long flags;
2877 /* make sure the pin is configured as gpio input */
2878 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2882 clk_enable(bank->clk);
2883 raw_spin_lock_irqsave(&bank->slock, flags);
2885 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2887 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2889 raw_spin_unlock_irqrestore(&bank->slock, flags);
2891 if (type & IRQ_TYPE_EDGE_BOTH)
2892 irq_set_handler_locked(d, handle_edge_irq);
2894 irq_set_handler_locked(d, handle_level_irq);
2896 raw_spin_lock_irqsave(&bank->slock, flags);
2899 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2900 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2903 case IRQ_TYPE_EDGE_BOTH:
2904 bank->toggle_edge_mode |= mask;
2908 * Determine gpio state. If 1 next interrupt should be falling
2911 data = readl(bank->reg_base + GPIO_EXT_PORT);
2917 case IRQ_TYPE_EDGE_RISING:
2918 bank->toggle_edge_mode &= ~mask;
2922 case IRQ_TYPE_EDGE_FALLING:
2923 bank->toggle_edge_mode &= ~mask;
2927 case IRQ_TYPE_LEVEL_HIGH:
2928 bank->toggle_edge_mode &= ~mask;
2932 case IRQ_TYPE_LEVEL_LOW:
2933 bank->toggle_edge_mode &= ~mask;
2939 raw_spin_unlock_irqrestore(&bank->slock, flags);
2940 clk_disable(bank->clk);
2944 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2945 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2948 raw_spin_unlock_irqrestore(&bank->slock, flags);
2949 clk_disable(bank->clk);
2954 static void rockchip_irq_suspend(struct irq_data *d)
2956 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2957 struct rockchip_pin_bank *bank = gc->private;
2959 clk_enable(bank->clk);
2960 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2961 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2962 clk_disable(bank->clk);
2965 static void rockchip_irq_resume(struct irq_data *d)
2967 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2968 struct rockchip_pin_bank *bank = gc->private;
2970 clk_enable(bank->clk);
2971 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2972 clk_disable(bank->clk);
2975 static void rockchip_irq_enable(struct irq_data *d)
2977 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2978 struct rockchip_pin_bank *bank = gc->private;
2980 clk_enable(bank->clk);
2981 irq_gc_mask_clr_bit(d);
2984 static void rockchip_irq_disable(struct irq_data *d)
2986 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2987 struct rockchip_pin_bank *bank = gc->private;
2989 irq_gc_mask_set_bit(d);
2990 clk_disable(bank->clk);
2993 static int rockchip_interrupts_register(struct platform_device *pdev,
2994 struct rockchip_pinctrl *info)
2996 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2997 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2998 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2999 struct irq_chip_generic *gc;
3003 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3005 dev_warn(&pdev->dev, "bank %s is not valid\n",
3010 ret = clk_enable(bank->clk);
3012 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3017 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3018 &irq_generic_chip_ops, NULL);
3019 if (!bank->domain) {
3020 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3022 clk_disable(bank->clk);
3026 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3027 "rockchip_gpio_irq", handle_level_irq,
3028 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3030 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3032 irq_domain_remove(bank->domain);
3033 clk_disable(bank->clk);
3038 * Linux assumes that all interrupts start out disabled/masked.
3039 * Our driver only uses the concept of masked and always keeps
3040 * things enabled, so for us that's all masked and all enabled.
3042 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3043 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3045 gc = irq_get_domain_generic_chip(bank->domain, 0);
3046 gc->reg_base = bank->reg_base;
3048 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3049 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3050 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3051 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3052 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3053 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3054 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3055 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3056 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3057 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3058 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3059 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3061 irq_set_chained_handler_and_data(bank->irq,
3062 rockchip_irq_demux, bank);
3064 /* map the gpio irqs here, when the clock is still running */
3065 for (j = 0 ; j < 32 ; j++)
3066 irq_create_mapping(bank->domain, j);
3068 clk_disable(bank->clk);
3074 static int rockchip_gpiolib_register(struct platform_device *pdev,
3075 struct rockchip_pinctrl *info)
3077 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3078 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3079 struct gpio_chip *gc;
3083 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3085 dev_warn(&pdev->dev, "bank %s is not valid\n",
3090 bank->gpio_chip = rockchip_gpiolib_chip;
3092 gc = &bank->gpio_chip;
3093 gc->base = bank->pin_base;
3094 gc->ngpio = bank->nr_pins;
3095 gc->parent = &pdev->dev;
3096 gc->of_node = bank->of_node;
3097 gc->label = bank->name;
3099 ret = gpiochip_add_data(gc, bank);
3101 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3107 rockchip_interrupts_register(pdev, info);
3112 for (--i, --bank; i >= 0; --i, --bank) {
3115 gpiochip_remove(&bank->gpio_chip);
3120 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3121 struct rockchip_pinctrl *info)
3123 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3124 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3127 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3130 gpiochip_remove(&bank->gpio_chip);
3136 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3137 struct rockchip_pinctrl *info)
3139 struct resource res;
3142 if (of_address_to_resource(bank->of_node, 0, &res)) {
3143 dev_err(info->dev, "cannot find IO resource for bank\n");
3147 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3148 if (IS_ERR(bank->reg_base))
3149 return PTR_ERR(bank->reg_base);
3152 * special case, where parts of the pull setting-registers are
3153 * part of the PMU register space
3155 if (of_device_is_compatible(bank->of_node,
3156 "rockchip,rk3188-gpio-bank0")) {
3157 struct device_node *node;
3159 node = of_parse_phandle(bank->of_node->parent,
3162 if (of_address_to_resource(bank->of_node, 1, &res)) {
3163 dev_err(info->dev, "cannot find IO resource for bank\n");
3167 base = devm_ioremap_resource(info->dev, &res);
3169 return PTR_ERR(base);
3170 rockchip_regmap_config.max_register =
3171 resource_size(&res) - 4;
3172 rockchip_regmap_config.name =
3173 "rockchip,rk3188-gpio-bank0-pull";
3174 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3176 &rockchip_regmap_config);
3181 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3183 bank->clk = of_clk_get(bank->of_node, 0);
3184 if (IS_ERR(bank->clk))
3185 return PTR_ERR(bank->clk);
3187 return clk_prepare(bank->clk);
3190 static const struct of_device_id rockchip_pinctrl_dt_match[];
3192 /* retrieve the soc specific data */
3193 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3194 struct rockchip_pinctrl *d,
3195 struct platform_device *pdev)
3197 const struct of_device_id *match;
3198 struct device_node *node = pdev->dev.of_node;
3199 struct device_node *np;
3200 struct rockchip_pin_ctrl *ctrl;
3201 struct rockchip_pin_bank *bank;
3202 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3204 match = of_match_node(rockchip_pinctrl_dt_match, node);
3205 ctrl = (struct rockchip_pin_ctrl *)match->data;
3207 for_each_child_of_node(node, np) {
3208 if (!of_find_property(np, "gpio-controller", NULL))
3211 bank = ctrl->pin_banks;
3212 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3213 if (!strcmp(bank->name, np->name)) {
3216 if (!rockchip_get_bank_data(bank, d))
3224 grf_offs = ctrl->grf_mux_offset;
3225 pmu_offs = ctrl->pmu_mux_offset;
3226 drv_pmu_offs = ctrl->pmu_drv_offset;
3227 drv_grf_offs = ctrl->grf_drv_offset;
3228 bank = ctrl->pin_banks;
3229 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3232 raw_spin_lock_init(&bank->slock);
3234 bank->pin_base = ctrl->nr_pins;
3235 ctrl->nr_pins += bank->nr_pins;
3237 /* calculate iomux and drv offsets */
3238 for (j = 0; j < 4; j++) {
3239 struct rockchip_iomux *iom = &bank->iomux[j];
3240 struct rockchip_drv *drv = &bank->drv[j];
3243 if (bank_pins >= bank->nr_pins)
3246 /* preset iomux offset value, set new start value */
3247 if (iom->offset >= 0) {
3248 if (iom->type & IOMUX_SOURCE_PMU)
3249 pmu_offs = iom->offset;
3251 grf_offs = iom->offset;
3252 } else { /* set current iomux offset */
3253 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3254 pmu_offs : grf_offs;
3257 /* preset drv offset value, set new start value */
3258 if (drv->offset >= 0) {
3259 if (iom->type & IOMUX_SOURCE_PMU)
3260 drv_pmu_offs = drv->offset;
3262 drv_grf_offs = drv->offset;
3263 } else { /* set current drv offset */
3264 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3265 drv_pmu_offs : drv_grf_offs;
3268 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3269 i, j, iom->offset, drv->offset);
3272 * Increase offset according to iomux width.
3273 * 4bit iomux'es are spread over two registers.
3275 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3276 IOMUX_WIDTH_3BIT)) ? 8 : 4;
3277 if (iom->type & IOMUX_SOURCE_PMU)
3283 * Increase offset according to drv width.
3284 * 3bit drive-strenth'es are spread over two registers.
3286 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3287 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3292 if (iom->type & IOMUX_SOURCE_PMU)
3293 drv_pmu_offs += inc;
3295 drv_grf_offs += inc;
3300 /* calculate the per-bank recalced_mask */
3301 for (j = 0; j < ctrl->niomux_recalced; j++) {
3304 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3305 pin = ctrl->iomux_recalced[j].pin;
3306 bank->recalced_mask |= BIT(pin);
3310 /* calculate the per-bank route_mask */
3311 for (j = 0; j < ctrl->niomux_routes; j++) {
3314 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3315 pin = ctrl->iomux_routes[j].pin;
3316 bank->route_mask |= BIT(pin);
3324 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3325 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3327 static u32 rk3288_grf_gpio6c_iomux;
3329 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3331 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3332 int ret = pinctrl_force_sleep(info->pctl_dev);
3338 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3339 * the setting here, and restore it at resume.
3341 if (info->ctrl->type == RK3288) {
3342 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3343 &rk3288_grf_gpio6c_iomux);
3345 pinctrl_force_default(info->pctl_dev);
3353 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3355 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3358 if (info->ctrl->type == RK3288) {
3359 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3360 rk3288_grf_gpio6c_iomux |
3361 GPIO6C6_SEL_WRITE_ENABLE);
3366 return pinctrl_force_default(info->pctl_dev);
3369 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3370 rockchip_pinctrl_resume);
3372 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3374 struct rockchip_pinctrl *info;
3375 struct device *dev = &pdev->dev;
3376 struct rockchip_pin_ctrl *ctrl;
3377 struct device_node *np = pdev->dev.of_node, *node;
3378 struct resource *res;
3382 if (!dev->of_node) {
3383 dev_err(dev, "device tree node not found\n");
3387 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3393 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3395 dev_err(dev, "driver data not available\n");
3400 node = of_parse_phandle(np, "rockchip,grf", 0);
3402 info->regmap_base = syscon_node_to_regmap(node);
3403 if (IS_ERR(info->regmap_base))
3404 return PTR_ERR(info->regmap_base);
3406 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3407 base = devm_ioremap_resource(&pdev->dev, res);
3409 return PTR_ERR(base);
3411 rockchip_regmap_config.max_register = resource_size(res) - 4;
3412 rockchip_regmap_config.name = "rockchip,pinctrl";
3413 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3414 &rockchip_regmap_config);
3416 /* to check for the old dt-bindings */
3417 info->reg_size = resource_size(res);
3419 /* Honor the old binding, with pull registers as 2nd resource */
3420 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3421 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3422 base = devm_ioremap_resource(&pdev->dev, res);
3424 return PTR_ERR(base);
3426 rockchip_regmap_config.max_register =
3427 resource_size(res) - 4;
3428 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3429 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3431 &rockchip_regmap_config);
3435 /* try to find the optional reference to the pmu syscon */
3436 node = of_parse_phandle(np, "rockchip,pmu", 0);
3438 info->regmap_pmu = syscon_node_to_regmap(node);
3439 if (IS_ERR(info->regmap_pmu))
3440 return PTR_ERR(info->regmap_pmu);
3443 ret = rockchip_gpiolib_register(pdev, info);
3447 ret = rockchip_pinctrl_register(pdev, info);
3449 rockchip_gpiolib_unregister(pdev, info);
3453 platform_set_drvdata(pdev, info);
3458 static struct rockchip_pin_bank px30_pin_banks[] = {
3459 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3464 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3469 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3474 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3481 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3482 .pin_banks = px30_pin_banks,
3483 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3484 .label = "PX30-GPIO",
3486 .grf_mux_offset = 0x0,
3487 .pmu_mux_offset = 0x0,
3488 .iomux_routes = px30_mux_route_data,
3489 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3490 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3491 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3492 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3495 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3496 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3500 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3501 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3502 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3505 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3506 .pin_banks = rv1108_pin_banks,
3507 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3508 .label = "RV1108-GPIO",
3510 .grf_mux_offset = 0x10,
3511 .pmu_mux_offset = 0x0,
3512 .iomux_recalced = rv1108_mux_recalced_data,
3513 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3514 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3515 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3516 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3519 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3520 PIN_BANK(0, 32, "gpio0"),
3521 PIN_BANK(1, 32, "gpio1"),
3522 PIN_BANK(2, 32, "gpio2"),
3523 PIN_BANK(3, 32, "gpio3"),
3526 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3527 .pin_banks = rk2928_pin_banks,
3528 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3529 .label = "RK2928-GPIO",
3531 .grf_mux_offset = 0xa8,
3532 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3535 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3536 PIN_BANK(0, 32, "gpio0"),
3537 PIN_BANK(1, 32, "gpio1"),
3538 PIN_BANK(2, 32, "gpio2"),
3541 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3542 .pin_banks = rk3036_pin_banks,
3543 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3544 .label = "RK3036-GPIO",
3546 .grf_mux_offset = 0xa8,
3547 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3550 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3551 PIN_BANK(0, 32, "gpio0"),
3552 PIN_BANK(1, 32, "gpio1"),
3553 PIN_BANK(2, 32, "gpio2"),
3554 PIN_BANK(3, 32, "gpio3"),
3555 PIN_BANK(4, 32, "gpio4"),
3556 PIN_BANK(6, 16, "gpio6"),
3559 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3560 .pin_banks = rk3066a_pin_banks,
3561 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3562 .label = "RK3066a-GPIO",
3564 .grf_mux_offset = 0xa8,
3565 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3568 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3569 PIN_BANK(0, 32, "gpio0"),
3570 PIN_BANK(1, 32, "gpio1"),
3571 PIN_BANK(2, 32, "gpio2"),
3572 PIN_BANK(3, 32, "gpio3"),
3575 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3576 .pin_banks = rk3066b_pin_banks,
3577 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3578 .label = "RK3066b-GPIO",
3580 .grf_mux_offset = 0x60,
3583 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3584 PIN_BANK(0, 32, "gpio0"),
3585 PIN_BANK(1, 32, "gpio1"),
3586 PIN_BANK(2, 32, "gpio2"),
3587 PIN_BANK(3, 32, "gpio3"),
3590 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3591 .pin_banks = rk3128_pin_banks,
3592 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3593 .label = "RK3128-GPIO",
3595 .grf_mux_offset = 0xa8,
3596 .iomux_recalced = rk3128_mux_recalced_data,
3597 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3598 .iomux_routes = rk3128_mux_route_data,
3599 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3600 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3603 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3604 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3605 PIN_BANK(1, 32, "gpio1"),
3606 PIN_BANK(2, 32, "gpio2"),
3607 PIN_BANK(3, 32, "gpio3"),
3610 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3611 .pin_banks = rk3188_pin_banks,
3612 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3613 .label = "RK3188-GPIO",
3615 .grf_mux_offset = 0x60,
3616 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3619 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3620 PIN_BANK(0, 32, "gpio0"),
3621 PIN_BANK(1, 32, "gpio1"),
3622 PIN_BANK(2, 32, "gpio2"),
3623 PIN_BANK(3, 32, "gpio3"),
3626 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3627 .pin_banks = rk3228_pin_banks,
3628 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3629 .label = "RK3228-GPIO",
3631 .grf_mux_offset = 0x0,
3632 .iomux_routes = rk3228_mux_route_data,
3633 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3634 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3635 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3638 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3639 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3644 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3649 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3650 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3651 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3656 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3661 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3662 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3667 PIN_BANK(8, 16, "gpio8"),
3670 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3671 .pin_banks = rk3288_pin_banks,
3672 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3673 .label = "RK3288-GPIO",
3675 .grf_mux_offset = 0x0,
3676 .pmu_mux_offset = 0x84,
3677 .iomux_routes = rk3288_mux_route_data,
3678 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3679 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3680 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3683 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3684 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3685 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3686 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3690 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3697 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3698 .pin_banks = rk3328_pin_banks,
3699 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3700 .label = "RK3328-GPIO",
3702 .grf_mux_offset = 0x0,
3703 .iomux_recalced = rk3328_mux_recalced_data,
3704 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3705 .iomux_routes = rk3328_mux_route_data,
3706 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3707 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3708 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3709 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3712 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3713 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3718 PIN_BANK(1, 32, "gpio1"),
3719 PIN_BANK(2, 32, "gpio2"),
3720 PIN_BANK(3, 32, "gpio3"),
3723 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3724 .pin_banks = rk3368_pin_banks,
3725 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3726 .label = "RK3368-GPIO",
3728 .grf_mux_offset = 0x0,
3729 .pmu_mux_offset = 0x0,
3730 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3731 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3734 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3735 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3740 DRV_TYPE_IO_1V8_ONLY,
3741 DRV_TYPE_IO_1V8_ONLY,
3742 DRV_TYPE_IO_DEFAULT,
3743 DRV_TYPE_IO_DEFAULT,
3748 PULL_TYPE_IO_1V8_ONLY,
3749 PULL_TYPE_IO_1V8_ONLY,
3750 PULL_TYPE_IO_DEFAULT,
3751 PULL_TYPE_IO_DEFAULT
3753 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3757 DRV_TYPE_IO_1V8_OR_3V0,
3758 DRV_TYPE_IO_1V8_OR_3V0,
3759 DRV_TYPE_IO_1V8_OR_3V0,
3760 DRV_TYPE_IO_1V8_OR_3V0,
3766 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3767 DRV_TYPE_IO_1V8_OR_3V0,
3768 DRV_TYPE_IO_1V8_ONLY,
3769 DRV_TYPE_IO_1V8_ONLY,
3770 PULL_TYPE_IO_DEFAULT,
3771 PULL_TYPE_IO_DEFAULT,
3772 PULL_TYPE_IO_1V8_ONLY,
3773 PULL_TYPE_IO_1V8_ONLY
3775 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3776 DRV_TYPE_IO_3V3_ONLY,
3777 DRV_TYPE_IO_3V3_ONLY,
3778 DRV_TYPE_IO_1V8_OR_3V0
3780 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3781 DRV_TYPE_IO_1V8_3V0_AUTO,
3782 DRV_TYPE_IO_1V8_OR_3V0,
3783 DRV_TYPE_IO_1V8_OR_3V0
3787 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3788 .pin_banks = rk3399_pin_banks,
3789 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3790 .label = "RK3399-GPIO",
3792 .grf_mux_offset = 0xe000,
3793 .pmu_mux_offset = 0x0,
3794 .grf_drv_offset = 0xe100,
3795 .pmu_drv_offset = 0x80,
3796 .iomux_routes = rk3399_mux_route_data,
3797 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3798 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3799 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3802 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3803 { .compatible = "rockchip,px30-pinctrl",
3804 .data = &px30_pin_ctrl },
3805 { .compatible = "rockchip,rv1108-pinctrl",
3806 .data = &rv1108_pin_ctrl },
3807 { .compatible = "rockchip,rk2928-pinctrl",
3808 .data = &rk2928_pin_ctrl },
3809 { .compatible = "rockchip,rk3036-pinctrl",
3810 .data = &rk3036_pin_ctrl },
3811 { .compatible = "rockchip,rk3066a-pinctrl",
3812 .data = &rk3066a_pin_ctrl },
3813 { .compatible = "rockchip,rk3066b-pinctrl",
3814 .data = &rk3066b_pin_ctrl },
3815 { .compatible = "rockchip,rk3128-pinctrl",
3816 .data = (void *)&rk3128_pin_ctrl },
3817 { .compatible = "rockchip,rk3188-pinctrl",
3818 .data = &rk3188_pin_ctrl },
3819 { .compatible = "rockchip,rk3228-pinctrl",
3820 .data = &rk3228_pin_ctrl },
3821 { .compatible = "rockchip,rk3288-pinctrl",
3822 .data = &rk3288_pin_ctrl },
3823 { .compatible = "rockchip,rk3328-pinctrl",
3824 .data = &rk3328_pin_ctrl },
3825 { .compatible = "rockchip,rk3368-pinctrl",
3826 .data = &rk3368_pin_ctrl },
3827 { .compatible = "rockchip,rk3399-pinctrl",
3828 .data = &rk3399_pin_ctrl },
3832 static struct platform_driver rockchip_pinctrl_driver = {
3833 .probe = rockchip_pinctrl_probe,
3835 .name = "rockchip-pinctrl",
3836 .pm = &rockchip_pinctrl_dev_pm_ops,
3837 .of_match_table = rockchip_pinctrl_dt_match,
3841 static int __init rockchip_pinctrl_drv_register(void)
3843 return platform_driver_register(&rockchip_pinctrl_driver);
3845 postcore_initcall(rockchip_pinctrl_drv_register);