2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/init.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
61 enum rockchip_pinctrl_type {
71 * Encode variants of iomux registers into a type variable
73 #define IOMUX_GPIO_ONLY BIT(0)
74 #define IOMUX_WIDTH_4BIT BIT(1)
75 #define IOMUX_SOURCE_PMU BIT(2)
76 #define IOMUX_UNROUTED BIT(3)
79 * @type: iomux variant using IOMUX_* constants
80 * @offset: if initialized to -1 it will be autocalculated, by specifying
81 * an initial offset value the relevant source offset can be reset
82 * to a new value for autocalculating the following iomux registers.
84 struct rockchip_iomux {
90 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
92 enum rockchip_pin_drv_type {
93 DRV_TYPE_IO_DEFAULT = 0,
94 DRV_TYPE_IO_1V8_OR_3V0,
96 DRV_TYPE_IO_1V8_3V0_AUTO,
102 * enum type index corresponding to rockchip_pull_list arrays index.
104 enum rockchip_pin_pull_type {
105 PULL_TYPE_IO_DEFAULT = 0,
106 PULL_TYPE_IO_1V8_ONLY,
111 * @drv_type: drive strength variant using rockchip_perpin_drv_type
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
113 * an initial offset value the relevant source offset can be reset
114 * to a new value for autocalculating the following drive strength
115 * registers. if used chips own cal_drv func instead to calculate
116 * registers offset, the variant could be ignored.
118 struct rockchip_drv {
119 enum rockchip_pin_drv_type drv_type;
124 * @reg_base: register base of the gpio bank
125 * @reg_pull: optional separate register for additional pull settings
126 * @clk: clock of the gpio bank
127 * @irq: interrupt of the gpio bank
128 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
129 * @pin_base: first pin number
130 * @nr_pins: number of pins in this bank
131 * @name: name of the bank
132 * @bank_num: number of the bank, to account for holes
133 * @iomux: array describing the 4 iomux sources of the bank
134 * @drv: array describing the 4 drive strength sources of the bank
135 * @pull_type: array describing the 4 pull type sources of the bank
136 * @valid: are all necessary informations present
137 * @of_node: dt node of this bank
138 * @drvdata: common pinctrl basedata
139 * @domain: irqdomain of the gpio bank
140 * @gpio_chip: gpiolib chip
141 * @grange: gpio range
142 * @slock: spinlock for the gpio bank
144 struct rockchip_pin_bank {
145 void __iomem *reg_base;
146 struct regmap *regmap_pull;
154 struct rockchip_iomux iomux[4];
155 struct rockchip_drv drv[4];
156 enum rockchip_pin_pull_type pull_type[4];
158 struct device_node *of_node;
159 struct rockchip_pinctrl *drvdata;
160 struct irq_domain *domain;
161 struct gpio_chip gpio_chip;
162 struct pinctrl_gpio_range grange;
164 u32 toggle_edge_mode;
167 #define PIN_BANK(id, pins, label) \
180 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
186 { .type = iom0, .offset = -1 }, \
187 { .type = iom1, .offset = -1 }, \
188 { .type = iom2, .offset = -1 }, \
189 { .type = iom3, .offset = -1 }, \
193 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
205 { .drv_type = type0, .offset = -1 }, \
206 { .drv_type = type1, .offset = -1 }, \
207 { .drv_type = type2, .offset = -1 }, \
208 { .drv_type = type3, .offset = -1 }, \
212 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
213 drv2, drv3, pull0, pull1, \
226 { .drv_type = drv0, .offset = -1 }, \
227 { .drv_type = drv1, .offset = -1 }, \
228 { .drv_type = drv2, .offset = -1 }, \
229 { .drv_type = drv3, .offset = -1 }, \
231 .pull_type[0] = pull0, \
232 .pull_type[1] = pull1, \
233 .pull_type[2] = pull2, \
234 .pull_type[3] = pull3, \
237 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
238 iom2, iom3, drv0, drv1, drv2, \
239 drv3, offset0, offset1, \
246 { .type = iom0, .offset = -1 }, \
247 { .type = iom1, .offset = -1 }, \
248 { .type = iom2, .offset = -1 }, \
249 { .type = iom3, .offset = -1 }, \
252 { .drv_type = drv0, .offset = offset0 }, \
253 { .drv_type = drv1, .offset = offset1 }, \
254 { .drv_type = drv2, .offset = offset2 }, \
255 { .drv_type = drv3, .offset = offset3 }, \
259 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
260 label, iom0, iom1, iom2, \
261 iom3, drv0, drv1, drv2, \
262 drv3, offset0, offset1, \
263 offset2, offset3, pull0, \
264 pull1, pull2, pull3) \
270 { .type = iom0, .offset = -1 }, \
271 { .type = iom1, .offset = -1 }, \
272 { .type = iom2, .offset = -1 }, \
273 { .type = iom3, .offset = -1 }, \
276 { .drv_type = drv0, .offset = offset0 }, \
277 { .drv_type = drv1, .offset = offset1 }, \
278 { .drv_type = drv2, .offset = offset2 }, \
279 { .drv_type = drv3, .offset = offset3 }, \
281 .pull_type[0] = pull0, \
282 .pull_type[1] = pull1, \
283 .pull_type[2] = pull2, \
284 .pull_type[3] = pull3, \
289 struct rockchip_pin_ctrl {
290 struct rockchip_pin_bank *pin_banks;
294 enum rockchip_pinctrl_type type;
300 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
301 int pin_num, struct regmap **regmap,
303 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
304 int pin_num, struct regmap **regmap,
308 struct rockchip_pin_config {
310 unsigned long *configs;
311 unsigned int nconfigs;
315 * struct rockchip_pin_group: represent group of pins of a pinmux function.
316 * @name: name of the pin group, used to lookup the group.
317 * @pins: the pins included in this group.
318 * @npins: number of pins included in this group.
319 * @func: the mux function number to be programmed when selected.
320 * @configs: the config values to be set for each pin
321 * @nconfigs: number of configs for each pin
323 struct rockchip_pin_group {
327 struct rockchip_pin_config *data;
331 * struct rockchip_pmx_func: represent a pin function.
332 * @name: name of the pin function, used to lookup the function.
333 * @groups: one or more names of pin groups that provide this function.
334 * @num_groups: number of groups included in @groups.
336 struct rockchip_pmx_func {
342 struct rockchip_pinctrl {
343 struct regmap *regmap_base;
345 struct regmap *regmap_pull;
346 struct regmap *regmap_pmu;
348 struct rockchip_pin_ctrl *ctrl;
349 struct pinctrl_desc pctl;
350 struct pinctrl_dev *pctl_dev;
351 struct rockchip_pin_group *groups;
352 unsigned int ngroups;
353 struct rockchip_pmx_func *functions;
354 unsigned int nfunctions;
357 static struct regmap_config rockchip_regmap_config = {
363 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
364 const struct rockchip_pinctrl *info,
369 for (i = 0; i < info->ngroups; i++) {
370 if (!strcmp(info->groups[i].name, name))
371 return &info->groups[i];
378 * given a pin number that is local to a pin controller, find out the pin bank
379 * and the register base of the pin bank.
381 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
384 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
386 while (pin >= (b->pin_base + b->nr_pins))
392 static struct rockchip_pin_bank *bank_num_to_bank(
393 struct rockchip_pinctrl *info,
396 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
399 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
400 if (b->bank_num == num)
404 return ERR_PTR(-EINVAL);
408 * Pinctrl_ops handling
411 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
413 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
415 return info->ngroups;
418 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
421 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
423 return info->groups[selector].name;
426 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
427 unsigned selector, const unsigned **pins,
430 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
432 if (selector >= info->ngroups)
435 *pins = info->groups[selector].pins;
436 *npins = info->groups[selector].npins;
441 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
442 struct device_node *np,
443 struct pinctrl_map **map, unsigned *num_maps)
445 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
446 const struct rockchip_pin_group *grp;
447 struct pinctrl_map *new_map;
448 struct device_node *parent;
453 * first find the group of this node and check if we need to create
454 * config maps for pins
456 grp = pinctrl_name_to_group(info, np->name);
458 dev_err(info->dev, "unable to find group for node %s\n",
463 map_num += grp->npins;
464 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
473 parent = of_get_parent(np);
475 devm_kfree(pctldev->dev, new_map);
478 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
479 new_map[0].data.mux.function = parent->name;
480 new_map[0].data.mux.group = np->name;
483 /* create config map */
485 for (i = 0; i < grp->npins; i++) {
486 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
487 new_map[i].data.configs.group_or_pin =
488 pin_get_name(pctldev, grp->pins[i]);
489 new_map[i].data.configs.configs = grp->data[i].configs;
490 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
493 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
494 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
499 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
500 struct pinctrl_map *map, unsigned num_maps)
504 static const struct pinctrl_ops rockchip_pctrl_ops = {
505 .get_groups_count = rockchip_get_groups_count,
506 .get_group_name = rockchip_get_group_name,
507 .get_group_pins = rockchip_get_group_pins,
508 .dt_node_to_map = rockchip_dt_node_to_map,
509 .dt_free_map = rockchip_dt_free_map,
516 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
518 struct rockchip_pinctrl *info = bank->drvdata;
519 int iomux_num = (pin / 8);
520 struct regmap *regmap;
528 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
529 dev_err(info->dev, "pin %d is unrouted\n", pin);
533 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
536 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
537 ? info->regmap_pmu : info->regmap_base;
539 /* get basic quadrupel of mux registers and the correct reg inside */
540 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
541 reg = bank->iomux[iomux_num].offset;
542 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
550 ret = regmap_read(regmap, reg, &val);
554 return ((val >> bit) & mask);
558 * Set a new mux function for a pin.
560 * The register is divided into the upper and lower 16 bit. When changing
561 * a value, the previous register value is not read and changed. Instead
562 * it seems the changed bits are marked in the upper 16 bit, while the
563 * changed value gets set in the same offset in the lower 16 bit.
564 * All pin settings seem to be 2 bit wide in both the upper and lower
566 * @bank: pin bank to change
567 * @pin: pin to change
568 * @mux: new mux function to set
570 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
572 struct rockchip_pinctrl *info = bank->drvdata;
573 int iomux_num = (pin / 8);
574 struct regmap *regmap;
583 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
584 dev_err(info->dev, "pin %d is unrouted\n", pin);
588 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
589 if (mux != RK_FUNC_GPIO) {
591 "pin %d only supports a gpio mux\n", pin);
598 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
599 bank->bank_num, pin, mux);
601 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
602 ? info->regmap_pmu : info->regmap_base;
604 /* get basic quadrupel of mux registers and the correct reg inside */
605 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
606 reg = bank->iomux[iomux_num].offset;
607 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
615 spin_lock_irqsave(&bank->slock, flags);
617 data = (mask << (bit + 16));
618 rmask = data | (data >> 16);
619 data |= (mux & mask) << bit;
620 ret = regmap_update_bits(regmap, reg, rmask, data);
622 spin_unlock_irqrestore(&bank->slock, flags);
627 #define RK2928_PULL_OFFSET 0x118
628 #define RK2928_PULL_PINS_PER_REG 16
629 #define RK2928_PULL_BANK_STRIDE 8
631 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
632 int pin_num, struct regmap **regmap,
635 struct rockchip_pinctrl *info = bank->drvdata;
637 *regmap = info->regmap_base;
638 *reg = RK2928_PULL_OFFSET;
639 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
640 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
642 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
645 #define RK3188_PULL_OFFSET 0x164
646 #define RK3188_PULL_BITS_PER_PIN 2
647 #define RK3188_PULL_PINS_PER_REG 8
648 #define RK3188_PULL_BANK_STRIDE 16
649 #define RK3188_PULL_PMU_OFFSET 0x64
651 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
652 int pin_num, struct regmap **regmap,
655 struct rockchip_pinctrl *info = bank->drvdata;
657 /* The first 12 pins of the first bank are located elsewhere */
658 if (bank->bank_num == 0 && pin_num < 12) {
659 *regmap = info->regmap_pmu ? info->regmap_pmu
661 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
662 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
663 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
664 *bit *= RK3188_PULL_BITS_PER_PIN;
666 *regmap = info->regmap_pull ? info->regmap_pull
668 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
670 /* correct the offset, as it is the 2nd pull register */
672 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
673 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
676 * The bits in these registers have an inverse ordering
677 * with the lowest pin being in bits 15:14 and the highest
680 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
681 *bit *= RK3188_PULL_BITS_PER_PIN;
685 #define RK3288_PULL_OFFSET 0x140
686 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
687 int pin_num, struct regmap **regmap,
690 struct rockchip_pinctrl *info = bank->drvdata;
692 /* The first 24 pins of the first bank are located in PMU */
693 if (bank->bank_num == 0) {
694 *regmap = info->regmap_pmu;
695 *reg = RK3188_PULL_PMU_OFFSET;
697 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
698 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
699 *bit *= RK3188_PULL_BITS_PER_PIN;
701 *regmap = info->regmap_base;
702 *reg = RK3288_PULL_OFFSET;
704 /* correct the offset, as we're starting with the 2nd bank */
706 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
707 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
709 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
710 *bit *= RK3188_PULL_BITS_PER_PIN;
714 #define RK3288_DRV_PMU_OFFSET 0x70
715 #define RK3288_DRV_GRF_OFFSET 0x1c0
716 #define RK3288_DRV_BITS_PER_PIN 2
717 #define RK3288_DRV_PINS_PER_REG 8
718 #define RK3288_DRV_BANK_STRIDE 16
720 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
721 int pin_num, struct regmap **regmap,
724 struct rockchip_pinctrl *info = bank->drvdata;
726 /* The first 24 pins of the first bank are located in PMU */
727 if (bank->bank_num == 0) {
728 *regmap = info->regmap_pmu;
729 *reg = RK3288_DRV_PMU_OFFSET;
731 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
732 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
733 *bit *= RK3288_DRV_BITS_PER_PIN;
735 *regmap = info->regmap_base;
736 *reg = RK3288_DRV_GRF_OFFSET;
738 /* correct the offset, as we're starting with the 2nd bank */
740 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
741 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
743 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
744 *bit *= RK3288_DRV_BITS_PER_PIN;
748 #define RK3228_PULL_OFFSET 0x100
750 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751 int pin_num, struct regmap **regmap,
754 struct rockchip_pinctrl *info = bank->drvdata;
756 *regmap = info->regmap_base;
757 *reg = RK3228_PULL_OFFSET;
758 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
759 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
761 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
762 *bit *= RK3188_PULL_BITS_PER_PIN;
765 #define RK3228_DRV_GRF_OFFSET 0x200
767 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
768 int pin_num, struct regmap **regmap,
771 struct rockchip_pinctrl *info = bank->drvdata;
773 *regmap = info->regmap_base;
774 *reg = RK3228_DRV_GRF_OFFSET;
775 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
776 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
778 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
779 *bit *= RK3288_DRV_BITS_PER_PIN;
782 #define RK3368_PULL_GRF_OFFSET 0x100
783 #define RK3368_PULL_PMU_OFFSET 0x10
785 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
786 int pin_num, struct regmap **regmap,
789 struct rockchip_pinctrl *info = bank->drvdata;
791 /* The first 32 pins of the first bank are located in PMU */
792 if (bank->bank_num == 0) {
793 *regmap = info->regmap_pmu;
794 *reg = RK3368_PULL_PMU_OFFSET;
796 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
797 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
798 *bit *= RK3188_PULL_BITS_PER_PIN;
800 *regmap = info->regmap_base;
801 *reg = RK3368_PULL_GRF_OFFSET;
803 /* correct the offset, as we're starting with the 2nd bank */
805 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
806 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
808 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
809 *bit *= RK3188_PULL_BITS_PER_PIN;
813 #define RK3368_DRV_PMU_OFFSET 0x20
814 #define RK3368_DRV_GRF_OFFSET 0x200
816 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
817 int pin_num, struct regmap **regmap,
820 struct rockchip_pinctrl *info = bank->drvdata;
822 /* The first 32 pins of the first bank are located in PMU */
823 if (bank->bank_num == 0) {
824 *regmap = info->regmap_pmu;
825 *reg = RK3368_DRV_PMU_OFFSET;
827 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
828 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
829 *bit *= RK3288_DRV_BITS_PER_PIN;
831 *regmap = info->regmap_base;
832 *reg = RK3368_DRV_GRF_OFFSET;
834 /* correct the offset, as we're starting with the 2nd bank */
836 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
837 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
839 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
840 *bit *= RK3288_DRV_BITS_PER_PIN;
844 #define RK3399_PULL_GRF_OFFSET 0xe040
845 #define RK3399_PULL_PMU_OFFSET 0x40
846 #define RK3399_DRV_3BITS_PER_PIN 3
848 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
849 int pin_num, struct regmap **regmap,
852 struct rockchip_pinctrl *info = bank->drvdata;
854 /* The bank0:16 and bank1:32 pins are located in PMU */
855 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
856 *regmap = info->regmap_pmu;
857 *reg = RK3399_PULL_PMU_OFFSET;
859 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
861 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
862 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
863 *bit *= RK3188_PULL_BITS_PER_PIN;
865 *regmap = info->regmap_base;
866 *reg = RK3399_PULL_GRF_OFFSET;
868 /* correct the offset, as we're starting with the 3rd bank */
870 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
871 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
873 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
874 *bit *= RK3188_PULL_BITS_PER_PIN;
878 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
879 int pin_num, struct regmap **regmap,
882 struct rockchip_pinctrl *info = bank->drvdata;
883 int drv_num = (pin_num / 8);
885 /* The bank0:16 and bank1:32 pins are located in PMU */
886 if ((bank->bank_num == 0) || (bank->bank_num == 1))
887 *regmap = info->regmap_pmu;
889 *regmap = info->regmap_base;
891 *reg = bank->drv[drv_num].offset;
892 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
893 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
894 *bit = (pin_num % 8) * 3;
896 *bit = (pin_num % 8) * 2;
899 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
900 { 2, 4, 8, 12, -1, -1, -1, -1 },
901 { 3, 6, 9, 12, -1, -1, -1, -1 },
902 { 5, 10, 15, 20, -1, -1, -1, -1 },
903 { 4, 6, 8, 10, 12, 14, 16, 18 },
904 { 4, 7, 10, 13, 16, 19, 22, 26 }
907 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
910 struct rockchip_pinctrl *info = bank->drvdata;
911 struct rockchip_pin_ctrl *ctrl = info->ctrl;
912 struct regmap *regmap;
914 u32 data, temp, rmask_bits;
916 int drv_type = bank->drv[pin_num / 8].drv_type;
918 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
921 case DRV_TYPE_IO_1V8_3V0_AUTO:
922 case DRV_TYPE_IO_3V3_ONLY:
923 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
926 /* regular case, nothing to do */
930 * drive-strength offset is special, as it is
931 * spread over 2 registers
933 ret = regmap_read(regmap, reg, &data);
937 ret = regmap_read(regmap, reg + 0x4, &temp);
942 * the bit data[15] contains bit 0 of the value
943 * while temp[1:0] contains bits 2 and 1
950 return rockchip_perpin_drv_list[drv_type][data];
952 /* setting fully enclosed in the second register */
957 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
963 case DRV_TYPE_IO_DEFAULT:
964 case DRV_TYPE_IO_1V8_OR_3V0:
965 case DRV_TYPE_IO_1V8_ONLY:
966 rmask_bits = RK3288_DRV_BITS_PER_PIN;
969 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
974 ret = regmap_read(regmap, reg, &data);
979 data &= (1 << rmask_bits) - 1;
981 return rockchip_perpin_drv_list[drv_type][data];
984 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
985 int pin_num, int strength)
987 struct rockchip_pinctrl *info = bank->drvdata;
988 struct rockchip_pin_ctrl *ctrl = info->ctrl;
989 struct regmap *regmap;
992 u32 data, rmask, rmask_bits, temp;
994 int drv_type = bank->drv[pin_num / 8].drv_type;
996 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
997 bank->bank_num, pin_num, strength);
999 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1002 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1003 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1006 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1007 ret = rockchip_perpin_drv_list[drv_type][i];
1013 dev_err(info->dev, "unsupported driver strength %d\n",
1018 spin_lock_irqsave(&bank->slock, flags);
1021 case DRV_TYPE_IO_1V8_3V0_AUTO:
1022 case DRV_TYPE_IO_3V3_ONLY:
1023 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1026 /* regular case, nothing to do */
1030 * drive-strength offset is special, as it is spread
1031 * over 2 registers, the bit data[15] contains bit 0
1032 * of the value while temp[1:0] contains bits 2 and 1
1034 data = (ret & 0x1) << 15;
1035 temp = (ret >> 0x1) & 0x3;
1037 rmask = BIT(15) | BIT(31);
1039 ret = regmap_update_bits(regmap, reg, rmask, data);
1041 spin_unlock_irqrestore(&bank->slock, flags);
1045 rmask = 0x3 | (0x3 << 16);
1046 temp |= (0x3 << 16);
1048 ret = regmap_update_bits(regmap, reg, rmask, temp);
1050 spin_unlock_irqrestore(&bank->slock, flags);
1053 /* setting fully enclosed in the second register */
1058 spin_unlock_irqrestore(&bank->slock, flags);
1059 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1064 case DRV_TYPE_IO_DEFAULT:
1065 case DRV_TYPE_IO_1V8_OR_3V0:
1066 case DRV_TYPE_IO_1V8_ONLY:
1067 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1070 spin_unlock_irqrestore(&bank->slock, flags);
1071 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1076 /* enable the write to the equivalent lower bits */
1077 data = ((1 << rmask_bits) - 1) << (bit + 16);
1078 rmask = data | (data >> 16);
1079 data |= (ret << bit);
1081 ret = regmap_update_bits(regmap, reg, rmask, data);
1082 spin_unlock_irqrestore(&bank->slock, flags);
1087 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1089 PIN_CONFIG_BIAS_DISABLE,
1090 PIN_CONFIG_BIAS_PULL_UP,
1091 PIN_CONFIG_BIAS_PULL_DOWN,
1092 PIN_CONFIG_BIAS_BUS_HOLD
1095 PIN_CONFIG_BIAS_DISABLE,
1096 PIN_CONFIG_BIAS_PULL_DOWN,
1097 PIN_CONFIG_BIAS_DISABLE,
1098 PIN_CONFIG_BIAS_PULL_UP
1102 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1104 struct rockchip_pinctrl *info = bank->drvdata;
1105 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1106 struct regmap *regmap;
1107 int reg, ret, pull_type;
1111 /* rk3066b does support any pulls */
1112 if (ctrl->type == RK3066B)
1113 return PIN_CONFIG_BIAS_DISABLE;
1115 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1117 ret = regmap_read(regmap, reg, &data);
1121 switch (ctrl->type) {
1123 return !(data & BIT(bit))
1124 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1125 : PIN_CONFIG_BIAS_DISABLE;
1130 pull_type = bank->pull_type[pin_num / 8];
1132 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1134 return rockchip_pull_list[pull_type][data];
1136 dev_err(info->dev, "unsupported pinctrl type\n");
1141 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1142 int pin_num, int pull)
1144 struct rockchip_pinctrl *info = bank->drvdata;
1145 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1146 struct regmap *regmap;
1147 int reg, ret, i, pull_type;
1148 unsigned long flags;
1152 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1153 bank->bank_num, pin_num, pull);
1155 /* rk3066b does support any pulls */
1156 if (ctrl->type == RK3066B)
1157 return pull ? -EINVAL : 0;
1159 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1161 switch (ctrl->type) {
1163 spin_lock_irqsave(&bank->slock, flags);
1165 data = BIT(bit + 16);
1166 if (pull == PIN_CONFIG_BIAS_DISABLE)
1168 ret = regmap_write(regmap, reg, data);
1170 spin_unlock_irqrestore(&bank->slock, flags);
1176 pull_type = bank->pull_type[pin_num / 8];
1178 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1180 if (rockchip_pull_list[pull_type][i] == pull) {
1187 dev_err(info->dev, "unsupported pull setting %d\n",
1192 spin_lock_irqsave(&bank->slock, flags);
1194 /* enable the write to the equivalent lower bits */
1195 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1196 rmask = data | (data >> 16);
1197 data |= (ret << bit);
1199 ret = regmap_update_bits(regmap, reg, rmask, data);
1201 spin_unlock_irqrestore(&bank->slock, flags);
1204 dev_err(info->dev, "unsupported pinctrl type\n");
1212 * Pinmux_ops handling
1215 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1217 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1219 return info->nfunctions;
1222 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1225 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1227 return info->functions[selector].name;
1230 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1231 unsigned selector, const char * const **groups,
1232 unsigned * const num_groups)
1234 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1236 *groups = info->functions[selector].groups;
1237 *num_groups = info->functions[selector].ngroups;
1242 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1245 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1246 const unsigned int *pins = info->groups[group].pins;
1247 const struct rockchip_pin_config *data = info->groups[group].data;
1248 struct rockchip_pin_bank *bank;
1251 dev_dbg(info->dev, "enable function %s group %s\n",
1252 info->functions[selector].name, info->groups[group].name);
1255 * for each pin in the pin group selected, program the correspoding pin
1256 * pin function number in the config register.
1258 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1259 bank = pin_to_bank(info, pins[cnt]);
1260 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1267 /* revert the already done pin settings */
1268 for (cnt--; cnt >= 0; cnt--)
1269 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1277 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1279 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1283 ret = clk_enable(bank->clk);
1285 dev_err(bank->drvdata->dev,
1286 "failed to enable clock for bank %s\n", bank->name);
1289 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1290 clk_disable(bank->clk);
1292 return !(data & BIT(offset));
1296 * The calls to gpio_direction_output() and gpio_direction_input()
1297 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1298 * function called from the gpiolib interface).
1300 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1301 int pin, bool input)
1303 struct rockchip_pin_bank *bank;
1305 unsigned long flags;
1308 bank = gpiochip_get_data(chip);
1310 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1314 clk_enable(bank->clk);
1315 spin_lock_irqsave(&bank->slock, flags);
1317 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1318 /* set bit to 1 for output, 0 for input */
1323 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1325 spin_unlock_irqrestore(&bank->slock, flags);
1326 clk_disable(bank->clk);
1331 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1332 struct pinctrl_gpio_range *range,
1333 unsigned offset, bool input)
1335 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1336 struct gpio_chip *chip;
1340 pin = offset - chip->base;
1341 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1342 offset, range->name, pin, input ? "input" : "output");
1344 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1348 static const struct pinmux_ops rockchip_pmx_ops = {
1349 .get_functions_count = rockchip_pmx_get_funcs_count,
1350 .get_function_name = rockchip_pmx_get_func_name,
1351 .get_function_groups = rockchip_pmx_get_groups,
1352 .set_mux = rockchip_pmx_set,
1353 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1357 * Pinconf_ops handling
1360 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1361 enum pin_config_param pull)
1363 switch (ctrl->type) {
1365 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1366 pull == PIN_CONFIG_BIAS_DISABLE);
1368 return pull ? false : true;
1373 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1379 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1380 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1382 /* set the pin config settings for a specified pin */
1383 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1384 unsigned long *configs, unsigned num_configs)
1386 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1387 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1388 enum pin_config_param param;
1393 for (i = 0; i < num_configs; i++) {
1394 param = pinconf_to_config_param(configs[i]);
1395 arg = pinconf_to_config_argument(configs[i]);
1398 case PIN_CONFIG_BIAS_DISABLE:
1399 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1404 case PIN_CONFIG_BIAS_PULL_UP:
1405 case PIN_CONFIG_BIAS_PULL_DOWN:
1406 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1407 case PIN_CONFIG_BIAS_BUS_HOLD:
1408 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1414 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1419 case PIN_CONFIG_OUTPUT:
1420 rockchip_gpio_set(&bank->gpio_chip,
1421 pin - bank->pin_base, arg);
1422 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1423 pin - bank->pin_base, false);
1427 case PIN_CONFIG_DRIVE_STRENGTH:
1428 /* rk3288 is the first with per-pin drive-strength */
1429 if (!info->ctrl->drv_calc_reg)
1432 rc = rockchip_set_drive_perpin(bank,
1433 pin - bank->pin_base, arg);
1441 } /* for each config */
1446 /* get the pin config settings for a specified pin */
1447 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1448 unsigned long *config)
1450 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1451 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1452 enum pin_config_param param = pinconf_to_config_param(*config);
1457 case PIN_CONFIG_BIAS_DISABLE:
1458 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1463 case PIN_CONFIG_BIAS_PULL_UP:
1464 case PIN_CONFIG_BIAS_PULL_DOWN:
1465 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1466 case PIN_CONFIG_BIAS_BUS_HOLD:
1467 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1470 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1475 case PIN_CONFIG_OUTPUT:
1476 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1477 if (rc != RK_FUNC_GPIO)
1480 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1486 case PIN_CONFIG_DRIVE_STRENGTH:
1487 /* rk3288 is the first with per-pin drive-strength */
1488 if (!info->ctrl->drv_calc_reg)
1491 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1502 *config = pinconf_to_config_packed(param, arg);
1507 static const struct pinconf_ops rockchip_pinconf_ops = {
1508 .pin_config_get = rockchip_pinconf_get,
1509 .pin_config_set = rockchip_pinconf_set,
1513 static const struct of_device_id rockchip_bank_match[] = {
1514 { .compatible = "rockchip,gpio-bank" },
1515 { .compatible = "rockchip,rk3188-gpio-bank0" },
1519 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1520 struct device_node *np)
1522 struct device_node *child;
1524 for_each_child_of_node(np, child) {
1525 if (of_match_node(rockchip_bank_match, child))
1529 info->ngroups += of_get_child_count(child);
1533 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1534 struct rockchip_pin_group *grp,
1535 struct rockchip_pinctrl *info,
1538 struct rockchip_pin_bank *bank;
1545 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1547 /* Initialise group */
1548 grp->name = np->name;
1551 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1552 * do sanity check and calculate pins number
1554 list = of_get_property(np, "rockchip,pins", &size);
1555 /* we do not check return since it's safe node passed down */
1556 size /= sizeof(*list);
1557 if (!size || size % 4) {
1558 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1562 grp->npins = size / 4;
1564 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1566 grp->data = devm_kzalloc(info->dev, grp->npins *
1567 sizeof(struct rockchip_pin_config),
1569 if (!grp->pins || !grp->data)
1572 for (i = 0, j = 0; i < size; i += 4, j++) {
1573 const __be32 *phandle;
1574 struct device_node *np_config;
1576 num = be32_to_cpu(*list++);
1577 bank = bank_num_to_bank(info, num);
1579 return PTR_ERR(bank);
1581 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1582 grp->data[j].func = be32_to_cpu(*list++);
1588 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1589 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1590 &grp->data[j].configs, &grp->data[j].nconfigs);
1598 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1599 struct rockchip_pinctrl *info,
1602 struct device_node *child;
1603 struct rockchip_pmx_func *func;
1604 struct rockchip_pin_group *grp;
1606 static u32 grp_index;
1609 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1611 func = &info->functions[index];
1613 /* Initialise function */
1614 func->name = np->name;
1615 func->ngroups = of_get_child_count(np);
1616 if (func->ngroups <= 0)
1619 func->groups = devm_kzalloc(info->dev,
1620 func->ngroups * sizeof(char *), GFP_KERNEL);
1624 for_each_child_of_node(np, child) {
1625 func->groups[i] = child->name;
1626 grp = &info->groups[grp_index++];
1627 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1637 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1638 struct rockchip_pinctrl *info)
1640 struct device *dev = &pdev->dev;
1641 struct device_node *np = dev->of_node;
1642 struct device_node *child;
1646 rockchip_pinctrl_child_count(info, np);
1648 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1649 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1651 info->functions = devm_kzalloc(dev, info->nfunctions *
1652 sizeof(struct rockchip_pmx_func),
1654 if (!info->functions) {
1655 dev_err(dev, "failed to allocate memory for function list\n");
1659 info->groups = devm_kzalloc(dev, info->ngroups *
1660 sizeof(struct rockchip_pin_group),
1662 if (!info->groups) {
1663 dev_err(dev, "failed allocate memory for ping group list\n");
1669 for_each_child_of_node(np, child) {
1670 if (of_match_node(rockchip_bank_match, child))
1673 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1675 dev_err(&pdev->dev, "failed to parse function\n");
1684 static int rockchip_pinctrl_register(struct platform_device *pdev,
1685 struct rockchip_pinctrl *info)
1687 struct pinctrl_desc *ctrldesc = &info->pctl;
1688 struct pinctrl_pin_desc *pindesc, *pdesc;
1689 struct rockchip_pin_bank *pin_bank;
1693 ctrldesc->name = "rockchip-pinctrl";
1694 ctrldesc->owner = THIS_MODULE;
1695 ctrldesc->pctlops = &rockchip_pctrl_ops;
1696 ctrldesc->pmxops = &rockchip_pmx_ops;
1697 ctrldesc->confops = &rockchip_pinconf_ops;
1699 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1700 info->ctrl->nr_pins, GFP_KERNEL);
1702 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1705 ctrldesc->pins = pindesc;
1706 ctrldesc->npins = info->ctrl->nr_pins;
1709 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1710 pin_bank = &info->ctrl->pin_banks[bank];
1711 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1713 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1714 pin_bank->name, pin);
1719 ret = rockchip_pinctrl_parse_dt(pdev, info);
1723 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1724 if (IS_ERR(info->pctl_dev)) {
1725 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1726 return PTR_ERR(info->pctl_dev);
1729 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1730 pin_bank = &info->ctrl->pin_banks[bank];
1731 pin_bank->grange.name = pin_bank->name;
1732 pin_bank->grange.id = bank;
1733 pin_bank->grange.pin_base = pin_bank->pin_base;
1734 pin_bank->grange.base = pin_bank->gpio_chip.base;
1735 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1736 pin_bank->grange.gc = &pin_bank->gpio_chip;
1737 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1747 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1749 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1750 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1751 unsigned long flags;
1754 clk_enable(bank->clk);
1755 spin_lock_irqsave(&bank->slock, flags);
1758 data &= ~BIT(offset);
1760 data |= BIT(offset);
1763 spin_unlock_irqrestore(&bank->slock, flags);
1764 clk_disable(bank->clk);
1768 * Returns the level of the pin for input direction and setting of the DR
1769 * register for output gpios.
1771 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1773 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1776 clk_enable(bank->clk);
1777 data = readl(bank->reg_base + GPIO_EXT_PORT);
1778 clk_disable(bank->clk);
1785 * gpiolib gpio_direction_input callback function. The setting of the pin
1786 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1789 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1791 return pinctrl_gpio_direction_input(gc->base + offset);
1795 * gpiolib gpio_direction_output callback function. The setting of the pin
1796 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1799 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1800 unsigned offset, int value)
1802 rockchip_gpio_set(gc, offset, value);
1803 return pinctrl_gpio_direction_output(gc->base + offset);
1807 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1808 * and a virtual IRQ, if not already present.
1810 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1812 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1818 clk_enable(bank->clk);
1819 virq = irq_create_mapping(bank->domain, offset);
1820 clk_disable(bank->clk);
1822 return (virq) ? : -ENXIO;
1825 static const struct gpio_chip rockchip_gpiolib_chip = {
1826 .request = gpiochip_generic_request,
1827 .free = gpiochip_generic_free,
1828 .set = rockchip_gpio_set,
1829 .get = rockchip_gpio_get,
1830 .get_direction = rockchip_gpio_get_direction,
1831 .direction_input = rockchip_gpio_direction_input,
1832 .direction_output = rockchip_gpio_direction_output,
1833 .to_irq = rockchip_gpio_to_irq,
1834 .owner = THIS_MODULE,
1838 * Interrupt handling
1841 static void rockchip_irq_demux(struct irq_desc *desc)
1843 struct irq_chip *chip = irq_desc_get_chip(desc);
1844 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
1847 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1849 chained_irq_enter(chip, desc);
1851 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1854 unsigned int irq, virq;
1858 virq = irq_linear_revmap(bank->domain, irq);
1861 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1865 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1868 * Triggering IRQ on both rising and falling edge
1869 * needs manual intervention.
1871 if (bank->toggle_edge_mode & BIT(irq)) {
1872 u32 data, data_old, polarity;
1873 unsigned long flags;
1875 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1877 spin_lock_irqsave(&bank->slock, flags);
1879 polarity = readl_relaxed(bank->reg_base +
1881 if (data & BIT(irq))
1882 polarity &= ~BIT(irq);
1884 polarity |= BIT(irq);
1886 bank->reg_base + GPIO_INT_POLARITY);
1888 spin_unlock_irqrestore(&bank->slock, flags);
1891 data = readl_relaxed(bank->reg_base +
1893 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
1896 generic_handle_irq(virq);
1899 chained_irq_exit(chip, desc);
1902 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1904 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1905 struct rockchip_pin_bank *bank = gc->private;
1906 u32 mask = BIT(d->hwirq);
1910 unsigned long flags;
1913 /* make sure the pin is configured as gpio input */
1914 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1918 clk_enable(bank->clk);
1919 spin_lock_irqsave(&bank->slock, flags);
1921 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1923 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1925 spin_unlock_irqrestore(&bank->slock, flags);
1927 if (type & IRQ_TYPE_EDGE_BOTH)
1928 irq_set_handler_locked(d, handle_edge_irq);
1930 irq_set_handler_locked(d, handle_level_irq);
1932 spin_lock_irqsave(&bank->slock, flags);
1935 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1936 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1939 case IRQ_TYPE_EDGE_BOTH:
1940 bank->toggle_edge_mode |= mask;
1944 * Determine gpio state. If 1 next interrupt should be falling
1947 data = readl(bank->reg_base + GPIO_EXT_PORT);
1953 case IRQ_TYPE_EDGE_RISING:
1954 bank->toggle_edge_mode &= ~mask;
1958 case IRQ_TYPE_EDGE_FALLING:
1959 bank->toggle_edge_mode &= ~mask;
1963 case IRQ_TYPE_LEVEL_HIGH:
1964 bank->toggle_edge_mode &= ~mask;
1968 case IRQ_TYPE_LEVEL_LOW:
1969 bank->toggle_edge_mode &= ~mask;
1975 spin_unlock_irqrestore(&bank->slock, flags);
1976 clk_disable(bank->clk);
1980 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1981 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1984 spin_unlock_irqrestore(&bank->slock, flags);
1985 clk_disable(bank->clk);
1990 static void rockchip_irq_suspend(struct irq_data *d)
1992 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1993 struct rockchip_pin_bank *bank = gc->private;
1995 clk_enable(bank->clk);
1996 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1997 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
1998 clk_disable(bank->clk);
2001 static void rockchip_irq_resume(struct irq_data *d)
2003 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2004 struct rockchip_pin_bank *bank = gc->private;
2006 clk_enable(bank->clk);
2007 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2008 clk_disable(bank->clk);
2011 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2013 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2014 struct rockchip_pin_bank *bank = gc->private;
2016 clk_enable(bank->clk);
2017 irq_gc_mask_clr_bit(d);
2020 static void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2022 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2023 struct rockchip_pin_bank *bank = gc->private;
2025 irq_gc_mask_set_bit(d);
2026 clk_disable(bank->clk);
2029 static int rockchip_interrupts_register(struct platform_device *pdev,
2030 struct rockchip_pinctrl *info)
2032 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2033 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2034 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2035 struct irq_chip_generic *gc;
2039 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2041 dev_warn(&pdev->dev, "bank %s is not valid\n",
2046 ret = clk_enable(bank->clk);
2048 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2053 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2054 &irq_generic_chip_ops, NULL);
2055 if (!bank->domain) {
2056 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2058 clk_disable(bank->clk);
2062 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2063 "rockchip_gpio_irq", handle_level_irq,
2064 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2066 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2068 irq_domain_remove(bank->domain);
2069 clk_disable(bank->clk);
2074 * Linux assumes that all interrupts start out disabled/masked.
2075 * Our driver only uses the concept of masked and always keeps
2076 * things enabled, so for us that's all masked and all enabled.
2078 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2079 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2081 gc = irq_get_domain_generic_chip(bank->domain, 0);
2082 gc->reg_base = bank->reg_base;
2084 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2085 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2086 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2087 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2088 gc->chip_types[0].chip.irq_unmask =
2089 rockchip_irq_gc_mask_clr_bit;
2090 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2091 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2092 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2093 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2094 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2096 irq_set_chained_handler_and_data(bank->irq,
2097 rockchip_irq_demux, bank);
2099 /* map the gpio irqs here, when the clock is still running */
2100 for (j = 0 ; j < 32 ; j++)
2101 irq_create_mapping(bank->domain, j);
2103 clk_disable(bank->clk);
2109 static int rockchip_gpiolib_register(struct platform_device *pdev,
2110 struct rockchip_pinctrl *info)
2112 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2113 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2114 struct gpio_chip *gc;
2118 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2120 dev_warn(&pdev->dev, "bank %s is not valid\n",
2125 bank->gpio_chip = rockchip_gpiolib_chip;
2127 gc = &bank->gpio_chip;
2128 gc->base = bank->pin_base;
2129 gc->ngpio = bank->nr_pins;
2130 gc->parent = &pdev->dev;
2131 gc->of_node = bank->of_node;
2132 gc->label = bank->name;
2134 ret = gpiochip_add_data(gc, bank);
2136 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2142 rockchip_interrupts_register(pdev, info);
2147 for (--i, --bank; i >= 0; --i, --bank) {
2150 gpiochip_remove(&bank->gpio_chip);
2155 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2156 struct rockchip_pinctrl *info)
2158 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2159 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2162 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2165 gpiochip_remove(&bank->gpio_chip);
2171 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2172 struct rockchip_pinctrl *info)
2174 struct resource res;
2177 if (of_address_to_resource(bank->of_node, 0, &res)) {
2178 dev_err(info->dev, "cannot find IO resource for bank\n");
2182 bank->reg_base = devm_ioremap_resource(info->dev, &res);
2183 if (IS_ERR(bank->reg_base))
2184 return PTR_ERR(bank->reg_base);
2187 * special case, where parts of the pull setting-registers are
2188 * part of the PMU register space
2190 if (of_device_is_compatible(bank->of_node,
2191 "rockchip,rk3188-gpio-bank0")) {
2192 struct device_node *node;
2194 node = of_parse_phandle(bank->of_node->parent,
2197 if (of_address_to_resource(bank->of_node, 1, &res)) {
2198 dev_err(info->dev, "cannot find IO resource for bank\n");
2202 base = devm_ioremap_resource(info->dev, &res);
2204 return PTR_ERR(base);
2205 rockchip_regmap_config.max_register =
2206 resource_size(&res) - 4;
2207 rockchip_regmap_config.name =
2208 "rockchip,rk3188-gpio-bank0-pull";
2209 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2211 &rockchip_regmap_config);
2216 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2218 bank->clk = of_clk_get(bank->of_node, 0);
2219 if (IS_ERR(bank->clk))
2220 return PTR_ERR(bank->clk);
2222 return clk_prepare(bank->clk);
2225 static const struct of_device_id rockchip_pinctrl_dt_match[];
2227 /* retrieve the soc specific data */
2228 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2229 struct rockchip_pinctrl *d,
2230 struct platform_device *pdev)
2232 const struct of_device_id *match;
2233 struct device_node *node = pdev->dev.of_node;
2234 struct device_node *np;
2235 struct rockchip_pin_ctrl *ctrl;
2236 struct rockchip_pin_bank *bank;
2237 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2239 match = of_match_node(rockchip_pinctrl_dt_match, node);
2240 ctrl = (struct rockchip_pin_ctrl *)match->data;
2242 for_each_child_of_node(node, np) {
2243 if (!of_find_property(np, "gpio-controller", NULL))
2246 bank = ctrl->pin_banks;
2247 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2248 if (!strcmp(bank->name, np->name)) {
2251 if (!rockchip_get_bank_data(bank, d))
2259 grf_offs = ctrl->grf_mux_offset;
2260 pmu_offs = ctrl->pmu_mux_offset;
2261 drv_pmu_offs = ctrl->pmu_drv_offset;
2262 drv_grf_offs = ctrl->grf_drv_offset;
2263 bank = ctrl->pin_banks;
2264 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2267 spin_lock_init(&bank->slock);
2269 bank->pin_base = ctrl->nr_pins;
2270 ctrl->nr_pins += bank->nr_pins;
2272 /* calculate iomux and drv offsets */
2273 for (j = 0; j < 4; j++) {
2274 struct rockchip_iomux *iom = &bank->iomux[j];
2275 struct rockchip_drv *drv = &bank->drv[j];
2278 if (bank_pins >= bank->nr_pins)
2281 /* preset iomux offset value, set new start value */
2282 if (iom->offset >= 0) {
2283 if (iom->type & IOMUX_SOURCE_PMU)
2284 pmu_offs = iom->offset;
2286 grf_offs = iom->offset;
2287 } else { /* set current iomux offset */
2288 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2289 pmu_offs : grf_offs;
2292 /* preset drv offset value, set new start value */
2293 if (drv->offset >= 0) {
2294 if (iom->type & IOMUX_SOURCE_PMU)
2295 drv_pmu_offs = drv->offset;
2297 drv_grf_offs = drv->offset;
2298 } else { /* set current drv offset */
2299 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2300 drv_pmu_offs : drv_grf_offs;
2303 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2304 i, j, iom->offset, drv->offset);
2307 * Increase offset according to iomux width.
2308 * 4bit iomux'es are spread over two registers.
2310 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
2311 if (iom->type & IOMUX_SOURCE_PMU)
2317 * Increase offset according to drv width.
2318 * 3bit drive-strenth'es are spread over two registers.
2320 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2321 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2326 if (iom->type & IOMUX_SOURCE_PMU)
2327 drv_pmu_offs += inc;
2329 drv_grf_offs += inc;
2338 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2339 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2341 static u32 rk3288_grf_gpio6c_iomux;
2343 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2345 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2346 int ret = pinctrl_force_sleep(info->pctl_dev);
2352 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2353 * the setting here, and restore it at resume.
2355 if (info->ctrl->type == RK3288) {
2356 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2357 &rk3288_grf_gpio6c_iomux);
2359 pinctrl_force_default(info->pctl_dev);
2367 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2369 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2372 if (info->ctrl->type == RK3288) {
2373 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2374 rk3288_grf_gpio6c_iomux |
2375 GPIO6C6_SEL_WRITE_ENABLE);
2380 return pinctrl_force_default(info->pctl_dev);
2383 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2384 rockchip_pinctrl_resume);
2386 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2388 struct rockchip_pinctrl *info;
2389 struct device *dev = &pdev->dev;
2390 struct rockchip_pin_ctrl *ctrl;
2391 struct device_node *np = pdev->dev.of_node, *node;
2392 struct resource *res;
2396 if (!dev->of_node) {
2397 dev_err(dev, "device tree node not found\n");
2401 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2407 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2409 dev_err(dev, "driver data not available\n");
2414 node = of_parse_phandle(np, "rockchip,grf", 0);
2416 info->regmap_base = syscon_node_to_regmap(node);
2417 if (IS_ERR(info->regmap_base))
2418 return PTR_ERR(info->regmap_base);
2420 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2421 base = devm_ioremap_resource(&pdev->dev, res);
2423 return PTR_ERR(base);
2425 rockchip_regmap_config.max_register = resource_size(res) - 4;
2426 rockchip_regmap_config.name = "rockchip,pinctrl";
2427 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2428 &rockchip_regmap_config);
2430 /* to check for the old dt-bindings */
2431 info->reg_size = resource_size(res);
2433 /* Honor the old binding, with pull registers as 2nd resource */
2434 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2435 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2436 base = devm_ioremap_resource(&pdev->dev, res);
2438 return PTR_ERR(base);
2440 rockchip_regmap_config.max_register =
2441 resource_size(res) - 4;
2442 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2443 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2445 &rockchip_regmap_config);
2449 /* try to find the optional reference to the pmu syscon */
2450 node = of_parse_phandle(np, "rockchip,pmu", 0);
2452 info->regmap_pmu = syscon_node_to_regmap(node);
2453 if (IS_ERR(info->regmap_pmu))
2454 return PTR_ERR(info->regmap_pmu);
2457 ret = rockchip_gpiolib_register(pdev, info);
2461 ret = rockchip_pinctrl_register(pdev, info);
2463 rockchip_gpiolib_unregister(pdev, info);
2467 platform_set_drvdata(pdev, info);
2472 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2473 PIN_BANK(0, 32, "gpio0"),
2474 PIN_BANK(1, 32, "gpio1"),
2475 PIN_BANK(2, 32, "gpio2"),
2476 PIN_BANK(3, 32, "gpio3"),
2479 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2480 .pin_banks = rk2928_pin_banks,
2481 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2482 .label = "RK2928-GPIO",
2484 .grf_mux_offset = 0xa8,
2485 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2488 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2489 PIN_BANK(0, 32, "gpio0"),
2490 PIN_BANK(1, 32, "gpio1"),
2491 PIN_BANK(2, 32, "gpio2"),
2494 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2495 .pin_banks = rk3036_pin_banks,
2496 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2497 .label = "RK3036-GPIO",
2499 .grf_mux_offset = 0xa8,
2500 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2503 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2504 PIN_BANK(0, 32, "gpio0"),
2505 PIN_BANK(1, 32, "gpio1"),
2506 PIN_BANK(2, 32, "gpio2"),
2507 PIN_BANK(3, 32, "gpio3"),
2508 PIN_BANK(4, 32, "gpio4"),
2509 PIN_BANK(6, 16, "gpio6"),
2512 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2513 .pin_banks = rk3066a_pin_banks,
2514 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2515 .label = "RK3066a-GPIO",
2517 .grf_mux_offset = 0xa8,
2518 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2521 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2522 PIN_BANK(0, 32, "gpio0"),
2523 PIN_BANK(1, 32, "gpio1"),
2524 PIN_BANK(2, 32, "gpio2"),
2525 PIN_BANK(3, 32, "gpio3"),
2528 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2529 .pin_banks = rk3066b_pin_banks,
2530 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2531 .label = "RK3066b-GPIO",
2533 .grf_mux_offset = 0x60,
2536 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2537 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2538 PIN_BANK(1, 32, "gpio1"),
2539 PIN_BANK(2, 32, "gpio2"),
2540 PIN_BANK(3, 32, "gpio3"),
2543 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2544 .pin_banks = rk3188_pin_banks,
2545 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2546 .label = "RK3188-GPIO",
2548 .grf_mux_offset = 0x60,
2549 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2552 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2553 PIN_BANK(0, 32, "gpio0"),
2554 PIN_BANK(1, 32, "gpio1"),
2555 PIN_BANK(2, 32, "gpio2"),
2556 PIN_BANK(3, 32, "gpio3"),
2559 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2560 .pin_banks = rk3228_pin_banks,
2561 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2562 .label = "RK3228-GPIO",
2564 .grf_mux_offset = 0x0,
2565 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2566 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2569 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2570 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2575 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2580 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2581 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2582 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2587 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2592 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2593 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2598 PIN_BANK(8, 16, "gpio8"),
2601 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2602 .pin_banks = rk3288_pin_banks,
2603 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2604 .label = "RK3288-GPIO",
2606 .grf_mux_offset = 0x0,
2607 .pmu_mux_offset = 0x84,
2608 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2609 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
2612 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2613 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2618 PIN_BANK(1, 32, "gpio1"),
2619 PIN_BANK(2, 32, "gpio2"),
2620 PIN_BANK(3, 32, "gpio3"),
2623 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2624 .pin_banks = rk3368_pin_banks,
2625 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2626 .label = "RK3368-GPIO",
2628 .grf_mux_offset = 0x0,
2629 .pmu_mux_offset = 0x0,
2630 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2631 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2634 static struct rockchip_pin_bank rk3399_pin_banks[] = {
2635 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
2640 DRV_TYPE_IO_1V8_ONLY,
2641 DRV_TYPE_IO_1V8_ONLY,
2642 DRV_TYPE_IO_DEFAULT,
2643 DRV_TYPE_IO_DEFAULT,
2648 PULL_TYPE_IO_1V8_ONLY,
2649 PULL_TYPE_IO_1V8_ONLY,
2650 PULL_TYPE_IO_DEFAULT,
2651 PULL_TYPE_IO_DEFAULT
2653 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2657 DRV_TYPE_IO_1V8_OR_3V0,
2658 DRV_TYPE_IO_1V8_OR_3V0,
2659 DRV_TYPE_IO_1V8_OR_3V0,
2660 DRV_TYPE_IO_1V8_OR_3V0,
2666 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2667 DRV_TYPE_IO_1V8_OR_3V0,
2668 DRV_TYPE_IO_1V8_ONLY,
2669 DRV_TYPE_IO_1V8_ONLY,
2670 PULL_TYPE_IO_DEFAULT,
2671 PULL_TYPE_IO_DEFAULT,
2672 PULL_TYPE_IO_1V8_ONLY,
2673 PULL_TYPE_IO_1V8_ONLY
2675 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2676 DRV_TYPE_IO_3V3_ONLY,
2677 DRV_TYPE_IO_3V3_ONLY,
2678 DRV_TYPE_IO_1V8_OR_3V0
2680 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2681 DRV_TYPE_IO_1V8_3V0_AUTO,
2682 DRV_TYPE_IO_1V8_OR_3V0,
2683 DRV_TYPE_IO_1V8_OR_3V0
2687 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2688 .pin_banks = rk3399_pin_banks,
2689 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
2690 .label = "RK3399-GPIO",
2692 .grf_mux_offset = 0xe000,
2693 .pmu_mux_offset = 0x0,
2694 .grf_drv_offset = 0xe100,
2695 .pmu_drv_offset = 0x80,
2696 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
2697 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
2700 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2701 { .compatible = "rockchip,rk2928-pinctrl",
2702 .data = (void *)&rk2928_pin_ctrl },
2703 { .compatible = "rockchip,rk3036-pinctrl",
2704 .data = (void *)&rk3036_pin_ctrl },
2705 { .compatible = "rockchip,rk3066a-pinctrl",
2706 .data = (void *)&rk3066a_pin_ctrl },
2707 { .compatible = "rockchip,rk3066b-pinctrl",
2708 .data = (void *)&rk3066b_pin_ctrl },
2709 { .compatible = "rockchip,rk3188-pinctrl",
2710 .data = (void *)&rk3188_pin_ctrl },
2711 { .compatible = "rockchip,rk3228-pinctrl",
2712 .data = (void *)&rk3228_pin_ctrl },
2713 { .compatible = "rockchip,rk3288-pinctrl",
2714 .data = (void *)&rk3288_pin_ctrl },
2715 { .compatible = "rockchip,rk3368-pinctrl",
2716 .data = (void *)&rk3368_pin_ctrl },
2717 { .compatible = "rockchip,rk3399-pinctrl",
2718 .data = (void *)&rk3399_pin_ctrl },
2722 static struct platform_driver rockchip_pinctrl_driver = {
2723 .probe = rockchip_pinctrl_probe,
2725 .name = "rockchip-pinctrl",
2726 .pm = &rockchip_pinctrl_dev_pm_ops,
2727 .of_match_table = rockchip_pinctrl_dt_match,
2731 static int __init rockchip_pinctrl_drv_register(void)
2733 return platform_driver_register(&rockchip_pinctrl_driver);
2735 postcore_initcall(rockchip_pinctrl_drv_register);