drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         PX30,
  63         RV1108,
  64         RK2928,
  65         RK3066B,
  66         RK3128,
  67         RK3188,
  68         RK3288,
  69         RK3368,
  70         RK3399,
  71 };
  72
  73 /*
  74  * Encode variants of iomux registers into a type variable
  75  */
  76 #define IOMUX_GPIO_ONLY         BIT(0)
  77 #define IOMUX_WIDTH_4BIT        BIT(1)
  78 #define IOMUX_SOURCE_PMU        BIT(2)
  79 #define IOMUX_UNROUTED          BIT(3)
  80 #define IOMUX_WIDTH_3BIT        BIT(4)
  81
  82 /**
  83  * struct rockchip_iomux
  84  * @type: iomux variant using IOMUX_* constants
  85  * @offset: if initialized to -1 it will be autocalculated, by specifying
  86  *          an initial offset value the relevant source offset can be reset
  87  *          to a new value for autocalculating the following iomux registers.
  88  */
  89 struct rockchip_iomux {
  90         int                             type;
  91         int                             offset;
  92 };
  93
  94 /*
  95  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  96  */
  97 enum rockchip_pin_drv_type {
  98         DRV_TYPE_IO_DEFAULT = 0,
  99         DRV_TYPE_IO_1V8_OR_3V0,
 100         DRV_TYPE_IO_1V8_ONLY,
 101         DRV_TYPE_IO_1V8_3V0_AUTO,
 102         DRV_TYPE_IO_3V3_ONLY,
 103         DRV_TYPE_MAX
 104 };
 105
 106 /*
 107  * enum type index corresponding to rockchip_pull_list arrays index.
 108  */
 109 enum rockchip_pin_pull_type {
 110         PULL_TYPE_IO_DEFAULT = 0,
 111         PULL_TYPE_IO_1V8_ONLY,
 112         PULL_TYPE_MAX
 113 };
 114
 115 /**
 116  * struct rockchip_drv
 117  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 118  * @offset: if initialized to -1 it will be autocalculated, by specifying
 119  *          an initial offset value the relevant source offset can be reset
 120  *          to a new value for autocalculating the following drive strength
 121  *          registers. if used chips own cal_drv func instead to calculate
 122  *          registers offset, the variant could be ignored.
 123  */
 124 struct rockchip_drv {
 125         enum rockchip_pin_drv_type      drv_type;
 126         int                             offset;
 127 };
 128
 129 /**
 130  * struct rockchip_pin_bank
 131  * @reg_base: register base of the gpio bank
 132  * @regmap_pull: optional separate register for additional pull settings
 133  * @clk: clock of the gpio bank
 134  * @irq: interrupt of the gpio bank
 135  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 136  * @pin_base: first pin number
 137  * @nr_pins: number of pins in this bank
 138  * @name: name of the bank
 139  * @bank_num: number of the bank, to account for holes
 140  * @iomux: array describing the 4 iomux sources of the bank
 141  * @drv: array describing the 4 drive strength sources of the bank
 142  * @pull_type: array describing the 4 pull type sources of the bank
 143  * @valid: is all necessary information present
 144  * @of_node: dt node of this bank
 145  * @drvdata: common pinctrl basedata
 146  * @domain: irqdomain of the gpio bank
 147  * @gpio_chip: gpiolib chip
 148  * @grange: gpio range
 149  * @slock: spinlock for the gpio bank
 150  * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
 151  * @recalced_mask: bit mask to indicate a need to recalulate the mask
 152  * @route_mask: bits describing the routing pins of per bank
 153  */
 154 struct rockchip_pin_bank {
 155         void __iomem                    *reg_base;
 156         struct regmap                   *regmap_pull;
 157         struct clk                      *clk;
 158         int                             irq;
 159         u32                             saved_masks;
 160         u32                             pin_base;
 161         u8                              nr_pins;
 162         char                            *name;
 163         u8                              bank_num;
 164         struct rockchip_iomux           iomux[4];
 165         struct rockchip_drv             drv[4];
 166         enum rockchip_pin_pull_type     pull_type[4];
 167         bool                            valid;
 168         struct device_node              *of_node;
 169         struct rockchip_pinctrl         *drvdata;
 170         struct irq_domain               *domain;
 171         struct gpio_chip                gpio_chip;
 172         struct pinctrl_gpio_range       grange;
 173         raw_spinlock_t                  slock;
 174         u32                             toggle_edge_mode;
 175         u32                             recalced_mask;
 176         u32                             route_mask;
 177 };
 178
 179 #define PIN_BANK(id, pins, label)                       \
 180         {                                               \
 181                 .bank_num       = id,                   \
 182                 .nr_pins        = pins,                 \
 183                 .name           = label,                \
 184                 .iomux          = {                     \
 185                         { .offset = -1 },               \
 186                         { .offset = -1 },               \
 187                         { .offset = -1 },               \
 188                         { .offset = -1 },               \
 189                 },                                      \
 190         }
 191
 192 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 193         {                                                               \
 194                 .bank_num       = id,                                   \
 195                 .nr_pins        = pins,                                 \
 196                 .name           = label,                                \
 197                 .iomux          = {                                     \
 198                         { .type = iom0, .offset = -1 },                 \
 199                         { .type = iom1, .offset = -1 },                 \
 200                         { .type = iom2, .offset = -1 },                 \
 201                         { .type = iom3, .offset = -1 },                 \
 202                 },                                                      \
 203         }
 204
 205 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 206         {                                                               \
 207                 .bank_num       = id,                                   \
 208                 .nr_pins        = pins,                                 \
 209                 .name           = label,                                \
 210                 .iomux          = {                                     \
 211                         { .offset = -1 },                               \
 212                         { .offset = -1 },                               \
 213                         { .offset = -1 },                               \
 214                         { .offset = -1 },                               \
 215                 },                                                      \
 216                 .drv            = {                                     \
 217                         { .drv_type = type0, .offset = -1 },            \
 218                         { .drv_type = type1, .offset = -1 },            \
 219                         { .drv_type = type2, .offset = -1 },            \
 220                         { .drv_type = type3, .offset = -1 },            \
 221                 },                                                      \
 222         }
 223
 224 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 225                                       drv2, drv3, pull0, pull1,         \
 226                                       pull2, pull3)                     \
 227         {                                                               \
 228                 .bank_num       = id,                                   \
 229                 .nr_pins        = pins,                                 \
 230                 .name           = label,                                \
 231                 .iomux          = {                                     \
 232                         { .offset = -1 },                               \
 233                         { .offset = -1 },                               \
 234                         { .offset = -1 },                               \
 235                         { .offset = -1 },                               \
 236                 },                                                      \
 237                 .drv            = {                                     \
 238                         { .drv_type = drv0, .offset = -1 },             \
 239                         { .drv_type = drv1, .offset = -1 },             \
 240                         { .drv_type = drv2, .offset = -1 },             \
 241                         { .drv_type = drv3, .offset = -1 },             \
 242                 },                                                      \
 243                 .pull_type[0] = pull0,                                  \
 244                 .pull_type[1] = pull1,                                  \
 245                 .pull_type[2] = pull2,                                  \
 246                 .pull_type[3] = pull3,                                  \
 247         }
 248
 249 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 250                                         iom2, iom3, drv0, drv1, drv2,   \
 251                                         drv3, offset0, offset1,         \
 252                                         offset2, offset3)               \
 253         {                                                               \
 254                 .bank_num       = id,                                   \
 255                 .nr_pins        = pins,                                 \
 256                 .name           = label,                                \
 257                 .iomux          = {                                     \
 258                         { .type = iom0, .offset = -1 },                 \
 259                         { .type = iom1, .offset = -1 },                 \
 260                         { .type = iom2, .offset = -1 },                 \
 261                         { .type = iom3, .offset = -1 },                 \
 262                 },                                                      \
 263                 .drv            = {                                     \
 264                         { .drv_type = drv0, .offset = offset0 },        \
 265                         { .drv_type = drv1, .offset = offset1 },        \
 266                         { .drv_type = drv2, .offset = offset2 },        \
 267                         { .drv_type = drv3, .offset = offset3 },        \
 268                 },                                                      \
 269         }
 270
 271 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 272                                               label, iom0, iom1, iom2,  \
 273                                               iom3, drv0, drv1, drv2,   \
 274                                               drv3, offset0, offset1,   \
 275                                               offset2, offset3, pull0,  \
 276                                               pull1, pull2, pull3)      \
 277         {                                                               \
 278                 .bank_num       = id,                                   \
 279                 .nr_pins        = pins,                                 \
 280                 .name           = label,                                \
 281                 .iomux          = {                                     \
 282                         { .type = iom0, .offset = -1 },                 \
 283                         { .type = iom1, .offset = -1 },                 \
 284                         { .type = iom2, .offset = -1 },                 \
 285                         { .type = iom3, .offset = -1 },                 \
 286                 },                                                      \
 287                 .drv            = {                                     \
 288                         { .drv_type = drv0, .offset = offset0 },        \
 289                         { .drv_type = drv1, .offset = offset1 },        \
 290                         { .drv_type = drv2, .offset = offset2 },        \
 291                         { .drv_type = drv3, .offset = offset3 },        \
 292                 },                                                      \
 293                 .pull_type[0] = pull0,                                  \
 294                 .pull_type[1] = pull1,                                  \
 295                 .pull_type[2] = pull2,                                  \
 296                 .pull_type[3] = pull3,                                  \
 297         }
 298
 299 /**
 300  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 301  * @num: bank number.
 302  * @pin: pin number.
 303  * @bit: index at register.
 304  * @reg: register offset.
 305  * @mask: mask bit
 306  */
 307 struct rockchip_mux_recalced_data {
 308         u8 num;
 309         u8 pin;
 310         u32 reg;
 311         u8 bit;
 312         u8 mask;
 313 };
 314
 315 /**
 316  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 317  * @bank_num: bank number.
 318  * @pin: index at register or used to calc index.
 319  * @func: the min pin.
 320  * @route_location: the mux route location (same, pmu, grf).
 321  * @route_offset: the max pin.
 322  * @route_val: the register offset.
 323  */
 324 struct rockchip_mux_route_data {
 325         u8 bank_num;
 326         u8 pin;
 327         u8 func;
 328         u32 route_offset;
 329         u32 route_val;
 330 };
 331
 332 struct rockchip_pin_ctrl {
 333         struct rockchip_pin_bank        *pin_banks;
 334         u32                             nr_banks;
 335         u32                             nr_pins;
 336         char                            *label;
 337         enum rockchip_pinctrl_type      type;
 338         int                             grf_mux_offset;
 339         int                             pmu_mux_offset;
 340         int                             grf_drv_offset;
 341         int                             pmu_drv_offset;
 342         struct rockchip_mux_recalced_data *iomux_recalced;
 343         u32                             niomux_recalced;
 344         struct rockchip_mux_route_data *iomux_routes;
 345         u32                             niomux_routes;
 346
 347         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 348                                     int pin_num, struct regmap **regmap,
 349                                     int *reg, u8 *bit);
 350         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 351                                     int pin_num, struct regmap **regmap,
 352                                     int *reg, u8 *bit);
 353         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 354                                     int pin_num, struct regmap **regmap,
 355                                     int *reg, u8 *bit);
 356 };
 357
 358 struct rockchip_pin_config {
 359         unsigned int            func;
 360         unsigned long           *configs;
 361         unsigned int            nconfigs;
 362 };
 363
 364 /**
 365  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 366  * @name: name of the pin group, used to lookup the group.
 367  * @pins: the pins included in this group.
 368  * @npins: number of pins included in this group.
 369  * @data: local pin configuration
 370  */
 371 struct rockchip_pin_group {
 372         const char                      *name;
 373         unsigned int                    npins;
 374         unsigned int                    *pins;
 375         struct rockchip_pin_config      *data;
 376 };
 377
 378 /**
 379  * struct rockchip_pmx_func: represent a pin function.
 380  * @name: name of the pin function, used to lookup the function.
 381  * @groups: one or more names of pin groups that provide this function.
 382  * @ngroups: number of groups included in @groups.
 383  */
 384 struct rockchip_pmx_func {
 385         const char              *name;
 386         const char              **groups;
 387         u8                      ngroups;
 388 };
 389
 390 struct rockchip_pinctrl {
 391         struct regmap                   *regmap_base;
 392         int                             reg_size;
 393         struct regmap                   *regmap_pull;
 394         struct regmap                   *regmap_pmu;
 395         struct device                   *dev;
 396         struct rockchip_pin_ctrl        *ctrl;
 397         struct pinctrl_desc             pctl;
 398         struct pinctrl_dev              *pctl_dev;
 399         struct rockchip_pin_group       *groups;
 400         unsigned int                    ngroups;
 401         struct rockchip_pmx_func        *functions;
 402         unsigned int                    nfunctions;
 403 };
 404
 405 static struct regmap_config rockchip_regmap_config = {
 406         .reg_bits = 32,
 407         .val_bits = 32,
 408         .reg_stride = 4,
 409 };
 410
 411 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 412                                         const struct rockchip_pinctrl *info,
 413                                         const char *name)
 414 {
 415         int i;
 416
 417         for (i = 0; i < info->ngroups; i++) {
 418                 if (!strcmp(info->groups[i].name, name))
 419                         return &info->groups[i];
 420         }
 421
 422         return NULL;
 423 }
 424
 425 /*
 426  * given a pin number that is local to a pin controller, find out the pin bank
 427  * and the register base of the pin bank.
 428  */
 429 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 430                                                                 unsigned pin)
 431 {
 432         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 433
 434         while (pin >= (b->pin_base + b->nr_pins))
 435                 b++;
 436
 437         return b;
 438 }
 439
 440 static struct rockchip_pin_bank *bank_num_to_bank(
 441                                         struct rockchip_pinctrl *info,
 442                                         unsigned num)
 443 {
 444         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 445         int i;
 446
 447         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 448                 if (b->bank_num == num)
 449                         return b;
 450         }
 451
 452         return ERR_PTR(-EINVAL);
 453 }
 454
 455 /*
 456  * Pinctrl_ops handling
 457  */
 458
 459 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 460 {
 461         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 462
 463         return info->ngroups;
 464 }
 465
 466 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 467                                                         unsigned selector)
 468 {
 469         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 470
 471         return info->groups[selector].name;
 472 }
 473
 474 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 475                                       unsigned selector, const unsigned **pins,
 476                                       unsigned *npins)
 477 {
 478         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 479
 480         if (selector >= info->ngroups)
 481                 return -EINVAL;
 482
 483         *pins = info->groups[selector].pins;
 484         *npins = info->groups[selector].npins;
 485
 486         return 0;
 487 }
 488
 489 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 490                                  struct device_node *np,
 491                                  struct pinctrl_map **map, unsigned *num_maps)
 492 {
 493         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 494         const struct rockchip_pin_group *grp;
 495         struct pinctrl_map *new_map;
 496         struct device_node *parent;
 497         int map_num = 1;
 498         int i;
 499
 500         /*
 501          * first find the group of this node and check if we need to create
 502          * config maps for pins
 503          */
 504         grp = pinctrl_name_to_group(info, np->name);
 505         if (!grp) {
 506                 dev_err(info->dev, "unable to find group for node %s\n",
 507                         np->name);
 508                 return -EINVAL;
 509         }
 510
 511         map_num += grp->npins;
 512
 513         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 514         if (!new_map)
 515                 return -ENOMEM;
 516
 517         *map = new_map;
 518         *num_maps = map_num;
 519
 520         /* create mux map */
 521         parent = of_get_parent(np);
 522         if (!parent) {
 523                 kfree(new_map);
 524                 return -EINVAL;
 525         }
 526         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 527         new_map[0].data.mux.function = parent->name;
 528         new_map[0].data.mux.group = np->name;
 529         of_node_put(parent);
 530
 531         /* create config map */
 532         new_map++;
 533         for (i = 0; i < grp->npins; i++) {
 534                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 535                 new_map[i].data.configs.group_or_pin =
 536                                 pin_get_name(pctldev, grp->pins[i]);
 537                 new_map[i].data.configs.configs = grp->data[i].configs;
 538                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 539         }
 540
 541         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 542                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 543
 544         return 0;
 545 }
 546
 547 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 548                                     struct pinctrl_map *map, unsigned num_maps)
 549 {
 550         kfree(map);
 551 }
 552
 553 static const struct pinctrl_ops rockchip_pctrl_ops = {
 554         .get_groups_count       = rockchip_get_groups_count,
 555         .get_group_name         = rockchip_get_group_name,
 556         .get_group_pins         = rockchip_get_group_pins,
 557         .dt_node_to_map         = rockchip_dt_node_to_map,
 558         .dt_free_map            = rockchip_dt_free_map,
 559 };
 560
 561 /*
 562  * Hardware access
 563  */
 564
 565 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 566         {
 567                 .num = 1,
 568                 .pin = 0,
 569                 .reg = 0x418,
 570                 .bit = 0,
 571                 .mask = 0x3
 572         }, {
 573                 .num = 1,
 574                 .pin = 1,
 575                 .reg = 0x418,
 576                 .bit = 2,
 577                 .mask = 0x3
 578         }, {
 579                 .num = 1,
 580                 .pin = 2,
 581                 .reg = 0x418,
 582                 .bit = 4,
 583                 .mask = 0x3
 584         }, {
 585                 .num = 1,
 586                 .pin = 3,
 587                 .reg = 0x418,
 588                 .bit = 6,
 589                 .mask = 0x3
 590         }, {
 591                 .num = 1,
 592                 .pin = 4,
 593                 .reg = 0x418,
 594                 .bit = 8,
 595                 .mask = 0x3
 596         }, {
 597                 .num = 1,
 598                 .pin = 5,
 599                 .reg = 0x418,
 600                 .bit = 10,
 601                 .mask = 0x3
 602         }, {
 603                 .num = 1,
 604                 .pin = 6,
 605                 .reg = 0x418,
 606                 .bit = 12,
 607                 .mask = 0x3
 608         }, {
 609                 .num = 1,
 610                 .pin = 7,
 611                 .reg = 0x418,
 612                 .bit = 14,
 613                 .mask = 0x3
 614         }, {
 615                 .num = 1,
 616                 .pin = 8,
 617                 .reg = 0x41c,
 618                 .bit = 0,
 619                 .mask = 0x3
 620         }, {
 621                 .num = 1,
 622                 .pin = 9,
 623                 .reg = 0x41c,
 624                 .bit = 2,
 625                 .mask = 0x3
 626         },
 627 };
 628
 629 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 630         {
 631                 .num = 2,
 632                 .pin = 20,
 633                 .reg = 0xe8,
 634                 .bit = 0,
 635                 .mask = 0x7
 636         }, {
 637                 .num = 2,
 638                 .pin = 21,
 639                 .reg = 0xe8,
 640                 .bit = 4,
 641                 .mask = 0x7
 642         }, {
 643                 .num = 2,
 644                 .pin = 22,
 645                 .reg = 0xe8,
 646                 .bit = 8,
 647                 .mask = 0x7
 648         }, {
 649                 .num = 2,
 650                 .pin = 23,
 651                 .reg = 0xe8,
 652                 .bit = 12,
 653                 .mask = 0x7
 654         }, {
 655                 .num = 2,
 656                 .pin = 24,
 657                 .reg = 0xd4,
 658                 .bit = 12,
 659                 .mask = 0x7
 660         },
 661 };
 662
 663 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 664         {
 665                 .num = 2,
 666                 .pin = 12,
 667                 .reg = 0x24,
 668                 .bit = 8,
 669                 .mask = 0x3
 670         }, {
 671                 .num = 2,
 672                 .pin = 15,
 673                 .reg = 0x28,
 674                 .bit = 0,
 675                 .mask = 0x7
 676         }, {
 677                 .num = 2,
 678                 .pin = 23,
 679                 .reg = 0x30,
 680                 .bit = 14,
 681                 .mask = 0x3
 682         },
 683 };
 684
 685 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 686                                       int *reg, u8 *bit, int *mask)
 687 {
 688         struct rockchip_pinctrl *info = bank->drvdata;
 689         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 690         struct rockchip_mux_recalced_data *data;
 691         int i;
 692
 693         for (i = 0; i < ctrl->niomux_recalced; i++) {
 694                 data = &ctrl->iomux_recalced[i];
 695                 if (data->num == bank->bank_num &&
 696                     data->pin == pin)
 697                         break;
 698         }
 699
 700         if (i >= ctrl->niomux_recalced)
 701                 return;
 702
 703         *reg = data->reg;
 704         *mask = data->mask;
 705         *bit = data->bit;
 706 }
 707
 708 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 709         {
 710                 /* cif-d2m0 */
 711                 .bank_num = 2,
 712                 .pin = 0,
 713                 .func = 1,
 714                 .route_offset = 0x184,
 715                 .route_val = BIT(16 + 7),
 716         }, {
 717                 /* cif-d2m1 */
 718                 .bank_num = 3,
 719                 .pin = 3,
 720                 .func = 3,
 721                 .route_offset = 0x184,
 722                 .route_val = BIT(16 + 7) | BIT(7),
 723         }, {
 724                 /* pdm-m0 */
 725                 .bank_num = 3,
 726                 .pin = 22,
 727                 .func = 2,
 728                 .route_offset = 0x184,
 729                 .route_val = BIT(16 + 8),
 730         }, {
 731                 /* pdm-m1 */
 732                 .bank_num = 2,
 733                 .pin = 22,
 734                 .func = 1,
 735                 .route_offset = 0x184,
 736                 .route_val = BIT(16 + 8) | BIT(8),
 737         }, {
 738                 /* uart2-rxm0 */
 739                 .bank_num = 1,
 740                 .pin = 27,
 741                 .func = 2,
 742                 .route_offset = 0x184,
 743                 .route_val = BIT(16 + 10),
 744         }, {
 745                 /* uart2-rxm1 */
 746                 .bank_num = 2,
 747                 .pin = 14,
 748                 .func = 2,
 749                 .route_offset = 0x184,
 750                 .route_val = BIT(16 + 10) | BIT(10),
 751         }, {
 752                 /* uart3-rxm0 */
 753                 .bank_num = 0,
 754                 .pin = 17,
 755                 .func = 2,
 756                 .route_offset = 0x184,
 757                 .route_val = BIT(16 + 9),
 758         }, {
 759                 /* uart3-rxm1 */
 760                 .bank_num = 1,
 761                 .pin = 15,
 762                 .func = 2,
 763                 .route_offset = 0x184,
 764                 .route_val = BIT(16 + 9) | BIT(9),
 765         },
 766 };
 767
 768 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 769         {
 770                 /* spi-0 */
 771                 .bank_num = 1,
 772                 .pin = 10,
 773                 .func = 1,
 774                 .route_offset = 0x144,
 775                 .route_val = BIT(16 + 3) | BIT(16 + 4),
 776         }, {
 777                 /* spi-1 */
 778                 .bank_num = 1,
 779                 .pin = 27,
 780                 .func = 3,
 781                 .route_offset = 0x144,
 782                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
 783         }, {
 784                 /* spi-2 */
 785                 .bank_num = 0,
 786                 .pin = 13,
 787                 .func = 2,
 788                 .route_offset = 0x144,
 789                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
 790         }, {
 791                 /* i2s-0 */
 792                 .bank_num = 1,
 793                 .pin = 5,
 794                 .func = 1,
 795                 .route_offset = 0x144,
 796                 .route_val = BIT(16 + 5),
 797         }, {
 798                 /* i2s-1 */
 799                 .bank_num = 0,
 800                 .pin = 14,
 801                 .func = 1,
 802                 .route_offset = 0x144,
 803                 .route_val = BIT(16 + 5) | BIT(5),
 804         }, {
 805                 /* emmc-0 */
 806                 .bank_num = 1,
 807                 .pin = 22,
 808                 .func = 2,
 809                 .route_offset = 0x144,
 810                 .route_val = BIT(16 + 6),
 811         }, {
 812                 /* emmc-1 */
 813                 .bank_num = 2,
 814                 .pin = 4,
 815                 .func = 2,
 816                 .route_offset = 0x144,
 817                 .route_val = BIT(16 + 6) | BIT(6),
 818         },
 819 };
 820
 821 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 822         {
 823                 /* pwm0-0 */
 824                 .bank_num = 0,
 825                 .pin = 26,
 826                 .func = 1,
 827                 .route_offset = 0x50,
 828                 .route_val = BIT(16),
 829         }, {
 830                 /* pwm0-1 */
 831                 .bank_num = 3,
 832                 .pin = 21,
 833                 .func = 1,
 834                 .route_offset = 0x50,
 835                 .route_val = BIT(16) | BIT(0),
 836         }, {
 837                 /* pwm1-0 */
 838                 .bank_num = 0,
 839                 .pin = 27,
 840                 .func = 1,
 841                 .route_offset = 0x50,
 842                 .route_val = BIT(16 + 1),
 843         }, {
 844                 /* pwm1-1 */
 845                 .bank_num = 0,
 846                 .pin = 30,
 847                 .func = 2,
 848                 .route_offset = 0x50,
 849                 .route_val = BIT(16 + 1) | BIT(1),
 850         }, {
 851                 /* pwm2-0 */
 852                 .bank_num = 0,
 853                 .pin = 28,
 854                 .func = 1,
 855                 .route_offset = 0x50,
 856                 .route_val = BIT(16 + 2),
 857         }, {
 858                 /* pwm2-1 */
 859                 .bank_num = 1,
 860                 .pin = 12,
 861                 .func = 2,
 862                 .route_offset = 0x50,
 863                 .route_val = BIT(16 + 2) | BIT(2),
 864         }, {
 865                 /* pwm3-0 */
 866                 .bank_num = 3,
 867                 .pin = 26,
 868                 .func = 1,
 869                 .route_offset = 0x50,
 870                 .route_val = BIT(16 + 3),
 871         }, {
 872                 /* pwm3-1 */
 873                 .bank_num = 1,
 874                 .pin = 11,
 875                 .func = 2,
 876                 .route_offset = 0x50,
 877                 .route_val = BIT(16 + 3) | BIT(3),
 878         }, {
 879                 /* sdio-0_d0 */
 880                 .bank_num = 1,
 881                 .pin = 1,
 882                 .func = 1,
 883                 .route_offset = 0x50,
 884                 .route_val = BIT(16 + 4),
 885         }, {
 886                 /* sdio-1_d0 */
 887                 .bank_num = 3,
 888                 .pin = 2,
 889                 .func = 1,
 890                 .route_offset = 0x50,
 891                 .route_val = BIT(16 + 4) | BIT(4),
 892         }, {
 893                 /* spi-0_rx */
 894                 .bank_num = 0,
 895                 .pin = 13,
 896                 .func = 2,
 897                 .route_offset = 0x50,
 898                 .route_val = BIT(16 + 5),
 899         }, {
 900                 /* spi-1_rx */
 901                 .bank_num = 2,
 902                 .pin = 0,
 903                 .func = 2,
 904                 .route_offset = 0x50,
 905                 .route_val = BIT(16 + 5) | BIT(5),
 906         }, {
 907                 /* emmc-0_cmd */
 908                 .bank_num = 1,
 909                 .pin = 22,
 910                 .func = 2,
 911                 .route_offset = 0x50,
 912                 .route_val = BIT(16 + 7),
 913         }, {
 914                 /* emmc-1_cmd */
 915                 .bank_num = 2,
 916                 .pin = 4,
 917                 .func = 2,
 918                 .route_offset = 0x50,
 919                 .route_val = BIT(16 + 7) | BIT(7),
 920         }, {
 921                 /* uart2-0_rx */
 922                 .bank_num = 1,
 923                 .pin = 19,
 924                 .func = 2,
 925                 .route_offset = 0x50,
 926                 .route_val = BIT(16 + 8),
 927         }, {
 928                 /* uart2-1_rx */
 929                 .bank_num = 1,
 930                 .pin = 10,
 931                 .func = 2,
 932                 .route_offset = 0x50,
 933                 .route_val = BIT(16 + 8) | BIT(8),
 934         }, {
 935                 /* uart1-0_rx */
 936                 .bank_num = 1,
 937                 .pin = 10,
 938                 .func = 1,
 939                 .route_offset = 0x50,
 940                 .route_val = BIT(16 + 11),
 941         }, {
 942                 /* uart1-1_rx */
 943                 .bank_num = 3,
 944                 .pin = 13,
 945                 .func = 1,
 946                 .route_offset = 0x50,
 947                 .route_val = BIT(16 + 11) | BIT(11),
 948         },
 949 };
 950
 951 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 952         {
 953                 /* edphdmi_cecinoutt1 */
 954                 .bank_num = 7,
 955                 .pin = 16,
 956                 .func = 2,
 957                 .route_offset = 0x264,
 958                 .route_val = BIT(16 + 12) | BIT(12),
 959         }, {
 960                 /* edphdmi_cecinout */
 961                 .bank_num = 7,
 962                 .pin = 23,
 963                 .func = 4,
 964                 .route_offset = 0x264,
 965                 .route_val = BIT(16 + 12),
 966         },
 967 };
 968
 969 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 970         {
 971                 /* uart2dbg_rxm0 */
 972                 .bank_num = 1,
 973                 .pin = 1,
 974                 .func = 2,
 975                 .route_offset = 0x50,
 976                 .route_val = BIT(16) | BIT(16 + 1),
 977         }, {
 978                 /* uart2dbg_rxm1 */
 979                 .bank_num = 2,
 980                 .pin = 1,
 981                 .func = 1,
 982                 .route_offset = 0x50,
 983                 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
 984         }, {
 985                 /* gmac-m1_rxd0 */
 986                 .bank_num = 1,
 987                 .pin = 11,
 988                 .func = 2,
 989                 .route_offset = 0x50,
 990                 .route_val = BIT(16 + 2) | BIT(2),
 991         }, {
 992                 /* gmac-m1-optimized_rxd3 */
 993                 .bank_num = 1,
 994                 .pin = 14,
 995                 .func = 2,
 996                 .route_offset = 0x50,
 997                 .route_val = BIT(16 + 10) | BIT(10),
 998         }, {
 999                 /* pdm_sdi0m0 */
1000                 .bank_num = 2,
1001                 .pin = 19,
1002                 .func = 2,
1003                 .route_offset = 0x50,
1004                 .route_val = BIT(16 + 3),
1005         }, {
1006                 /* pdm_sdi0m1 */
1007                 .bank_num = 1,
1008                 .pin = 23,
1009                 .func = 3,
1010                 .route_offset = 0x50,
1011                 .route_val =  BIT(16 + 3) | BIT(3),
1012         }, {
1013                 /* spi_rxdm2 */
1014                 .bank_num = 3,
1015                 .pin = 2,
1016                 .func = 4,
1017                 .route_offset = 0x50,
1018                 .route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1019         }, {
1020                 /* i2s2_sdim0 */
1021                 .bank_num = 1,
1022                 .pin = 24,
1023                 .func = 1,
1024                 .route_offset = 0x50,
1025                 .route_val = BIT(16 + 6),
1026         }, {
1027                 /* i2s2_sdim1 */
1028                 .bank_num = 3,
1029                 .pin = 2,
1030                 .func = 6,
1031                 .route_offset = 0x50,
1032                 .route_val =  BIT(16 + 6) | BIT(6),
1033         }, {
1034                 /* card_iom1 */
1035                 .bank_num = 2,
1036                 .pin = 22,
1037                 .func = 3,
1038                 .route_offset = 0x50,
1039                 .route_val =  BIT(16 + 7) | BIT(7),
1040         }, {
1041                 /* tsp_d5m1 */
1042                 .bank_num = 2,
1043                 .pin = 16,
1044                 .func = 3,
1045                 .route_offset = 0x50,
1046                 .route_val =  BIT(16 + 8) | BIT(8),
1047         }, {
1048                 /* cif_data5m1 */
1049                 .bank_num = 2,
1050                 .pin = 16,
1051                 .func = 4,
1052                 .route_offset = 0x50,
1053                 .route_val =  BIT(16 + 9) | BIT(9),
1054         },
1055 };
1056
1057 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1058         {
1059                 /* uart2dbga_rx */
1060                 .bank_num = 4,
1061                 .pin = 8,
1062                 .func = 2,
1063                 .route_offset = 0xe21c,
1064                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1065         }, {
1066                 /* uart2dbgb_rx */
1067                 .bank_num = 4,
1068                 .pin = 16,
1069                 .func = 2,
1070                 .route_offset = 0xe21c,
1071                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1072         }, {
1073                 /* uart2dbgc_rx */
1074                 .bank_num = 4,
1075                 .pin = 19,
1076                 .func = 1,
1077                 .route_offset = 0xe21c,
1078                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1079         }, {
1080                 /* pcie_clkreqn */
1081                 .bank_num = 2,
1082                 .pin = 26,
1083                 .func = 2,
1084                 .route_offset = 0xe21c,
1085                 .route_val = BIT(16 + 14),
1086         }, {
1087                 /* pcie_clkreqnb */
1088                 .bank_num = 4,
1089                 .pin = 24,
1090                 .func = 1,
1091                 .route_offset = 0xe21c,
1092                 .route_val = BIT(16 + 14) | BIT(14),
1093         },
1094 };
1095
1096 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1097                                    int mux, u32 *reg, u32 *value)
1098 {
1099         struct rockchip_pinctrl *info = bank->drvdata;
1100         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1101         struct rockchip_mux_route_data *data;
1102         int i;
1103
1104         for (i = 0; i < ctrl->niomux_routes; i++) {
1105                 data = &ctrl->iomux_routes[i];
1106                 if ((data->bank_num == bank->bank_num) &&
1107                     (data->pin == pin) && (data->func == mux))
1108                         break;
1109         }
1110
1111         if (i >= ctrl->niomux_routes)
1112                 return false;
1113
1114         *reg = data->route_offset;
1115         *value = data->route_val;
1116
1117         return true;
1118 }
1119
1120 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1121 {
1122         struct rockchip_pinctrl *info = bank->drvdata;
1123         int iomux_num = (pin / 8);
1124         struct regmap *regmap;
1125         unsigned int val;
1126         int reg, ret, mask, mux_type;
1127         u8 bit;
1128
1129         if (iomux_num > 3)
1130                 return -EINVAL;
1131
1132         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1133                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1134                 return -EINVAL;
1135         }
1136
1137         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1138                 return RK_FUNC_GPIO;
1139
1140         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1141                                 ? info->regmap_pmu : info->regmap_base;
1142
1143         /* get basic quadrupel of mux registers and the correct reg inside */
1144         mux_type = bank->iomux[iomux_num].type;
1145         reg = bank->iomux[iomux_num].offset;
1146         if (mux_type & IOMUX_WIDTH_4BIT) {
1147                 if ((pin % 8) >= 4)
1148                         reg += 0x4;
1149                 bit = (pin % 4) * 4;
1150                 mask = 0xf;
1151         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1152                 if ((pin % 8) >= 5)
1153                         reg += 0x4;
1154                 bit = (pin % 8 % 5) * 3;
1155                 mask = 0x7;
1156         } else {
1157                 bit = (pin % 8) * 2;
1158                 mask = 0x3;
1159         }
1160
1161         if (bank->recalced_mask & BIT(pin))
1162                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1163
1164         ret = regmap_read(regmap, reg, &val);
1165         if (ret)
1166                 return ret;
1167
1168         return ((val >> bit) & mask);
1169 }
1170
1171 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1172                                int pin, int mux)
1173 {
1174         struct rockchip_pinctrl *info = bank->drvdata;
1175         int iomux_num = (pin / 8);
1176
1177         if (iomux_num > 3)
1178                 return -EINVAL;
1179
1180         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1181                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1182                 return -EINVAL;
1183         }
1184
1185         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1186                 if (mux != RK_FUNC_GPIO) {
1187                         dev_err(info->dev,
1188                                 "pin %d only supports a gpio mux\n", pin);
1189                         return -ENOTSUPP;
1190                 }
1191         }
1192
1193         return 0;
1194 }
1195
1196 /*
1197  * Set a new mux function for a pin.
1198  *
1199  * The register is divided into the upper and lower 16 bit. When changing
1200  * a value, the previous register value is not read and changed. Instead
1201  * it seems the changed bits are marked in the upper 16 bit, while the
1202  * changed value gets set in the same offset in the lower 16 bit.
1203  * All pin settings seem to be 2 bit wide in both the upper and lower
1204  * parts.
1205  * @bank: pin bank to change
1206  * @pin: pin to change
1207  * @mux: new mux function to set
1208  */
1209 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1210 {
1211         struct rockchip_pinctrl *info = bank->drvdata;
1212         int iomux_num = (pin / 8);
1213         struct regmap *regmap;
1214         int reg, ret, mask, mux_type;
1215         u8 bit;
1216         u32 data, rmask, route_reg, route_val;
1217
1218         ret = rockchip_verify_mux(bank, pin, mux);
1219         if (ret < 0)
1220                 return ret;
1221
1222         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1223                 return 0;
1224
1225         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1226                                                 bank->bank_num, pin, mux);
1227
1228         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1229                                 ? info->regmap_pmu : info->regmap_base;
1230
1231         /* get basic quadrupel of mux registers and the correct reg inside */
1232         mux_type = bank->iomux[iomux_num].type;
1233         reg = bank->iomux[iomux_num].offset;
1234         if (mux_type & IOMUX_WIDTH_4BIT) {
1235                 if ((pin % 8) >= 4)
1236                         reg += 0x4;
1237                 bit = (pin % 4) * 4;
1238                 mask = 0xf;
1239         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1240                 if ((pin % 8) >= 5)
1241                         reg += 0x4;
1242                 bit = (pin % 8 % 5) * 3;
1243                 mask = 0x7;
1244         } else {
1245                 bit = (pin % 8) * 2;
1246                 mask = 0x3;
1247         }
1248
1249         if (bank->recalced_mask & BIT(pin))
1250                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1251
1252         if (bank->route_mask & BIT(pin)) {
1253                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1254                                            &route_val)) {
1255                         ret = regmap_write(regmap, route_reg, route_val);
1256                         if (ret)
1257                                 return ret;
1258                 }
1259         }
1260
1261         data = (mask << (bit + 16));
1262         rmask = data | (data >> 16);
1263         data |= (mux & mask) << bit;
1264         ret = regmap_update_bits(regmap, reg, rmask, data);
1265
1266         return ret;
1267 }
1268
1269 #define PX30_PULL_PMU_OFFSET            0x10
1270 #define PX30_PULL_GRF_OFFSET            0x60
1271 #define PX30_PULL_BITS_PER_PIN          2
1272 #define PX30_PULL_PINS_PER_REG          8
1273 #define PX30_PULL_BANK_STRIDE           16
1274
1275 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1276                                        int pin_num, struct regmap **regmap,
1277                                        int *reg, u8 *bit)
1278 {
1279         struct rockchip_pinctrl *info = bank->drvdata;
1280
1281         /* The first 32 pins of the first bank are located in PMU */
1282         if (bank->bank_num == 0) {
1283                 *regmap = info->regmap_pmu;
1284                 *reg = PX30_PULL_PMU_OFFSET;
1285         } else {
1286                 *regmap = info->regmap_base;
1287                 *reg = PX30_PULL_GRF_OFFSET;
1288
1289                 /* correct the offset, as we're starting with the 2nd bank */
1290                 *reg -= 0x10;
1291                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1292         }
1293
1294         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1295         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1296         *bit *= PX30_PULL_BITS_PER_PIN;
1297 }
1298
1299 #define PX30_DRV_PMU_OFFSET             0x20
1300 #define PX30_DRV_GRF_OFFSET             0xf0
1301 #define PX30_DRV_BITS_PER_PIN           2
1302 #define PX30_DRV_PINS_PER_REG           8
1303 #define PX30_DRV_BANK_STRIDE            16
1304
1305 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1306                                       int pin_num, struct regmap **regmap,
1307                                       int *reg, u8 *bit)
1308 {
1309         struct rockchip_pinctrl *info = bank->drvdata;
1310
1311         /* The first 32 pins of the first bank are located in PMU */
1312         if (bank->bank_num == 0) {
1313                 *regmap = info->regmap_pmu;
1314                 *reg = PX30_DRV_PMU_OFFSET;
1315         } else {
1316                 *regmap = info->regmap_base;
1317                 *reg = PX30_DRV_GRF_OFFSET;
1318
1319                 /* correct the offset, as we're starting with the 2nd bank */
1320                 *reg -= 0x10;
1321                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1322         }
1323
1324         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1325         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1326         *bit *= PX30_DRV_BITS_PER_PIN;
1327 }
1328
1329 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1330 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1331 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1332 #define PX30_SCHMITT_BANK_STRIDE                16
1333 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1334
1335 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1336                                          int pin_num,
1337                                          struct regmap **regmap,
1338                                          int *reg, u8 *bit)
1339 {
1340         struct rockchip_pinctrl *info = bank->drvdata;
1341         int pins_per_reg;
1342
1343         if (bank->bank_num == 0) {
1344                 *regmap = info->regmap_pmu;
1345                 *reg = PX30_SCHMITT_PMU_OFFSET;
1346                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1347         } else {
1348                 *regmap = info->regmap_base;
1349                 *reg = PX30_SCHMITT_GRF_OFFSET;
1350                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1351                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1352         }
1353
1354         *reg += ((pin_num / pins_per_reg) * 4);
1355         *bit = pin_num % pins_per_reg;
1356
1357         return 0;
1358 }
1359
1360 #define RV1108_PULL_PMU_OFFSET          0x10
1361 #define RV1108_PULL_OFFSET              0x110
1362 #define RV1108_PULL_PINS_PER_REG        8
1363 #define RV1108_PULL_BITS_PER_PIN        2
1364 #define RV1108_PULL_BANK_STRIDE         16
1365
1366 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1367                                          int pin_num, struct regmap **regmap,
1368                                          int *reg, u8 *bit)
1369 {
1370         struct rockchip_pinctrl *info = bank->drvdata;
1371
1372         /* The first 24 pins of the first bank are located in PMU */
1373         if (bank->bank_num == 0) {
1374                 *regmap = info->regmap_pmu;
1375                 *reg = RV1108_PULL_PMU_OFFSET;
1376         } else {
1377                 *reg = RV1108_PULL_OFFSET;
1378                 *regmap = info->regmap_base;
1379                 /* correct the offset, as we're starting with the 2nd bank */
1380                 *reg -= 0x10;
1381                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1382         }
1383
1384         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1385         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1386         *bit *= RV1108_PULL_BITS_PER_PIN;
1387 }
1388
1389 #define RV1108_DRV_PMU_OFFSET           0x20
1390 #define RV1108_DRV_GRF_OFFSET           0x210
1391 #define RV1108_DRV_BITS_PER_PIN         2
1392 #define RV1108_DRV_PINS_PER_REG         8
1393 #define RV1108_DRV_BANK_STRIDE          16
1394
1395 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1396                                         int pin_num, struct regmap **regmap,
1397                                         int *reg, u8 *bit)
1398 {
1399         struct rockchip_pinctrl *info = bank->drvdata;
1400
1401         /* The first 24 pins of the first bank are located in PMU */
1402         if (bank->bank_num == 0) {
1403                 *regmap = info->regmap_pmu;
1404                 *reg = RV1108_DRV_PMU_OFFSET;
1405         } else {
1406                 *regmap = info->regmap_base;
1407                 *reg = RV1108_DRV_GRF_OFFSET;
1408
1409                 /* correct the offset, as we're starting with the 2nd bank */
1410                 *reg -= 0x10;
1411                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1412         }
1413
1414         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1415         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1416         *bit *= RV1108_DRV_BITS_PER_PIN;
1417 }
1418
1419 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1420 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1421 #define RV1108_SCHMITT_BANK_STRIDE              8
1422 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1423 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1424
1425 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1426                                            int pin_num,
1427                                            struct regmap **regmap,
1428                                            int *reg, u8 *bit)
1429 {
1430         struct rockchip_pinctrl *info = bank->drvdata;
1431         int pins_per_reg;
1432
1433         if (bank->bank_num == 0) {
1434                 *regmap = info->regmap_pmu;
1435                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1436                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1437         } else {
1438                 *regmap = info->regmap_base;
1439                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1440                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1441                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1442         }
1443         *reg += ((pin_num / pins_per_reg) * 4);
1444         *bit = pin_num % pins_per_reg;
1445
1446         return 0;
1447 }
1448
1449 #define RK2928_PULL_OFFSET              0x118
1450 #define RK2928_PULL_PINS_PER_REG        16
1451 #define RK2928_PULL_BANK_STRIDE         8
1452
1453 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1454                                     int pin_num, struct regmap **regmap,
1455                                     int *reg, u8 *bit)
1456 {
1457         struct rockchip_pinctrl *info = bank->drvdata;
1458
1459         *regmap = info->regmap_base;
1460         *reg = RK2928_PULL_OFFSET;
1461         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1462         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1463
1464         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1465 };
1466
1467 #define RK3128_PULL_OFFSET      0x118
1468
1469 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1470                                          int pin_num, struct regmap **regmap,
1471                                          int *reg, u8 *bit)
1472 {
1473         struct rockchip_pinctrl *info = bank->drvdata;
1474
1475         *regmap = info->regmap_base;
1476         *reg = RK3128_PULL_OFFSET;
1477         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1478         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1479
1480         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1481 }
1482
1483 #define RK3188_PULL_OFFSET              0x164
1484 #define RK3188_PULL_BITS_PER_PIN        2
1485 #define RK3188_PULL_PINS_PER_REG        8
1486 #define RK3188_PULL_BANK_STRIDE         16
1487 #define RK3188_PULL_PMU_OFFSET          0x64
1488
1489 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1490                                     int pin_num, struct regmap **regmap,
1491                                     int *reg, u8 *bit)
1492 {
1493         struct rockchip_pinctrl *info = bank->drvdata;
1494
1495         /* The first 12 pins of the first bank are located elsewhere */
1496         if (bank->bank_num == 0 && pin_num < 12) {
1497                 *regmap = info->regmap_pmu ? info->regmap_pmu
1498                                            : bank->regmap_pull;
1499                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1500                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1501                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1502                 *bit *= RK3188_PULL_BITS_PER_PIN;
1503         } else {
1504                 *regmap = info->regmap_pull ? info->regmap_pull
1505                                             : info->regmap_base;
1506                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1507
1508                 /* correct the offset, as it is the 2nd pull register */
1509                 *reg -= 4;
1510                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1511                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1512
1513                 /*
1514                  * The bits in these registers have an inverse ordering
1515                  * with the lowest pin being in bits 15:14 and the highest
1516                  * pin in bits 1:0
1517                  */
1518                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1519                 *bit *= RK3188_PULL_BITS_PER_PIN;
1520         }
1521 }
1522
1523 #define RK3288_PULL_OFFSET              0x140
1524 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1525                                     int pin_num, struct regmap **regmap,
1526                                     int *reg, u8 *bit)
1527 {
1528         struct rockchip_pinctrl *info = bank->drvdata;
1529
1530         /* The first 24 pins of the first bank are located in PMU */
1531         if (bank->bank_num == 0) {
1532                 *regmap = info->regmap_pmu;
1533                 *reg = RK3188_PULL_PMU_OFFSET;
1534
1535                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1536                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1537                 *bit *= RK3188_PULL_BITS_PER_PIN;
1538         } else {
1539                 *regmap = info->regmap_base;
1540                 *reg = RK3288_PULL_OFFSET;
1541
1542                 /* correct the offset, as we're starting with the 2nd bank */
1543                 *reg -= 0x10;
1544                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1545                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1546
1547                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1548                 *bit *= RK3188_PULL_BITS_PER_PIN;
1549         }
1550 }
1551
1552 #define RK3288_DRV_PMU_OFFSET           0x70
1553 #define RK3288_DRV_GRF_OFFSET           0x1c0
1554 #define RK3288_DRV_BITS_PER_PIN         2
1555 #define RK3288_DRV_PINS_PER_REG         8
1556 #define RK3288_DRV_BANK_STRIDE          16
1557
1558 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1559                                     int pin_num, struct regmap **regmap,
1560                                     int *reg, u8 *bit)
1561 {
1562         struct rockchip_pinctrl *info = bank->drvdata;
1563
1564         /* The first 24 pins of the first bank are located in PMU */
1565         if (bank->bank_num == 0) {
1566                 *regmap = info->regmap_pmu;
1567                 *reg = RK3288_DRV_PMU_OFFSET;
1568
1569                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1570                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1571                 *bit *= RK3288_DRV_BITS_PER_PIN;
1572         } else {
1573                 *regmap = info->regmap_base;
1574                 *reg = RK3288_DRV_GRF_OFFSET;
1575
1576                 /* correct the offset, as we're starting with the 2nd bank */
1577                 *reg -= 0x10;
1578                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1579                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1580
1581                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1582                 *bit *= RK3288_DRV_BITS_PER_PIN;
1583         }
1584 }
1585
1586 #define RK3228_PULL_OFFSET              0x100
1587
1588 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1589                                     int pin_num, struct regmap **regmap,
1590                                     int *reg, u8 *bit)
1591 {
1592         struct rockchip_pinctrl *info = bank->drvdata;
1593
1594         *regmap = info->regmap_base;
1595         *reg = RK3228_PULL_OFFSET;
1596         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1597         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1598
1599         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1600         *bit *= RK3188_PULL_BITS_PER_PIN;
1601 }
1602
1603 #define RK3228_DRV_GRF_OFFSET           0x200
1604
1605 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1606                                     int pin_num, struct regmap **regmap,
1607                                     int *reg, u8 *bit)
1608 {
1609         struct rockchip_pinctrl *info = bank->drvdata;
1610
1611         *regmap = info->regmap_base;
1612         *reg = RK3228_DRV_GRF_OFFSET;
1613         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1614         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1615
1616         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1617         *bit *= RK3288_DRV_BITS_PER_PIN;
1618 }
1619
1620 #define RK3368_PULL_GRF_OFFSET          0x100
1621 #define RK3368_PULL_PMU_OFFSET          0x10
1622
1623 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1624                                     int pin_num, struct regmap **regmap,
1625                                     int *reg, u8 *bit)
1626 {
1627         struct rockchip_pinctrl *info = bank->drvdata;
1628
1629         /* The first 32 pins of the first bank are located in PMU */
1630         if (bank->bank_num == 0) {
1631                 *regmap = info->regmap_pmu;
1632                 *reg = RK3368_PULL_PMU_OFFSET;
1633
1634                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1635                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1636                 *bit *= RK3188_PULL_BITS_PER_PIN;
1637         } else {
1638                 *regmap = info->regmap_base;
1639                 *reg = RK3368_PULL_GRF_OFFSET;
1640
1641                 /* correct the offset, as we're starting with the 2nd bank */
1642                 *reg -= 0x10;
1643                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1644                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1645
1646                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1647                 *bit *= RK3188_PULL_BITS_PER_PIN;
1648         }
1649 }
1650
1651 #define RK3368_DRV_PMU_OFFSET           0x20
1652 #define RK3368_DRV_GRF_OFFSET           0x200
1653
1654 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1655                                     int pin_num, struct regmap **regmap,
1656                                     int *reg, u8 *bit)
1657 {
1658         struct rockchip_pinctrl *info = bank->drvdata;
1659
1660         /* The first 32 pins of the first bank are located in PMU */
1661         if (bank->bank_num == 0) {
1662                 *regmap = info->regmap_pmu;
1663                 *reg = RK3368_DRV_PMU_OFFSET;
1664
1665                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1666                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1667                 *bit *= RK3288_DRV_BITS_PER_PIN;
1668         } else {
1669                 *regmap = info->regmap_base;
1670                 *reg = RK3368_DRV_GRF_OFFSET;
1671
1672                 /* correct the offset, as we're starting with the 2nd bank */
1673                 *reg -= 0x10;
1674                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1675                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1676
1677                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1678                 *bit *= RK3288_DRV_BITS_PER_PIN;
1679         }
1680 }
1681
1682 #define RK3399_PULL_GRF_OFFSET          0xe040
1683 #define RK3399_PULL_PMU_OFFSET          0x40
1684 #define RK3399_DRV_3BITS_PER_PIN        3
1685
1686 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1687                                          int pin_num, struct regmap **regmap,
1688                                          int *reg, u8 *bit)
1689 {
1690         struct rockchip_pinctrl *info = bank->drvdata;
1691
1692         /* The bank0:16 and bank1:32 pins are located in PMU */
1693         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1694                 *regmap = info->regmap_pmu;
1695                 *reg = RK3399_PULL_PMU_OFFSET;
1696
1697                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1698
1699                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1700                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1701                 *bit *= RK3188_PULL_BITS_PER_PIN;
1702         } else {
1703                 *regmap = info->regmap_base;
1704                 *reg = RK3399_PULL_GRF_OFFSET;
1705
1706                 /* correct the offset, as we're starting with the 3rd bank */
1707                 *reg -= 0x20;
1708                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1709                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1710
1711                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1712                 *bit *= RK3188_PULL_BITS_PER_PIN;
1713         }
1714 }
1715
1716 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1717                                         int pin_num, struct regmap **regmap,
1718                                         int *reg, u8 *bit)
1719 {
1720         struct rockchip_pinctrl *info = bank->drvdata;
1721         int drv_num = (pin_num / 8);
1722
1723         /*  The bank0:16 and bank1:32 pins are located in PMU */
1724         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1725                 *regmap = info->regmap_pmu;
1726         else
1727                 *regmap = info->regmap_base;
1728
1729         *reg = bank->drv[drv_num].offset;
1730         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1731             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1732                 *bit = (pin_num % 8) * 3;
1733         else
1734                 *bit = (pin_num % 8) * 2;
1735 }
1736
1737 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1738         { 2, 4, 8, 12, -1, -1, -1, -1 },
1739         { 3, 6, 9, 12, -1, -1, -1, -1 },
1740         { 5, 10, 15, 20, -1, -1, -1, -1 },
1741         { 4, 6, 8, 10, 12, 14, 16, 18 },
1742         { 4, 7, 10, 13, 16, 19, 22, 26 }
1743 };
1744
1745 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1746                                      int pin_num)
1747 {
1748         struct rockchip_pinctrl *info = bank->drvdata;
1749         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1750         struct regmap *regmap;
1751         int reg, ret;
1752         u32 data, temp, rmask_bits;
1753         u8 bit;
1754         int drv_type = bank->drv[pin_num / 8].drv_type;
1755
1756         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1757
1758         switch (drv_type) {
1759         case DRV_TYPE_IO_1V8_3V0_AUTO:
1760         case DRV_TYPE_IO_3V3_ONLY:
1761                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1762                 switch (bit) {
1763                 case 0 ... 12:
1764                         /* regular case, nothing to do */
1765                         break;
1766                 case 15:
1767                         /*
1768                          * drive-strength offset is special, as it is
1769                          * spread over 2 registers
1770                          */
1771                         ret = regmap_read(regmap, reg, &data);
1772                         if (ret)
1773                                 return ret;
1774
1775                         ret = regmap_read(regmap, reg + 0x4, &temp);
1776                         if (ret)
1777                                 return ret;
1778
1779                         /*
1780                          * the bit data[15] contains bit 0 of the value
1781                          * while temp[1:0] contains bits 2 and 1
1782                          */
1783                         data >>= 15;
1784                         temp &= 0x3;
1785                         temp <<= 1;
1786                         data |= temp;
1787
1788                         return rockchip_perpin_drv_list[drv_type][data];
1789                 case 18 ... 21:
1790                         /* setting fully enclosed in the second register */
1791                         reg += 4;
1792                         bit -= 16;
1793                         break;
1794                 default:
1795                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1796                                 bit, drv_type);
1797                         return -EINVAL;
1798                 }
1799
1800                 break;
1801         case DRV_TYPE_IO_DEFAULT:
1802         case DRV_TYPE_IO_1V8_OR_3V0:
1803         case DRV_TYPE_IO_1V8_ONLY:
1804                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1805                 break;
1806         default:
1807                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1808                         drv_type);
1809                 return -EINVAL;
1810         }
1811
1812         ret = regmap_read(regmap, reg, &data);
1813         if (ret)
1814                 return ret;
1815
1816         data >>= bit;
1817         data &= (1 << rmask_bits) - 1;
1818
1819         return rockchip_perpin_drv_list[drv_type][data];
1820 }
1821
1822 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1823                                      int pin_num, int strength)
1824 {
1825         struct rockchip_pinctrl *info = bank->drvdata;
1826         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1827         struct regmap *regmap;
1828         int reg, ret, i;
1829         u32 data, rmask, rmask_bits, temp;
1830         u8 bit;
1831         int drv_type = bank->drv[pin_num / 8].drv_type;
1832
1833         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1834                 bank->bank_num, pin_num, strength);
1835
1836         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1837
1838         ret = -EINVAL;
1839         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1840                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1841                         ret = i;
1842                         break;
1843                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1844                         ret = rockchip_perpin_drv_list[drv_type][i];
1845                         break;
1846                 }
1847         }
1848
1849         if (ret < 0) {
1850                 dev_err(info->dev, "unsupported driver strength %d\n",
1851                         strength);
1852                 return ret;
1853         }
1854
1855         switch (drv_type) {
1856         case DRV_TYPE_IO_1V8_3V0_AUTO:
1857         case DRV_TYPE_IO_3V3_ONLY:
1858                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1859                 switch (bit) {
1860                 case 0 ... 12:
1861                         /* regular case, nothing to do */
1862                         break;
1863                 case 15:
1864                         /*
1865                          * drive-strength offset is special, as it is spread
1866                          * over 2 registers, the bit data[15] contains bit 0
1867                          * of the value while temp[1:0] contains bits 2 and 1
1868                          */
1869                         data = (ret & 0x1) << 15;
1870                         temp = (ret >> 0x1) & 0x3;
1871
1872                         rmask = BIT(15) | BIT(31);
1873                         data |= BIT(31);
1874                         ret = regmap_update_bits(regmap, reg, rmask, data);
1875                         if (ret)
1876                                 return ret;
1877
1878                         rmask = 0x3 | (0x3 << 16);
1879                         temp |= (0x3 << 16);
1880                         reg += 0x4;
1881                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1882
1883                         return ret;
1884                 case 18 ... 21:
1885                         /* setting fully enclosed in the second register */
1886                         reg += 4;
1887                         bit -= 16;
1888                         break;
1889                 default:
1890                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1891                                 bit, drv_type);
1892                         return -EINVAL;
1893                 }
1894                 break;
1895         case DRV_TYPE_IO_DEFAULT:
1896         case DRV_TYPE_IO_1V8_OR_3V0:
1897         case DRV_TYPE_IO_1V8_ONLY:
1898                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1899                 break;
1900         default:
1901                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1902                         drv_type);
1903                 return -EINVAL;
1904         }
1905
1906         /* enable the write to the equivalent lower bits */
1907         data = ((1 << rmask_bits) - 1) << (bit + 16);
1908         rmask = data | (data >> 16);
1909         data |= (ret << bit);
1910
1911         ret = regmap_update_bits(regmap, reg, rmask, data);
1912
1913         return ret;
1914 }
1915
1916 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1917         {
1918                 PIN_CONFIG_BIAS_DISABLE,
1919                 PIN_CONFIG_BIAS_PULL_UP,
1920                 PIN_CONFIG_BIAS_PULL_DOWN,
1921                 PIN_CONFIG_BIAS_BUS_HOLD
1922         },
1923         {
1924                 PIN_CONFIG_BIAS_DISABLE,
1925                 PIN_CONFIG_BIAS_PULL_DOWN,
1926                 PIN_CONFIG_BIAS_DISABLE,
1927                 PIN_CONFIG_BIAS_PULL_UP
1928         },
1929 };
1930
1931 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1932 {
1933         struct rockchip_pinctrl *info = bank->drvdata;
1934         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1935         struct regmap *regmap;
1936         int reg, ret, pull_type;
1937         u8 bit;
1938         u32 data;
1939
1940         /* rk3066b does support any pulls */
1941         if (ctrl->type == RK3066B)
1942                 return PIN_CONFIG_BIAS_DISABLE;
1943
1944         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1945
1946         ret = regmap_read(regmap, reg, &data);
1947         if (ret)
1948                 return ret;
1949
1950         switch (ctrl->type) {
1951         case RK2928:
1952         case RK3128:
1953                 return !(data & BIT(bit))
1954                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1955                                 : PIN_CONFIG_BIAS_DISABLE;
1956         case PX30:
1957         case RV1108:
1958         case RK3188:
1959         case RK3288:
1960         case RK3368:
1961         case RK3399:
1962                 pull_type = bank->pull_type[pin_num / 8];
1963                 data >>= bit;
1964                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1965
1966                 return rockchip_pull_list[pull_type][data];
1967         default:
1968                 dev_err(info->dev, "unsupported pinctrl type\n");
1969                 return -EINVAL;
1970         };
1971 }
1972
1973 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1974                                         int pin_num, int pull)
1975 {
1976         struct rockchip_pinctrl *info = bank->drvdata;
1977         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1978         struct regmap *regmap;
1979         int reg, ret, i, pull_type;
1980         u8 bit;
1981         u32 data, rmask;
1982
1983         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1984                  bank->bank_num, pin_num, pull);
1985
1986         /* rk3066b does support any pulls */
1987         if (ctrl->type == RK3066B)
1988                 return pull ? -EINVAL : 0;
1989
1990         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1991
1992         switch (ctrl->type) {
1993         case RK2928:
1994         case RK3128:
1995                 data = BIT(bit + 16);
1996                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1997                         data |= BIT(bit);
1998                 ret = regmap_write(regmap, reg, data);
1999                 break;
2000         case PX30:
2001         case RV1108:
2002         case RK3188:
2003         case RK3288:
2004         case RK3368:
2005         case RK3399:
2006                 pull_type = bank->pull_type[pin_num / 8];
2007                 ret = -EINVAL;
2008                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2009                         i++) {
2010                         if (rockchip_pull_list[pull_type][i] == pull) {
2011                                 ret = i;
2012                                 break;
2013                         }
2014                 }
2015
2016                 if (ret < 0) {
2017                         dev_err(info->dev, "unsupported pull setting %d\n",
2018                                 pull);
2019                         return ret;
2020                 }
2021
2022                 /* enable the write to the equivalent lower bits */
2023                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2024                 rmask = data | (data >> 16);
2025                 data |= (ret << bit);
2026
2027                 ret = regmap_update_bits(regmap, reg, rmask, data);
2028                 break;
2029         default:
2030                 dev_err(info->dev, "unsupported pinctrl type\n");
2031                 return -EINVAL;
2032         }
2033
2034         return ret;
2035 }
2036
2037 #define RK3328_SCHMITT_BITS_PER_PIN             1
2038 #define RK3328_SCHMITT_PINS_PER_REG             16
2039 #define RK3328_SCHMITT_BANK_STRIDE              8
2040 #define RK3328_SCHMITT_GRF_OFFSET               0x380
2041
2042 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2043                                            int pin_num,
2044                                            struct regmap **regmap,
2045                                            int *reg, u8 *bit)
2046 {
2047         struct rockchip_pinctrl *info = bank->drvdata;
2048
2049         *regmap = info->regmap_base;
2050         *reg = RK3328_SCHMITT_GRF_OFFSET;
2051
2052         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2053         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2054         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2055
2056         return 0;
2057 }
2058
2059 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2060 {
2061         struct rockchip_pinctrl *info = bank->drvdata;
2062         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2063         struct regmap *regmap;
2064         int reg, ret;
2065         u8 bit;
2066         u32 data;
2067
2068         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2069         if (ret)
2070                 return ret;
2071
2072         ret = regmap_read(regmap, reg, &data);
2073         if (ret)
2074                 return ret;
2075
2076         data >>= bit;
2077         return data & 0x1;
2078 }
2079
2080 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2081                                 int pin_num, int enable)
2082 {
2083         struct rockchip_pinctrl *info = bank->drvdata;
2084         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2085         struct regmap *regmap;
2086         int reg, ret;
2087         u8 bit;
2088         u32 data, rmask;
2089
2090         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2091                 bank->bank_num, pin_num, enable);
2092
2093         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2094         if (ret)
2095                 return ret;
2096
2097         /* enable the write to the equivalent lower bits */
2098         data = BIT(bit + 16) | (enable << bit);
2099         rmask = BIT(bit + 16) | BIT(bit);
2100
2101         return regmap_update_bits(regmap, reg, rmask, data);
2102 }
2103
2104 /*
2105  * Pinmux_ops handling
2106  */
2107
2108 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2109 {
2110         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2111
2112         return info->nfunctions;
2113 }
2114
2115 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2116                                           unsigned selector)
2117 {
2118         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2119
2120         return info->functions[selector].name;
2121 }
2122
2123 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2124                                 unsigned selector, const char * const **groups,
2125                                 unsigned * const num_groups)
2126 {
2127         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2128
2129         *groups = info->functions[selector].groups;
2130         *num_groups = info->functions[selector].ngroups;
2131
2132         return 0;
2133 }
2134
2135 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2136                             unsigned group)
2137 {
2138         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2139         const unsigned int *pins = info->groups[group].pins;
2140         const struct rockchip_pin_config *data = info->groups[group].data;
2141         struct rockchip_pin_bank *bank;
2142         int cnt, ret = 0;
2143
2144         dev_dbg(info->dev, "enable function %s group %s\n",
2145                 info->functions[selector].name, info->groups[group].name);
2146
2147         /*
2148          * for each pin in the pin group selected, program the corresponding
2149          * pin function number in the config register.
2150          */
2151         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2152                 bank = pin_to_bank(info, pins[cnt]);
2153                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2154                                        data[cnt].func);
2155                 if (ret)
2156                         break;
2157         }
2158
2159         if (ret) {
2160                 /* revert the already done pin settings */
2161                 for (cnt--; cnt >= 0; cnt--)
2162                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2163
2164                 return ret;
2165         }
2166
2167         return 0;
2168 }
2169
2170 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2171 {
2172         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2173         u32 data;
2174         int ret;
2175
2176         ret = clk_enable(bank->clk);
2177         if (ret < 0) {
2178                 dev_err(bank->drvdata->dev,
2179                         "failed to enable clock for bank %s\n", bank->name);
2180                 return ret;
2181         }
2182         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2183         clk_disable(bank->clk);
2184
2185         return !(data & BIT(offset));
2186 }
2187
2188 /*
2189  * The calls to gpio_direction_output() and gpio_direction_input()
2190  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2191  * function called from the gpiolib interface).
2192  */
2193 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2194                                             int pin, bool input)
2195 {
2196         struct rockchip_pin_bank *bank;
2197         int ret;
2198         unsigned long flags;
2199         u32 data;
2200
2201         bank = gpiochip_get_data(chip);
2202
2203         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2204         if (ret < 0)
2205                 return ret;
2206
2207         clk_enable(bank->clk);
2208         raw_spin_lock_irqsave(&bank->slock, flags);
2209
2210         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2211         /* set bit to 1 for output, 0 for input */
2212         if (!input)
2213                 data |= BIT(pin);
2214         else
2215                 data &= ~BIT(pin);
2216         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2217
2218         raw_spin_unlock_irqrestore(&bank->slock, flags);
2219         clk_disable(bank->clk);
2220
2221         return 0;
2222 }
2223
2224 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2225                                               struct pinctrl_gpio_range *range,
2226                                               unsigned offset, bool input)
2227 {
2228         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2229         struct gpio_chip *chip;
2230         int pin;
2231
2232         chip = range->gc;
2233         pin = offset - chip->base;
2234         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2235                  offset, range->name, pin, input ? "input" : "output");
2236
2237         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2238                                                 input);
2239 }
2240
2241 static const struct pinmux_ops rockchip_pmx_ops = {
2242         .get_functions_count    = rockchip_pmx_get_funcs_count,
2243         .get_function_name      = rockchip_pmx_get_func_name,
2244         .get_function_groups    = rockchip_pmx_get_groups,
2245         .set_mux                = rockchip_pmx_set,
2246         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2247 };
2248
2249 /*
2250  * Pinconf_ops handling
2251  */
2252
2253 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2254                                         enum pin_config_param pull)
2255 {
2256         switch (ctrl->type) {
2257         case RK2928:
2258         case RK3128:
2259                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2260                                         pull == PIN_CONFIG_BIAS_DISABLE);
2261         case RK3066B:
2262                 return pull ? false : true;
2263         case PX30:
2264         case RV1108:
2265         case RK3188:
2266         case RK3288:
2267         case RK3368:
2268         case RK3399:
2269                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2270         }
2271
2272         return false;
2273 }
2274
2275 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2276 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2277
2278 /* set the pin config settings for a specified pin */
2279 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2280                                 unsigned long *configs, unsigned num_configs)
2281 {
2282         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2283         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2284         enum pin_config_param param;
2285         u32 arg;
2286         int i;
2287         int rc;
2288
2289         for (i = 0; i < num_configs; i++) {
2290                 param = pinconf_to_config_param(configs[i]);
2291                 arg = pinconf_to_config_argument(configs[i]);
2292
2293                 switch (param) {
2294                 case PIN_CONFIG_BIAS_DISABLE:
2295                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2296                                 param);
2297                         if (rc)
2298                                 return rc;
2299                         break;
2300                 case PIN_CONFIG_BIAS_PULL_UP:
2301                 case PIN_CONFIG_BIAS_PULL_DOWN:
2302                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2303                 case PIN_CONFIG_BIAS_BUS_HOLD:
2304                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2305                                 return -ENOTSUPP;
2306
2307                         if (!arg)
2308                                 return -EINVAL;
2309
2310                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2311                                 param);
2312                         if (rc)
2313                                 return rc;
2314                         break;
2315                 case PIN_CONFIG_OUTPUT:
2316                         rockchip_gpio_set(&bank->gpio_chip,
2317                                           pin - bank->pin_base, arg);
2318                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2319                                           pin - bank->pin_base, false);
2320                         if (rc)
2321                                 return rc;
2322                         break;
2323                 case PIN_CONFIG_DRIVE_STRENGTH:
2324                         /* rk3288 is the first with per-pin drive-strength */
2325                         if (!info->ctrl->drv_calc_reg)
2326                                 return -ENOTSUPP;
2327
2328                         rc = rockchip_set_drive_perpin(bank,
2329                                                 pin - bank->pin_base, arg);
2330                         if (rc < 0)
2331                                 return rc;
2332                         break;
2333                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2334                         if (!info->ctrl->schmitt_calc_reg)
2335                                 return -ENOTSUPP;
2336
2337                         rc = rockchip_set_schmitt(bank,
2338                                                   pin - bank->pin_base, arg);
2339                         if (rc < 0)
2340                                 return rc;
2341                         break;
2342                 default:
2343                         return -ENOTSUPP;
2344                         break;
2345                 }
2346         } /* for each config */
2347
2348         return 0;
2349 }
2350
2351 /* get the pin config settings for a specified pin */
2352 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2353                                                         unsigned long *config)
2354 {
2355         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2356         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2357         enum pin_config_param param = pinconf_to_config_param(*config);
2358         u16 arg;
2359         int rc;
2360
2361         switch (param) {
2362         case PIN_CONFIG_BIAS_DISABLE:
2363                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2364                         return -EINVAL;
2365
2366                 arg = 0;
2367                 break;
2368         case PIN_CONFIG_BIAS_PULL_UP:
2369         case PIN_CONFIG_BIAS_PULL_DOWN:
2370         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2371         case PIN_CONFIG_BIAS_BUS_HOLD:
2372                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2373                         return -ENOTSUPP;
2374
2375                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2376                         return -EINVAL;
2377
2378                 arg = 1;
2379                 break;
2380         case PIN_CONFIG_OUTPUT:
2381                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2382                 if (rc != RK_FUNC_GPIO)
2383                         return -EINVAL;
2384
2385                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2386                 if (rc < 0)
2387                         return rc;
2388
2389                 arg = rc ? 1 : 0;
2390                 break;
2391         case PIN_CONFIG_DRIVE_STRENGTH:
2392                 /* rk3288 is the first with per-pin drive-strength */
2393                 if (!info->ctrl->drv_calc_reg)
2394                         return -ENOTSUPP;
2395
2396                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2397                 if (rc < 0)
2398                         return rc;
2399
2400                 arg = rc;
2401                 break;
2402         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2403                 if (!info->ctrl->schmitt_calc_reg)
2404                         return -ENOTSUPP;
2405
2406                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2407                 if (rc < 0)
2408                         return rc;
2409
2410                 arg = rc;
2411                 break;
2412         default:
2413                 return -ENOTSUPP;
2414                 break;
2415         }
2416
2417         *config = pinconf_to_config_packed(param, arg);
2418
2419         return 0;
2420 }
2421
2422 static const struct pinconf_ops rockchip_pinconf_ops = {
2423         .pin_config_get                 = rockchip_pinconf_get,
2424         .pin_config_set                 = rockchip_pinconf_set,
2425         .is_generic                     = true,
2426 };
2427
2428 static const struct of_device_id rockchip_bank_match[] = {
2429         { .compatible = "rockchip,gpio-bank" },
2430         { .compatible = "rockchip,rk3188-gpio-bank0" },
2431         {},
2432 };
2433
2434 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2435                                                 struct device_node *np)
2436 {
2437         struct device_node *child;
2438
2439         for_each_child_of_node(np, child) {
2440                 if (of_match_node(rockchip_bank_match, child))
2441                         continue;
2442
2443                 info->nfunctions++;
2444                 info->ngroups += of_get_child_count(child);
2445         }
2446 }
2447
2448 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2449                                               struct rockchip_pin_group *grp,
2450                                               struct rockchip_pinctrl *info,
2451                                               u32 index)
2452 {
2453         struct rockchip_pin_bank *bank;
2454         int size;
2455         const __be32 *list;
2456         int num;
2457         int i, j;
2458         int ret;
2459
2460         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2461
2462         /* Initialise group */
2463         grp->name = np->name;
2464
2465         /*
2466          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2467          * do sanity check and calculate pins number
2468          */
2469         list = of_get_property(np, "rockchip,pins", &size);
2470         /* we do not check return since it's safe node passed down */
2471         size /= sizeof(*list);
2472         if (!size || size % 4) {
2473                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2474                 return -EINVAL;
2475         }
2476
2477         grp->npins = size / 4;
2478
2479         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2480                                                 GFP_KERNEL);
2481         grp->data = devm_kcalloc(info->dev,
2482                                         grp->npins,
2483                                         sizeof(struct rockchip_pin_config),
2484                                         GFP_KERNEL);
2485         if (!grp->pins || !grp->data)
2486                 return -ENOMEM;
2487
2488         for (i = 0, j = 0; i < size; i += 4, j++) {
2489                 const __be32 *phandle;
2490                 struct device_node *np_config;
2491
2492                 num = be32_to_cpu(*list++);
2493                 bank = bank_num_to_bank(info, num);
2494                 if (IS_ERR(bank))
2495                         return PTR_ERR(bank);
2496
2497                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2498                 grp->data[j].func = be32_to_cpu(*list++);
2499
2500                 phandle = list++;
2501                 if (!phandle)
2502                         return -EINVAL;
2503
2504                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2505                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2506                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2507                 of_node_put(np_config);
2508                 if (ret)
2509                         return ret;
2510         }
2511
2512         return 0;
2513 }
2514
2515 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2516                                                 struct rockchip_pinctrl *info,
2517                                                 u32 index)
2518 {
2519         struct device_node *child;
2520         struct rockchip_pmx_func *func;
2521         struct rockchip_pin_group *grp;
2522         int ret;
2523         static u32 grp_index;
2524         u32 i = 0;
2525
2526         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2527
2528         func = &info->functions[index];
2529
2530         /* Initialise function */
2531         func->name = np->name;
2532         func->ngroups = of_get_child_count(np);
2533         if (func->ngroups <= 0)
2534                 return 0;
2535
2536         func->groups = devm_kcalloc(info->dev,
2537                         func->ngroups, sizeof(char *), GFP_KERNEL);
2538         if (!func->groups)
2539                 return -ENOMEM;
2540
2541         for_each_child_of_node(np, child) {
2542                 func->groups[i] = child->name;
2543                 grp = &info->groups[grp_index++];
2544                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2545                 if (ret) {
2546                         of_node_put(child);
2547                         return ret;
2548                 }
2549         }
2550
2551         return 0;
2552 }
2553
2554 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2555                                               struct rockchip_pinctrl *info)
2556 {
2557         struct device *dev = &pdev->dev;
2558         struct device_node *np = dev->of_node;
2559         struct device_node *child;
2560         int ret;
2561         int i;
2562
2563         rockchip_pinctrl_child_count(info, np);
2564
2565         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2566         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2567
2568         info->functions = devm_kcalloc(dev,
2569                                               info->nfunctions,
2570                                               sizeof(struct rockchip_pmx_func),
2571                                               GFP_KERNEL);
2572         if (!info->functions)
2573                 return -EINVAL;
2574
2575         info->groups = devm_kcalloc(dev,
2576                                             info->ngroups,
2577                                             sizeof(struct rockchip_pin_group),
2578                                             GFP_KERNEL);
2579         if (!info->groups)
2580                 return -EINVAL;
2581
2582         i = 0;
2583
2584         for_each_child_of_node(np, child) {
2585                 if (of_match_node(rockchip_bank_match, child))
2586                         continue;
2587
2588                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2589                 if (ret) {
2590                         dev_err(&pdev->dev, "failed to parse function\n");
2591                         of_node_put(child);
2592                         return ret;
2593                 }
2594         }
2595
2596         return 0;
2597 }
2598
2599 static int rockchip_pinctrl_register(struct platform_device *pdev,
2600                                         struct rockchip_pinctrl *info)
2601 {
2602         struct pinctrl_desc *ctrldesc = &info->pctl;
2603         struct pinctrl_pin_desc *pindesc, *pdesc;
2604         struct rockchip_pin_bank *pin_bank;
2605         int pin, bank, ret;
2606         int k;
2607
2608         ctrldesc->name = "rockchip-pinctrl";
2609         ctrldesc->owner = THIS_MODULE;
2610         ctrldesc->pctlops = &rockchip_pctrl_ops;
2611         ctrldesc->pmxops = &rockchip_pmx_ops;
2612         ctrldesc->confops = &rockchip_pinconf_ops;
2613
2614         pindesc = devm_kcalloc(&pdev->dev,
2615                                info->ctrl->nr_pins, sizeof(*pindesc),
2616                                GFP_KERNEL);
2617         if (!pindesc)
2618                 return -ENOMEM;
2619
2620         ctrldesc->pins = pindesc;
2621         ctrldesc->npins = info->ctrl->nr_pins;
2622
2623         pdesc = pindesc;
2624         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2625                 pin_bank = &info->ctrl->pin_banks[bank];
2626                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2627                         pdesc->number = k;
2628                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2629                                                 pin_bank->name, pin);
2630                         pdesc++;
2631                 }
2632         }
2633
2634         ret = rockchip_pinctrl_parse_dt(pdev, info);
2635         if (ret)
2636                 return ret;
2637
2638         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2639         if (IS_ERR(info->pctl_dev)) {
2640                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2641                 return PTR_ERR(info->pctl_dev);
2642         }
2643
2644         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2645                 pin_bank = &info->ctrl->pin_banks[bank];
2646                 pin_bank->grange.name = pin_bank->name;
2647                 pin_bank->grange.id = bank;
2648                 pin_bank->grange.pin_base = pin_bank->pin_base;
2649                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2650                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2651                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2652                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2653         }
2654
2655         return 0;
2656 }
2657
2658 /*
2659  * GPIO handling
2660  */
2661
2662 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2663 {
2664         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2665         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2666         unsigned long flags;
2667         u32 data;
2668
2669         clk_enable(bank->clk);
2670         raw_spin_lock_irqsave(&bank->slock, flags);
2671
2672         data = readl(reg);
2673         data &= ~BIT(offset);
2674         if (value)
2675                 data |= BIT(offset);
2676         writel(data, reg);
2677
2678         raw_spin_unlock_irqrestore(&bank->slock, flags);
2679         clk_disable(bank->clk);
2680 }
2681
2682 /*
2683  * Returns the level of the pin for input direction and setting of the DR
2684  * register for output gpios.
2685  */
2686 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2687 {
2688         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2689         u32 data;
2690
2691         clk_enable(bank->clk);
2692         data = readl(bank->reg_base + GPIO_EXT_PORT);
2693         clk_disable(bank->clk);
2694         data >>= offset;
2695         data &= 1;
2696         return data;
2697 }
2698
2699 /*
2700  * gpiolib gpio_direction_input callback function. The setting of the pin
2701  * mux function as 'gpio input' will be handled by the pinctrl subsystem
2702  * interface.
2703  */
2704 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2705 {
2706         return pinctrl_gpio_direction_input(gc->base + offset);
2707 }
2708
2709 /*
2710  * gpiolib gpio_direction_output callback function. The setting of the pin
2711  * mux function as 'gpio output' will be handled by the pinctrl subsystem
2712  * interface.
2713  */
2714 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2715                                           unsigned offset, int value)
2716 {
2717         rockchip_gpio_set(gc, offset, value);
2718         return pinctrl_gpio_direction_output(gc->base + offset);
2719 }
2720
2721 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2722                                        unsigned int offset, bool enable)
2723 {
2724         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2725         void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2726         unsigned long flags;
2727         u32 data;
2728
2729         clk_enable(bank->clk);
2730         raw_spin_lock_irqsave(&bank->slock, flags);
2731
2732         data = readl(reg);
2733         if (enable)
2734                 data |= BIT(offset);
2735         else
2736                 data &= ~BIT(offset);
2737         writel(data, reg);
2738
2739         raw_spin_unlock_irqrestore(&bank->slock, flags);
2740         clk_disable(bank->clk);
2741 }
2742
2743 /*
2744  * gpiolib set_config callback function. The setting of the pin
2745  * mux function as 'gpio output' will be handled by the pinctrl subsystem
2746  * interface.
2747  */
2748 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2749                                   unsigned long config)
2750 {
2751         enum pin_config_param param = pinconf_to_config_param(config);
2752
2753         switch (param) {
2754         case PIN_CONFIG_INPUT_DEBOUNCE:
2755                 rockchip_gpio_set_debounce(gc, offset, true);
2756                 /*
2757                  * Rockchip's gpio could only support up to one period
2758                  * of the debounce clock(pclk), which is far away from
2759                  * satisftying the requirement, as pclk is usually near
2760                  * 100MHz shared by all peripherals. So the fact is it
2761                  * has crippled debounce capability could only be useful
2762                  * to prevent any spurious glitches from waking up the system
2763                  * if the gpio is conguired as wakeup interrupt source. Let's
2764                  * still return -ENOTSUPP as before, to make sure the caller
2765                  * of gpiod_set_debounce won't change its behaviour.
2766                  */
2767         default:
2768                 return -ENOTSUPP;
2769         }
2770 }
2771
2772 /*
2773  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2774  * and a virtual IRQ, if not already present.
2775  */
2776 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2777 {
2778         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2779         unsigned int virq;
2780
2781         if (!bank->domain)
2782                 return -ENXIO;
2783
2784         clk_enable(bank->clk);
2785         virq = irq_create_mapping(bank->domain, offset);
2786         clk_disable(bank->clk);
2787
2788         return (virq) ? : -ENXIO;
2789 }
2790
2791 static const struct gpio_chip rockchip_gpiolib_chip = {
2792         .request = gpiochip_generic_request,
2793         .free = gpiochip_generic_free,
2794         .set = rockchip_gpio_set,
2795         .get = rockchip_gpio_get,
2796         .get_direction  = rockchip_gpio_get_direction,
2797         .direction_input = rockchip_gpio_direction_input,
2798         .direction_output = rockchip_gpio_direction_output,
2799         .set_config = rockchip_gpio_set_config,
2800         .to_irq = rockchip_gpio_to_irq,
2801         .owner = THIS_MODULE,
2802 };
2803
2804 /*
2805  * Interrupt handling
2806  */
2807
2808 static void rockchip_irq_demux(struct irq_desc *desc)
2809 {
2810         struct irq_chip *chip = irq_desc_get_chip(desc);
2811         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2812         u32 pend;
2813
2814         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2815
2816         chained_irq_enter(chip, desc);
2817
2818         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2819
2820         while (pend) {
2821                 unsigned int irq, virq;
2822
2823                 irq = __ffs(pend);
2824                 pend &= ~BIT(irq);
2825                 virq = irq_linear_revmap(bank->domain, irq);
2826
2827                 if (!virq) {
2828                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2829                         continue;
2830                 }
2831
2832                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2833
2834                 /*
2835                  * Triggering IRQ on both rising and falling edge
2836                  * needs manual intervention.
2837                  */
2838                 if (bank->toggle_edge_mode & BIT(irq)) {
2839                         u32 data, data_old, polarity;
2840                         unsigned long flags;
2841
2842                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2843                         do {
2844                                 raw_spin_lock_irqsave(&bank->slock, flags);
2845
2846                                 polarity = readl_relaxed(bank->reg_base +
2847                                                          GPIO_INT_POLARITY);
2848                                 if (data & BIT(irq))
2849                                         polarity &= ~BIT(irq);
2850                                 else
2851                                         polarity |= BIT(irq);
2852                                 writel(polarity,
2853                                        bank->reg_base + GPIO_INT_POLARITY);
2854
2855                                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2856
2857                                 data_old = data;
2858                                 data = readl_relaxed(bank->reg_base +
2859                                                      GPIO_EXT_PORT);
2860                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2861                 }
2862
2863                 generic_handle_irq(virq);
2864         }
2865
2866         chained_irq_exit(chip, desc);
2867 }
2868
2869 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2870 {
2871         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2872         struct rockchip_pin_bank *bank = gc->private;
2873         u32 mask = BIT(d->hwirq);
2874         u32 polarity;
2875         u32 level;
2876         u32 data;
2877         unsigned long flags;
2878         int ret;
2879
2880         /* make sure the pin is configured as gpio input */
2881         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2882         if (ret < 0)
2883                 return ret;
2884
2885         clk_enable(bank->clk);
2886         raw_spin_lock_irqsave(&bank->slock, flags);
2887
2888         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2889         data &= ~mask;
2890         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2891
2892         raw_spin_unlock_irqrestore(&bank->slock, flags);
2893
2894         if (type & IRQ_TYPE_EDGE_BOTH)
2895                 irq_set_handler_locked(d, handle_edge_irq);
2896         else
2897                 irq_set_handler_locked(d, handle_level_irq);
2898
2899         raw_spin_lock_irqsave(&bank->slock, flags);
2900         irq_gc_lock(gc);
2901
2902         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2903         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2904
2905         switch (type) {
2906         case IRQ_TYPE_EDGE_BOTH:
2907                 bank->toggle_edge_mode |= mask;
2908                 level |= mask;
2909
2910                 /*
2911                  * Determine gpio state. If 1 next interrupt should be falling
2912                  * otherwise rising.
2913                  */
2914                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2915                 if (data & mask)
2916                         polarity &= ~mask;
2917                 else
2918                         polarity |= mask;
2919                 break;
2920         case IRQ_TYPE_EDGE_RISING:
2921                 bank->toggle_edge_mode &= ~mask;
2922                 level |= mask;
2923                 polarity |= mask;
2924                 break;
2925         case IRQ_TYPE_EDGE_FALLING:
2926                 bank->toggle_edge_mode &= ~mask;
2927                 level |= mask;
2928                 polarity &= ~mask;
2929                 break;
2930         case IRQ_TYPE_LEVEL_HIGH:
2931                 bank->toggle_edge_mode &= ~mask;
2932                 level &= ~mask;
2933                 polarity |= mask;
2934                 break;
2935         case IRQ_TYPE_LEVEL_LOW:
2936                 bank->toggle_edge_mode &= ~mask;
2937                 level &= ~mask;
2938                 polarity &= ~mask;
2939                 break;
2940         default:
2941                 irq_gc_unlock(gc);
2942                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2943                 clk_disable(bank->clk);
2944                 return -EINVAL;
2945         }
2946
2947         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2948         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2949
2950         irq_gc_unlock(gc);
2951         raw_spin_unlock_irqrestore(&bank->slock, flags);
2952         clk_disable(bank->clk);
2953
2954         return 0;
2955 }
2956
2957 static void rockchip_irq_suspend(struct irq_data *d)
2958 {
2959         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2960         struct rockchip_pin_bank *bank = gc->private;
2961
2962         clk_enable(bank->clk);
2963         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2964         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2965         clk_disable(bank->clk);
2966 }
2967
2968 static void rockchip_irq_resume(struct irq_data *d)
2969 {
2970         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2971         struct rockchip_pin_bank *bank = gc->private;
2972
2973         clk_enable(bank->clk);
2974         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2975         clk_disable(bank->clk);
2976 }
2977
2978 static void rockchip_irq_enable(struct irq_data *d)
2979 {
2980         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2981         struct rockchip_pin_bank *bank = gc->private;
2982
2983         clk_enable(bank->clk);
2984         irq_gc_mask_clr_bit(d);
2985 }
2986
2987 static void rockchip_irq_disable(struct irq_data *d)
2988 {
2989         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2990         struct rockchip_pin_bank *bank = gc->private;
2991
2992         irq_gc_mask_set_bit(d);
2993         clk_disable(bank->clk);
2994 }
2995
2996 static int rockchip_interrupts_register(struct platform_device *pdev,
2997                                                 struct rockchip_pinctrl *info)
2998 {
2999         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3000         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3001         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3002         struct irq_chip_generic *gc;
3003         int ret;
3004         int i, j;
3005
3006         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3007                 if (!bank->valid) {
3008                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3009                                  bank->name);
3010                         continue;
3011                 }
3012
3013                 ret = clk_enable(bank->clk);
3014                 if (ret) {
3015                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3016                                 bank->name);
3017                         continue;
3018                 }
3019
3020                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3021                                                 &irq_generic_chip_ops, NULL);
3022                 if (!bank->domain) {
3023                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3024                                  bank->name);
3025                         clk_disable(bank->clk);
3026                         continue;
3027                 }
3028
3029                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3030                                          "rockchip_gpio_irq", handle_level_irq,
3031                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
3032                 if (ret) {
3033                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3034                                 bank->name);
3035                         irq_domain_remove(bank->domain);
3036                         clk_disable(bank->clk);
3037                         continue;
3038                 }
3039
3040                 /*
3041                  * Linux assumes that all interrupts start out disabled/masked.
3042                  * Our driver only uses the concept of masked and always keeps
3043                  * things enabled, so for us that's all masked and all enabled.
3044                  */
3045                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3046                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3047
3048                 gc = irq_get_domain_generic_chip(bank->domain, 0);
3049                 gc->reg_base = bank->reg_base;
3050                 gc->private = bank;
3051                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3052                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3053                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3054                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3055                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3056                 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3057                 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3058                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3059                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3060                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3061                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3062                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3063
3064                 irq_set_chained_handler_and_data(bank->irq,
3065                                                  rockchip_irq_demux, bank);
3066
3067                 /* map the gpio irqs here, when the clock is still running */
3068                 for (j = 0 ; j < 32 ; j++)
3069                         irq_create_mapping(bank->domain, j);
3070
3071                 clk_disable(bank->clk);
3072         }
3073
3074         return 0;
3075 }
3076
3077 static int rockchip_gpiolib_register(struct platform_device *pdev,
3078                                                 struct rockchip_pinctrl *info)
3079 {
3080         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3081         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3082         struct gpio_chip *gc;
3083         int ret;
3084         int i;
3085
3086         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3087                 if (!bank->valid) {
3088                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3089                                  bank->name);
3090                         continue;
3091                 }
3092
3093                 bank->gpio_chip = rockchip_gpiolib_chip;
3094
3095                 gc = &bank->gpio_chip;
3096                 gc->base = bank->pin_base;
3097                 gc->ngpio = bank->nr_pins;
3098                 gc->parent = &pdev->dev;
3099                 gc->of_node = bank->of_node;
3100                 gc->label = bank->name;
3101
3102                 ret = gpiochip_add_data(gc, bank);
3103                 if (ret) {
3104                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3105                                                         gc->label, ret);
3106                         goto fail;
3107                 }
3108         }
3109
3110         rockchip_interrupts_register(pdev, info);
3111
3112         return 0;
3113
3114 fail:
3115         for (--i, --bank; i >= 0; --i, --bank) {
3116                 if (!bank->valid)
3117                         continue;
3118                 gpiochip_remove(&bank->gpio_chip);
3119         }
3120         return ret;
3121 }
3122
3123 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3124                                                 struct rockchip_pinctrl *info)
3125 {
3126         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3127         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3128         int i;
3129
3130         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3131                 if (!bank->valid)
3132                         continue;
3133                 gpiochip_remove(&bank->gpio_chip);
3134         }
3135
3136         return 0;
3137 }
3138
3139 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3140                                   struct rockchip_pinctrl *info)
3141 {
3142         struct resource res;
3143         void __iomem *base;
3144
3145         if (of_address_to_resource(bank->of_node, 0, &res)) {
3146                 dev_err(info->dev, "cannot find IO resource for bank\n");
3147                 return -ENOENT;
3148         }
3149
3150         bank->reg_base = devm_ioremap_resource(info->dev, &res);
3151         if (IS_ERR(bank->reg_base))
3152                 return PTR_ERR(bank->reg_base);
3153
3154         /*
3155          * special case, where parts of the pull setting-registers are
3156          * part of the PMU register space
3157          */
3158         if (of_device_is_compatible(bank->of_node,
3159                                     "rockchip,rk3188-gpio-bank0")) {
3160                 struct device_node *node;
3161
3162                 node = of_parse_phandle(bank->of_node->parent,
3163                                         "rockchip,pmu", 0);
3164                 if (!node) {
3165                         if (of_address_to_resource(bank->of_node, 1, &res)) {
3166                                 dev_err(info->dev, "cannot find IO resource for bank\n");
3167                                 return -ENOENT;
3168                         }
3169
3170                         base = devm_ioremap_resource(info->dev, &res);
3171                         if (IS_ERR(base))
3172                                 return PTR_ERR(base);
3173                         rockchip_regmap_config.max_register =
3174                                                     resource_size(&res) - 4;
3175                         rockchip_regmap_config.name =
3176                                             "rockchip,rk3188-gpio-bank0-pull";
3177                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3178                                                     base,
3179                                                     &rockchip_regmap_config);
3180                 }
3181                 of_node_put(node);
3182         }
3183
3184         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3185
3186         bank->clk = of_clk_get(bank->of_node, 0);
3187         if (IS_ERR(bank->clk))
3188                 return PTR_ERR(bank->clk);
3189
3190         return clk_prepare(bank->clk);
3191 }
3192
3193 static const struct of_device_id rockchip_pinctrl_dt_match[];
3194
3195 /* retrieve the soc specific data */
3196 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3197                                                 struct rockchip_pinctrl *d,
3198                                                 struct platform_device *pdev)
3199 {
3200         const struct of_device_id *match;
3201         struct device_node *node = pdev->dev.of_node;
3202         struct device_node *np;
3203         struct rockchip_pin_ctrl *ctrl;
3204         struct rockchip_pin_bank *bank;
3205         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3206
3207         match = of_match_node(rockchip_pinctrl_dt_match, node);
3208         ctrl = (struct rockchip_pin_ctrl *)match->data;
3209
3210         for_each_child_of_node(node, np) {
3211                 if (!of_find_property(np, "gpio-controller", NULL))
3212                         continue;
3213
3214                 bank = ctrl->pin_banks;
3215                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3216                         if (!strcmp(bank->name, np->name)) {
3217                                 bank->of_node = np;
3218
3219                                 if (!rockchip_get_bank_data(bank, d))
3220                                         bank->valid = true;
3221
3222                                 break;
3223                         }
3224                 }
3225         }
3226
3227         grf_offs = ctrl->grf_mux_offset;
3228         pmu_offs = ctrl->pmu_mux_offset;
3229         drv_pmu_offs = ctrl->pmu_drv_offset;
3230         drv_grf_offs = ctrl->grf_drv_offset;
3231         bank = ctrl->pin_banks;
3232         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3233                 int bank_pins = 0;
3234
3235                 raw_spin_lock_init(&bank->slock);
3236                 bank->drvdata = d;
3237                 bank->pin_base = ctrl->nr_pins;
3238                 ctrl->nr_pins += bank->nr_pins;
3239
3240                 /* calculate iomux and drv offsets */
3241                 for (j = 0; j < 4; j++) {
3242                         struct rockchip_iomux *iom = &bank->iomux[j];
3243                         struct rockchip_drv *drv = &bank->drv[j];
3244                         int inc;
3245
3246                         if (bank_pins >= bank->nr_pins)
3247                                 break;
3248
3249                         /* preset iomux offset value, set new start value */
3250                         if (iom->offset >= 0) {
3251                                 if (iom->type & IOMUX_SOURCE_PMU)
3252                                         pmu_offs = iom->offset;
3253                                 else
3254                                         grf_offs = iom->offset;
3255                         } else { /* set current iomux offset */
3256                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3257                                                         pmu_offs : grf_offs;
3258                         }
3259
3260                         /* preset drv offset value, set new start value */
3261                         if (drv->offset >= 0) {
3262                                 if (iom->type & IOMUX_SOURCE_PMU)
3263                                         drv_pmu_offs = drv->offset;
3264                                 else
3265                                         drv_grf_offs = drv->offset;
3266                         } else { /* set current drv offset */
3267                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3268                                                 drv_pmu_offs : drv_grf_offs;
3269                         }
3270
3271                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3272                                 i, j, iom->offset, drv->offset);
3273
3274                         /*
3275                          * Increase offset according to iomux width.
3276                          * 4bit iomux'es are spread over two registers.
3277                          */
3278                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3279                                             IOMUX_WIDTH_3BIT)) ? 8 : 4;
3280                         if (iom->type & IOMUX_SOURCE_PMU)
3281                                 pmu_offs += inc;
3282                         else
3283                                 grf_offs += inc;
3284
3285                         /*
3286                          * Increase offset according to drv width.
3287                          * 3bit drive-strenth'es are spread over two registers.
3288                          */
3289                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3290                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3291                                 inc = 8;
3292                         else
3293                                 inc = 4;
3294
3295                         if (iom->type & IOMUX_SOURCE_PMU)
3296                                 drv_pmu_offs += inc;
3297                         else
3298                                 drv_grf_offs += inc;
3299
3300                         bank_pins += 8;
3301                 }
3302
3303                 /* calculate the per-bank recalced_mask */
3304                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3305                         int pin = 0;
3306
3307                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3308                                 pin = ctrl->iomux_recalced[j].pin;
3309                                 bank->recalced_mask |= BIT(pin);
3310                         }
3311                 }
3312
3313                 /* calculate the per-bank route_mask */
3314                 for (j = 0; j < ctrl->niomux_routes; j++) {
3315                         int pin = 0;
3316
3317                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3318                                 pin = ctrl->iomux_routes[j].pin;
3319                                 bank->route_mask |= BIT(pin);
3320                         }
3321                 }
3322         }
3323
3324         return ctrl;
3325 }
3326
3327 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3328 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3329
3330 static u32 rk3288_grf_gpio6c_iomux;
3331
3332 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3333 {
3334         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3335         int ret = pinctrl_force_sleep(info->pctl_dev);
3336
3337         if (ret)
3338                 return ret;
3339
3340         /*
3341          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3342          * the setting here, and restore it at resume.
3343          */
3344         if (info->ctrl->type == RK3288) {
3345                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3346                                   &rk3288_grf_gpio6c_iomux);
3347                 if (ret) {
3348                         pinctrl_force_default(info->pctl_dev);
3349                         return ret;
3350                 }
3351         }
3352
3353         return 0;
3354 }
3355
3356 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3357 {
3358         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3359         int ret;
3360
3361         if (info->ctrl->type == RK3288) {
3362                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3363                                    rk3288_grf_gpio6c_iomux |
3364                                    GPIO6C6_SEL_WRITE_ENABLE);
3365                 if (ret)
3366                         return ret;
3367         }
3368
3369         return pinctrl_force_default(info->pctl_dev);
3370 }
3371
3372 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3373                          rockchip_pinctrl_resume);
3374
3375 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3376 {
3377         struct rockchip_pinctrl *info;
3378         struct device *dev = &pdev->dev;
3379         struct rockchip_pin_ctrl *ctrl;
3380         struct device_node *np = pdev->dev.of_node, *node;
3381         struct resource *res;
3382         void __iomem *base;
3383         int ret;
3384
3385         if (!dev->of_node) {
3386                 dev_err(dev, "device tree node not found\n");
3387                 return -ENODEV;
3388         }
3389
3390         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3391         if (!info)
3392                 return -ENOMEM;
3393
3394         info->dev = dev;
3395
3396         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3397         if (!ctrl) {
3398                 dev_err(dev, "driver data not available\n");
3399                 return -EINVAL;
3400         }
3401         info->ctrl = ctrl;
3402
3403         node = of_parse_phandle(np, "rockchip,grf", 0);
3404         if (node) {
3405                 info->regmap_base = syscon_node_to_regmap(node);
3406                 of_node_put(node);
3407                 if (IS_ERR(info->regmap_base))
3408                         return PTR_ERR(info->regmap_base);
3409         } else {
3410                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3411                 base = devm_ioremap_resource(&pdev->dev, res);
3412                 if (IS_ERR(base))
3413                         return PTR_ERR(base);
3414
3415                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3416                 rockchip_regmap_config.name = "rockchip,pinctrl";
3417                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3418                                                     &rockchip_regmap_config);
3419
3420                 /* to check for the old dt-bindings */
3421                 info->reg_size = resource_size(res);
3422
3423                 /* Honor the old binding, with pull registers as 2nd resource */
3424                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3425                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3426                         base = devm_ioremap_resource(&pdev->dev, res);
3427                         if (IS_ERR(base))
3428                                 return PTR_ERR(base);
3429
3430                         rockchip_regmap_config.max_register =
3431                                                         resource_size(res) - 4;
3432                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3433                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3434                                                     base,
3435                                                     &rockchip_regmap_config);
3436                 }
3437         }
3438
3439         /* try to find the optional reference to the pmu syscon */
3440         node = of_parse_phandle(np, "rockchip,pmu", 0);
3441         if (node) {
3442                 info->regmap_pmu = syscon_node_to_regmap(node);
3443                 of_node_put(node);
3444                 if (IS_ERR(info->regmap_pmu))
3445                         return PTR_ERR(info->regmap_pmu);
3446         }
3447
3448         ret = rockchip_gpiolib_register(pdev, info);
3449         if (ret)
3450                 return ret;
3451
3452         ret = rockchip_pinctrl_register(pdev, info);
3453         if (ret) {
3454                 rockchip_gpiolib_unregister(pdev, info);
3455                 return ret;
3456         }
3457
3458         platform_set_drvdata(pdev, info);
3459
3460         return 0;
3461 }
3462
3463 static struct rockchip_pin_bank px30_pin_banks[] = {
3464         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3465                                              IOMUX_SOURCE_PMU,
3466                                              IOMUX_SOURCE_PMU,
3467                                              IOMUX_SOURCE_PMU
3468                             ),
3469         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3470                                              IOMUX_WIDTH_4BIT,
3471                                              IOMUX_WIDTH_4BIT,
3472                                              IOMUX_WIDTH_4BIT
3473                             ),
3474         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3475                                              IOMUX_WIDTH_4BIT,
3476                                              IOMUX_WIDTH_4BIT,
3477                                              IOMUX_WIDTH_4BIT
3478                             ),
3479         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3480                                              IOMUX_WIDTH_4BIT,
3481                                              IOMUX_WIDTH_4BIT,
3482                                              IOMUX_WIDTH_4BIT
3483                             ),
3484 };
3485
3486 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3487                 .pin_banks              = px30_pin_banks,
3488                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
3489                 .label                  = "PX30-GPIO",
3490                 .type                   = PX30,
3491                 .grf_mux_offset         = 0x0,
3492                 .pmu_mux_offset         = 0x0,
3493                 .iomux_routes           = px30_mux_route_data,
3494                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
3495                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
3496                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
3497                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
3498 };
3499
3500 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3501         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3502                                              IOMUX_SOURCE_PMU,
3503                                              IOMUX_SOURCE_PMU,
3504                                              IOMUX_SOURCE_PMU),
3505         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3506         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3507         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3508 };
3509
3510 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3511         .pin_banks              = rv1108_pin_banks,
3512         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3513         .label                  = "RV1108-GPIO",
3514         .type                   = RV1108,
3515         .grf_mux_offset         = 0x10,
3516         .pmu_mux_offset         = 0x0,
3517         .iomux_recalced         = rv1108_mux_recalced_data,
3518         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3519         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3520         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3521         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3522 };
3523
3524 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3525         PIN_BANK(0, 32, "gpio0"),
3526         PIN_BANK(1, 32, "gpio1"),
3527         PIN_BANK(2, 32, "gpio2"),
3528         PIN_BANK(3, 32, "gpio3"),
3529 };
3530
3531 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3532                 .pin_banks              = rk2928_pin_banks,
3533                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3534                 .label                  = "RK2928-GPIO",
3535                 .type                   = RK2928,
3536                 .grf_mux_offset         = 0xa8,
3537                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3538 };
3539
3540 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3541         PIN_BANK(0, 32, "gpio0"),
3542         PIN_BANK(1, 32, "gpio1"),
3543         PIN_BANK(2, 32, "gpio2"),
3544 };
3545
3546 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3547                 .pin_banks              = rk3036_pin_banks,
3548                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3549                 .label                  = "RK3036-GPIO",
3550                 .type                   = RK2928,
3551                 .grf_mux_offset         = 0xa8,
3552                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3553 };
3554
3555 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3556         PIN_BANK(0, 32, "gpio0"),
3557         PIN_BANK(1, 32, "gpio1"),
3558         PIN_BANK(2, 32, "gpio2"),
3559         PIN_BANK(3, 32, "gpio3"),
3560         PIN_BANK(4, 32, "gpio4"),
3561         PIN_BANK(6, 16, "gpio6"),
3562 };
3563
3564 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3565                 .pin_banks              = rk3066a_pin_banks,
3566                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3567                 .label                  = "RK3066a-GPIO",
3568                 .type                   = RK2928,
3569                 .grf_mux_offset         = 0xa8,
3570                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3571 };
3572
3573 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3574         PIN_BANK(0, 32, "gpio0"),
3575         PIN_BANK(1, 32, "gpio1"),
3576         PIN_BANK(2, 32, "gpio2"),
3577         PIN_BANK(3, 32, "gpio3"),
3578 };
3579
3580 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3581                 .pin_banks      = rk3066b_pin_banks,
3582                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3583                 .label          = "RK3066b-GPIO",
3584                 .type           = RK3066B,
3585                 .grf_mux_offset = 0x60,
3586 };
3587
3588 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3589         PIN_BANK(0, 32, "gpio0"),
3590         PIN_BANK(1, 32, "gpio1"),
3591         PIN_BANK(2, 32, "gpio2"),
3592         PIN_BANK(3, 32, "gpio3"),
3593 };
3594
3595 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3596                 .pin_banks              = rk3128_pin_banks,
3597                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3598                 .label                  = "RK3128-GPIO",
3599                 .type                   = RK3128,
3600                 .grf_mux_offset         = 0xa8,
3601                 .iomux_recalced         = rk3128_mux_recalced_data,
3602                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3603                 .iomux_routes           = rk3128_mux_route_data,
3604                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3605                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3606 };
3607
3608 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3609         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3610         PIN_BANK(1, 32, "gpio1"),
3611         PIN_BANK(2, 32, "gpio2"),
3612         PIN_BANK(3, 32, "gpio3"),
3613 };
3614
3615 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3616                 .pin_banks              = rk3188_pin_banks,
3617                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3618                 .label                  = "RK3188-GPIO",
3619                 .type                   = RK3188,
3620                 .grf_mux_offset         = 0x60,
3621                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3622 };
3623
3624 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3625         PIN_BANK(0, 32, "gpio0"),
3626         PIN_BANK(1, 32, "gpio1"),
3627         PIN_BANK(2, 32, "gpio2"),
3628         PIN_BANK(3, 32, "gpio3"),
3629 };
3630
3631 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3632                 .pin_banks              = rk3228_pin_banks,
3633                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3634                 .label                  = "RK3228-GPIO",
3635                 .type                   = RK3288,
3636                 .grf_mux_offset         = 0x0,
3637                 .iomux_routes           = rk3228_mux_route_data,
3638                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3639                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3640                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3641 };
3642
3643 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3644         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3645                                              IOMUX_SOURCE_PMU,
3646                                              IOMUX_SOURCE_PMU,
3647                                              IOMUX_UNROUTED
3648                             ),
3649         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3650                                              IOMUX_UNROUTED,
3651                                              IOMUX_UNROUTED,
3652                                              0
3653                             ),
3654         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3655         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3656         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3657                                              IOMUX_WIDTH_4BIT,
3658                                              0,
3659                                              0
3660                             ),
3661         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3662                                              0,
3663                                              0,
3664                                              IOMUX_UNROUTED
3665                             ),
3666         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3667         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3668                                              0,
3669                                              IOMUX_WIDTH_4BIT,
3670                                              IOMUX_UNROUTED
3671                             ),
3672         PIN_BANK(8, 16, "gpio8"),
3673 };
3674
3675 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3676                 .pin_banks              = rk3288_pin_banks,
3677                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3678                 .label                  = "RK3288-GPIO",
3679                 .type                   = RK3288,
3680                 .grf_mux_offset         = 0x0,
3681                 .pmu_mux_offset         = 0x84,
3682                 .iomux_routes           = rk3288_mux_route_data,
3683                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3684                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3685                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3686 };
3687
3688 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3689         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3690         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3691         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3692                              IOMUX_WIDTH_3BIT,
3693                              IOMUX_WIDTH_3BIT,
3694                              0),
3695         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3696                              IOMUX_WIDTH_3BIT,
3697                              IOMUX_WIDTH_3BIT,
3698                              0,
3699                              0),
3700 };
3701
3702 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3703                 .pin_banks              = rk3328_pin_banks,
3704                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3705                 .label                  = "RK3328-GPIO",
3706                 .type                   = RK3288,
3707                 .grf_mux_offset         = 0x0,
3708                 .iomux_recalced         = rk3328_mux_recalced_data,
3709                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3710                 .iomux_routes           = rk3328_mux_route_data,
3711                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3712                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3713                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3714                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3715 };
3716
3717 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3718         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3719                                              IOMUX_SOURCE_PMU,
3720                                              IOMUX_SOURCE_PMU,
3721                                              IOMUX_SOURCE_PMU
3722                             ),
3723         PIN_BANK(1, 32, "gpio1"),
3724         PIN_BANK(2, 32, "gpio2"),
3725         PIN_BANK(3, 32, "gpio3"),
3726 };
3727
3728 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3729                 .pin_banks              = rk3368_pin_banks,
3730                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3731                 .label                  = "RK3368-GPIO",
3732                 .type                   = RK3368,
3733                 .grf_mux_offset         = 0x0,
3734                 .pmu_mux_offset         = 0x0,
3735                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3736                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3737 };
3738
3739 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3740         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3741                                                          IOMUX_SOURCE_PMU,
3742                                                          IOMUX_SOURCE_PMU,
3743                                                          IOMUX_SOURCE_PMU,
3744                                                          IOMUX_SOURCE_PMU,
3745                                                          DRV_TYPE_IO_1V8_ONLY,
3746                                                          DRV_TYPE_IO_1V8_ONLY,
3747                                                          DRV_TYPE_IO_DEFAULT,
3748                                                          DRV_TYPE_IO_DEFAULT,
3749                                                          0x80,
3750                                                          0x88,
3751                                                          -1,
3752                                                          -1,
3753                                                          PULL_TYPE_IO_1V8_ONLY,
3754                                                          PULL_TYPE_IO_1V8_ONLY,
3755                                                          PULL_TYPE_IO_DEFAULT,
3756                                                          PULL_TYPE_IO_DEFAULT
3757                                                         ),
3758         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3759                                         IOMUX_SOURCE_PMU,
3760                                         IOMUX_SOURCE_PMU,
3761                                         IOMUX_SOURCE_PMU,
3762                                         DRV_TYPE_IO_1V8_OR_3V0,
3763                                         DRV_TYPE_IO_1V8_OR_3V0,
3764                                         DRV_TYPE_IO_1V8_OR_3V0,
3765                                         DRV_TYPE_IO_1V8_OR_3V0,
3766                                         0xa0,
3767                                         0xa8,
3768                                         0xb0,
3769                                         0xb8
3770                                         ),
3771         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3772                                       DRV_TYPE_IO_1V8_OR_3V0,
3773                                       DRV_TYPE_IO_1V8_ONLY,
3774                                       DRV_TYPE_IO_1V8_ONLY,
3775                                       PULL_TYPE_IO_DEFAULT,
3776                                       PULL_TYPE_IO_DEFAULT,
3777                                       PULL_TYPE_IO_1V8_ONLY,
3778                                       PULL_TYPE_IO_1V8_ONLY
3779                                       ),
3780         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3781                            DRV_TYPE_IO_3V3_ONLY,
3782                            DRV_TYPE_IO_3V3_ONLY,
3783                            DRV_TYPE_IO_1V8_OR_3V0
3784                            ),
3785         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3786                            DRV_TYPE_IO_1V8_3V0_AUTO,
3787                            DRV_TYPE_IO_1V8_OR_3V0,
3788                            DRV_TYPE_IO_1V8_OR_3V0
3789                            ),
3790 };
3791
3792 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3793                 .pin_banks              = rk3399_pin_banks,
3794                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3795                 .label                  = "RK3399-GPIO",
3796                 .type                   = RK3399,
3797                 .grf_mux_offset         = 0xe000,
3798                 .pmu_mux_offset         = 0x0,
3799                 .grf_drv_offset         = 0xe100,
3800                 .pmu_drv_offset         = 0x80,
3801                 .iomux_routes           = rk3399_mux_route_data,
3802                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3803                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3804                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3805 };
3806
3807 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3808         { .compatible = "rockchip,px30-pinctrl",
3809                 .data = &px30_pin_ctrl },
3810         { .compatible = "rockchip,rv1108-pinctrl",
3811                 .data = &rv1108_pin_ctrl },
3812         { .compatible = "rockchip,rk2928-pinctrl",
3813                 .data = &rk2928_pin_ctrl },
3814         { .compatible = "rockchip,rk3036-pinctrl",
3815                 .data = &rk3036_pin_ctrl },
3816         { .compatible = "rockchip,rk3066a-pinctrl",
3817                 .data = &rk3066a_pin_ctrl },
3818         { .compatible = "rockchip,rk3066b-pinctrl",
3819                 .data = &rk3066b_pin_ctrl },
3820         { .compatible = "rockchip,rk3128-pinctrl",
3821                 .data = (void *)&rk3128_pin_ctrl },
3822         { .compatible = "rockchip,rk3188-pinctrl",
3823                 .data = &rk3188_pin_ctrl },
3824         { .compatible = "rockchip,rk3228-pinctrl",
3825                 .data = &rk3228_pin_ctrl },
3826         { .compatible = "rockchip,rk3288-pinctrl",
3827                 .data = &rk3288_pin_ctrl },
3828         { .compatible = "rockchip,rk3328-pinctrl",
3829                 .data = &rk3328_pin_ctrl },
3830         { .compatible = "rockchip,rk3368-pinctrl",
3831                 .data = &rk3368_pin_ctrl },
3832         { .compatible = "rockchip,rk3399-pinctrl",
3833                 .data = &rk3399_pin_ctrl },
3834         {},
3835 };
3836
3837 static struct platform_driver rockchip_pinctrl_driver = {
3838         .probe          = rockchip_pinctrl_probe,
3839         .driver = {
3840                 .name   = "rockchip-pinctrl",
3841                 .pm = &rockchip_pinctrl_dev_pm_ops,
3842                 .of_match_table = rockchip_pinctrl_dt_match,
3843         },
3844 };
3845
3846 static int __init rockchip_pinctrl_drv_register(void)
3847 {
3848         return platform_driver_register(&rockchip_pinctrl_driver);
3849 }
3850 postcore_initcall(rockchip_pinctrl_drv_register);