drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66         RK3368,
  67 };
  68
  69 /**
  70  * Encode variants of iomux registers into a type variable
  71  */
  72 #define IOMUX_GPIO_ONLY         BIT(0)
  73 #define IOMUX_WIDTH_4BIT        BIT(1)
  74 #define IOMUX_SOURCE_PMU        BIT(2)
  75 #define IOMUX_UNROUTED          BIT(3)
  76
  77 /**
  78  * @type: iomux variant using IOMUX_* constants
  79  * @offset: if initialized to -1 it will be autocalculated, by specifying
  80  *          an initial offset value the relevant source offset can be reset
  81  *          to a new value for autocalculating the following iomux registers.
  82  */
  83 struct rockchip_iomux {
  84         int                             type;
  85         int                             offset;
  86 };
  87
  88 /**
  89  * @reg_base: register base of the gpio bank
  90  * @reg_pull: optional separate register for additional pull settings
  91  * @clk: clock of the gpio bank
  92  * @irq: interrupt of the gpio bank
  93  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
  94  * @pin_base: first pin number
  95  * @nr_pins: number of pins in this bank
  96  * @name: name of the bank
  97  * @bank_num: number of the bank, to account for holes
  98  * @iomux: array describing the 4 iomux sources of the bank
  99  * @valid: are all necessary informations present
 100  * @of_node: dt node of this bank
 101  * @drvdata: common pinctrl basedata
 102  * @domain: irqdomain of the gpio bank
 103  * @gpio_chip: gpiolib chip
 104  * @grange: gpio range
 105  * @slock: spinlock for the gpio bank
 106  */
 107 struct rockchip_pin_bank {
 108         void __iomem                    *reg_base;
 109         struct regmap                   *regmap_pull;
 110         struct clk                      *clk;
 111         int                             irq;
 112         u32                             saved_masks;
 113         u32                             pin_base;
 114         u8                              nr_pins;
 115         char                            *name;
 116         u8                              bank_num;
 117         struct rockchip_iomux           iomux[4];
 118         bool                            valid;
 119         struct device_node              *of_node;
 120         struct rockchip_pinctrl         *drvdata;
 121         struct irq_domain               *domain;
 122         struct gpio_chip                gpio_chip;
 123         struct pinctrl_gpio_range       grange;
 124         spinlock_t                      slock;
 125         u32                             toggle_edge_mode;
 126 };
 127
 128 #define PIN_BANK(id, pins, label)                       \
 129         {                                               \
 130                 .bank_num       = id,                   \
 131                 .nr_pins        = pins,                 \
 132                 .name           = label,                \
 133                 .iomux          = {                     \
 134                         { .offset = -1 },               \
 135                         { .offset = -1 },               \
 136                         { .offset = -1 },               \
 137                         { .offset = -1 },               \
 138                 },                                      \
 139         }
 140
 141 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 142         {                                                               \
 143                 .bank_num       = id,                                   \
 144                 .nr_pins        = pins,                                 \
 145                 .name           = label,                                \
 146                 .iomux          = {                                     \
 147                         { .type = iom0, .offset = -1 },                 \
 148                         { .type = iom1, .offset = -1 },                 \
 149                         { .type = iom2, .offset = -1 },                 \
 150                         { .type = iom3, .offset = -1 },                 \
 151                 },                                                      \
 152         }
 153
 154 /**
 155  */
 156 struct rockchip_pin_ctrl {
 157         struct rockchip_pin_bank        *pin_banks;
 158         u32                             nr_banks;
 159         u32                             nr_pins;
 160         char                            *label;
 161         enum rockchip_pinctrl_type      type;
 162         int                             grf_mux_offset;
 163         int                             pmu_mux_offset;
 164         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 165                                     int pin_num, struct regmap **regmap,
 166                                     int *reg, u8 *bit);
 167         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 168                                     int pin_num, struct regmap **regmap,
 169                                     int *reg, u8 *bit);
 170 };
 171
 172 struct rockchip_pin_config {
 173         unsigned int            func;
 174         unsigned long           *configs;
 175         unsigned int            nconfigs;
 176 };
 177
 178 /**
 179  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 180  * @name: name of the pin group, used to lookup the group.
 181  * @pins: the pins included in this group.
 182  * @npins: number of pins included in this group.
 183  * @func: the mux function number to be programmed when selected.
 184  * @configs: the config values to be set for each pin
 185  * @nconfigs: number of configs for each pin
 186  */
 187 struct rockchip_pin_group {
 188         const char                      *name;
 189         unsigned int                    npins;
 190         unsigned int                    *pins;
 191         struct rockchip_pin_config      *data;
 192 };
 193
 194 /**
 195  * struct rockchip_pmx_func: represent a pin function.
 196  * @name: name of the pin function, used to lookup the function.
 197  * @groups: one or more names of pin groups that provide this function.
 198  * @num_groups: number of groups included in @groups.
 199  */
 200 struct rockchip_pmx_func {
 201         const char              *name;
 202         const char              **groups;
 203         u8                      ngroups;
 204 };
 205
 206 struct rockchip_pinctrl {
 207         struct regmap                   *regmap_base;
 208         int                             reg_size;
 209         struct regmap                   *regmap_pull;
 210         struct regmap                   *regmap_pmu;
 211         struct device                   *dev;
 212         struct rockchip_pin_ctrl        *ctrl;
 213         struct pinctrl_desc             pctl;
 214         struct pinctrl_dev              *pctl_dev;
 215         struct rockchip_pin_group       *groups;
 216         unsigned int                    ngroups;
 217         struct rockchip_pmx_func        *functions;
 218         unsigned int                    nfunctions;
 219 };
 220
 221 static struct regmap_config rockchip_regmap_config = {
 222         .reg_bits = 32,
 223         .val_bits = 32,
 224         .reg_stride = 4,
 225 };
 226
 227 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 228 {
 229         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 230 }
 231
 232 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 233                                         const struct rockchip_pinctrl *info,
 234                                         const char *name)
 235 {
 236         int i;
 237
 238         for (i = 0; i < info->ngroups; i++) {
 239                 if (!strcmp(info->groups[i].name, name))
 240                         return &info->groups[i];
 241         }
 242
 243         return NULL;
 244 }
 245
 246 /*
 247  * given a pin number that is local to a pin controller, find out the pin bank
 248  * and the register base of the pin bank.
 249  */
 250 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 251                                                                 unsigned pin)
 252 {
 253         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 254
 255         while (pin >= (b->pin_base + b->nr_pins))
 256                 b++;
 257
 258         return b;
 259 }
 260
 261 static struct rockchip_pin_bank *bank_num_to_bank(
 262                                         struct rockchip_pinctrl *info,
 263                                         unsigned num)
 264 {
 265         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 266         int i;
 267
 268         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 269                 if (b->bank_num == num)
 270                         return b;
 271         }
 272
 273         return ERR_PTR(-EINVAL);
 274 }
 275
 276 /*
 277  * Pinctrl_ops handling
 278  */
 279
 280 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 281 {
 282         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 283
 284         return info->ngroups;
 285 }
 286
 287 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 288                                                         unsigned selector)
 289 {
 290         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 291
 292         return info->groups[selector].name;
 293 }
 294
 295 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 296                                       unsigned selector, const unsigned **pins,
 297                                       unsigned *npins)
 298 {
 299         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 300
 301         if (selector >= info->ngroups)
 302                 return -EINVAL;
 303
 304         *pins = info->groups[selector].pins;
 305         *npins = info->groups[selector].npins;
 306
 307         return 0;
 308 }
 309
 310 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 311                                  struct device_node *np,
 312                                  struct pinctrl_map **map, unsigned *num_maps)
 313 {
 314         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 315         const struct rockchip_pin_group *grp;
 316         struct pinctrl_map *new_map;
 317         struct device_node *parent;
 318         int map_num = 1;
 319         int i;
 320
 321         /*
 322          * first find the group of this node and check if we need to create
 323          * config maps for pins
 324          */
 325         grp = pinctrl_name_to_group(info, np->name);
 326         if (!grp) {
 327                 dev_err(info->dev, "unable to find group for node %s\n",
 328                         np->name);
 329                 return -EINVAL;
 330         }
 331
 332         map_num += grp->npins;
 333         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 334                                                                 GFP_KERNEL);
 335         if (!new_map)
 336                 return -ENOMEM;
 337
 338         *map = new_map;
 339         *num_maps = map_num;
 340
 341         /* create mux map */
 342         parent = of_get_parent(np);
 343         if (!parent) {
 344                 devm_kfree(pctldev->dev, new_map);
 345                 return -EINVAL;
 346         }
 347         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 348         new_map[0].data.mux.function = parent->name;
 349         new_map[0].data.mux.group = np->name;
 350         of_node_put(parent);
 351
 352         /* create config map */
 353         new_map++;
 354         for (i = 0; i < grp->npins; i++) {
 355                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 356                 new_map[i].data.configs.group_or_pin =
 357                                 pin_get_name(pctldev, grp->pins[i]);
 358                 new_map[i].data.configs.configs = grp->data[i].configs;
 359                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 360         }
 361
 362         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 363                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 364
 365         return 0;
 366 }
 367
 368 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 369                                     struct pinctrl_map *map, unsigned num_maps)
 370 {
 371 }
 372
 373 static const struct pinctrl_ops rockchip_pctrl_ops = {
 374         .get_groups_count       = rockchip_get_groups_count,
 375         .get_group_name         = rockchip_get_group_name,
 376         .get_group_pins         = rockchip_get_group_pins,
 377         .dt_node_to_map         = rockchip_dt_node_to_map,
 378         .dt_free_map            = rockchip_dt_free_map,
 379 };
 380
 381 /*
 382  * Hardware access
 383  */
 384
 385 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 386 {
 387         struct rockchip_pinctrl *info = bank->drvdata;
 388         int iomux_num = (pin / 8);
 389         struct regmap *regmap;
 390         unsigned int val;
 391         int reg, ret, mask;
 392         u8 bit;
 393
 394         if (iomux_num > 3)
 395                 return -EINVAL;
 396
 397         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 398                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 399                 return -EINVAL;
 400         }
 401
 402         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 403                 return RK_FUNC_GPIO;
 404
 405         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 406                                 ? info->regmap_pmu : info->regmap_base;
 407
 408         /* get basic quadrupel of mux registers and the correct reg inside */
 409         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 410         reg = bank->iomux[iomux_num].offset;
 411         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 412                 if ((pin % 8) >= 4)
 413                         reg += 0x4;
 414                 bit = (pin % 4) * 4;
 415         } else {
 416                 bit = (pin % 8) * 2;
 417         }
 418
 419         ret = regmap_read(regmap, reg, &val);
 420         if (ret)
 421                 return ret;
 422
 423         return ((val >> bit) & mask);
 424 }
 425
 426 /*
 427  * Set a new mux function for a pin.
 428  *
 429  * The register is divided into the upper and lower 16 bit. When changing
 430  * a value, the previous register value is not read and changed. Instead
 431  * it seems the changed bits are marked in the upper 16 bit, while the
 432  * changed value gets set in the same offset in the lower 16 bit.
 433  * All pin settings seem to be 2 bit wide in both the upper and lower
 434  * parts.
 435  * @bank: pin bank to change
 436  * @pin: pin to change
 437  * @mux: new mux function to set
 438  */
 439 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 440 {
 441         struct rockchip_pinctrl *info = bank->drvdata;
 442         int iomux_num = (pin / 8);
 443         struct regmap *regmap;
 444         int reg, ret, mask;
 445         unsigned long flags;
 446         u8 bit;
 447         u32 data, rmask;
 448
 449         if (iomux_num > 3)
 450                 return -EINVAL;
 451
 452         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 453                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 454                 return -EINVAL;
 455         }
 456
 457         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 458                 if (mux != RK_FUNC_GPIO) {
 459                         dev_err(info->dev,
 460                                 "pin %d only supports a gpio mux\n", pin);
 461                         return -ENOTSUPP;
 462                 } else {
 463                         return 0;
 464                 }
 465         }
 466
 467         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 468                                                 bank->bank_num, pin, mux);
 469
 470         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 471                                 ? info->regmap_pmu : info->regmap_base;
 472
 473         /* get basic quadrupel of mux registers and the correct reg inside */
 474         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 475         reg = bank->iomux[iomux_num].offset;
 476         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 477                 if ((pin % 8) >= 4)
 478                         reg += 0x4;
 479                 bit = (pin % 4) * 4;
 480         } else {
 481                 bit = (pin % 8) * 2;
 482         }
 483
 484         spin_lock_irqsave(&bank->slock, flags);
 485
 486         data = (mask << (bit + 16));
 487         rmask = data | (data >> 16);
 488         data |= (mux & mask) << bit;
 489         ret = regmap_update_bits(regmap, reg, rmask, data);
 490
 491         spin_unlock_irqrestore(&bank->slock, flags);
 492
 493         return ret;
 494 }
 495
 496 #define RK2928_PULL_OFFSET              0x118
 497 #define RK2928_PULL_PINS_PER_REG        16
 498 #define RK2928_PULL_BANK_STRIDE         8
 499
 500 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 501                                     int pin_num, struct regmap **regmap,
 502                                     int *reg, u8 *bit)
 503 {
 504         struct rockchip_pinctrl *info = bank->drvdata;
 505
 506         *regmap = info->regmap_base;
 507         *reg = RK2928_PULL_OFFSET;
 508         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 509         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 510
 511         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 512 };
 513
 514 #define RK3188_PULL_OFFSET              0x164
 515 #define RK3188_PULL_BITS_PER_PIN        2
 516 #define RK3188_PULL_PINS_PER_REG        8
 517 #define RK3188_PULL_BANK_STRIDE         16
 518 #define RK3188_PULL_PMU_OFFSET          0x64
 519
 520 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 521                                     int pin_num, struct regmap **regmap,
 522                                     int *reg, u8 *bit)
 523 {
 524         struct rockchip_pinctrl *info = bank->drvdata;
 525
 526         /* The first 12 pins of the first bank are located elsewhere */
 527         if (bank->bank_num == 0 && pin_num < 12) {
 528                 *regmap = info->regmap_pmu ? info->regmap_pmu
 529                                            : bank->regmap_pull;
 530                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 531                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 532                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 533                 *bit *= RK3188_PULL_BITS_PER_PIN;
 534         } else {
 535                 *regmap = info->regmap_pull ? info->regmap_pull
 536                                             : info->regmap_base;
 537                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 538
 539                 /* correct the offset, as it is the 2nd pull register */
 540                 *reg -= 4;
 541                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 542                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 543
 544                 /*
 545                  * The bits in these registers have an inverse ordering
 546                  * with the lowest pin being in bits 15:14 and the highest
 547                  * pin in bits 1:0
 548                  */
 549                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 550                 *bit *= RK3188_PULL_BITS_PER_PIN;
 551         }
 552 }
 553
 554 #define RK3288_PULL_OFFSET              0x140
 555 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 556                                     int pin_num, struct regmap **regmap,
 557                                     int *reg, u8 *bit)
 558 {
 559         struct rockchip_pinctrl *info = bank->drvdata;
 560
 561         /* The first 24 pins of the first bank are located in PMU */
 562         if (bank->bank_num == 0) {
 563                 *regmap = info->regmap_pmu;
 564                 *reg = RK3188_PULL_PMU_OFFSET;
 565
 566                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 567                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 568                 *bit *= RK3188_PULL_BITS_PER_PIN;
 569         } else {
 570                 *regmap = info->regmap_base;
 571                 *reg = RK3288_PULL_OFFSET;
 572
 573                 /* correct the offset, as we're starting with the 2nd bank */
 574                 *reg -= 0x10;
 575                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 576                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 577
 578                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 579                 *bit *= RK3188_PULL_BITS_PER_PIN;
 580         }
 581 }
 582
 583 #define RK3288_DRV_PMU_OFFSET           0x70
 584 #define RK3288_DRV_GRF_OFFSET           0x1c0
 585 #define RK3288_DRV_BITS_PER_PIN         2
 586 #define RK3288_DRV_PINS_PER_REG         8
 587 #define RK3288_DRV_BANK_STRIDE          16
 588
 589 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 590                                     int pin_num, struct regmap **regmap,
 591                                     int *reg, u8 *bit)
 592 {
 593         struct rockchip_pinctrl *info = bank->drvdata;
 594
 595         /* The first 24 pins of the first bank are located in PMU */
 596         if (bank->bank_num == 0) {
 597                 *regmap = info->regmap_pmu;
 598                 *reg = RK3288_DRV_PMU_OFFSET;
 599
 600                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 601                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 602                 *bit *= RK3288_DRV_BITS_PER_PIN;
 603         } else {
 604                 *regmap = info->regmap_base;
 605                 *reg = RK3288_DRV_GRF_OFFSET;
 606
 607                 /* correct the offset, as we're starting with the 2nd bank */
 608                 *reg -= 0x10;
 609                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 610                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 611
 612                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 613                 *bit *= RK3288_DRV_BITS_PER_PIN;
 614         }
 615 }
 616
 617 #define RK3368_PULL_GRF_OFFSET          0x100
 618 #define RK3368_PULL_PMU_OFFSET          0x10
 619
 620 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 621                                     int pin_num, struct regmap **regmap,
 622                                     int *reg, u8 *bit)
 623 {
 624         struct rockchip_pinctrl *info = bank->drvdata;
 625
 626         /* The first 32 pins of the first bank are located in PMU */
 627         if (bank->bank_num == 0) {
 628                 *regmap = info->regmap_pmu;
 629                 *reg = RK3368_PULL_PMU_OFFSET;
 630
 631                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 632                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 633                 *bit *= RK3188_PULL_BITS_PER_PIN;
 634         } else {
 635                 *regmap = info->regmap_base;
 636                 *reg = RK3368_PULL_GRF_OFFSET;
 637
 638                 /* correct the offset, as we're starting with the 2nd bank */
 639                 *reg -= 0x10;
 640                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 641                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 642
 643                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 644                 *bit *= RK3188_PULL_BITS_PER_PIN;
 645         }
 646 }
 647
 648 #define RK3368_DRV_PMU_OFFSET           0x20
 649 #define RK3368_DRV_GRF_OFFSET           0x200
 650
 651 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 652                                     int pin_num, struct regmap **regmap,
 653                                     int *reg, u8 *bit)
 654 {
 655         struct rockchip_pinctrl *info = bank->drvdata;
 656
 657         /* The first 32 pins of the first bank are located in PMU */
 658         if (bank->bank_num == 0) {
 659                 *regmap = info->regmap_pmu;
 660                 *reg = RK3368_DRV_PMU_OFFSET;
 661
 662                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 663                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 664                 *bit *= RK3288_DRV_BITS_PER_PIN;
 665         } else {
 666                 *regmap = info->regmap_base;
 667                 *reg = RK3368_DRV_GRF_OFFSET;
 668
 669                 /* correct the offset, as we're starting with the 2nd bank */
 670                 *reg -= 0x10;
 671                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 672                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 673
 674                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 675                 *bit *= RK3288_DRV_BITS_PER_PIN;
 676         }
 677 }
 678
 679 static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
 680
 681 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 682                                      int pin_num)
 683 {
 684         struct rockchip_pinctrl *info = bank->drvdata;
 685         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 686         struct regmap *regmap;
 687         int reg, ret;
 688         u32 data;
 689         u8 bit;
 690
 691         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 692
 693         ret = regmap_read(regmap, reg, &data);
 694         if (ret)
 695                 return ret;
 696
 697         data >>= bit;
 698         data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
 699
 700         return rockchip_perpin_drv_list[data];
 701 }
 702
 703 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 704                                      int pin_num, int strength)
 705 {
 706         struct rockchip_pinctrl *info = bank->drvdata;
 707         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 708         struct regmap *regmap;
 709         unsigned long flags;
 710         int reg, ret, i;
 711         u32 data, rmask;
 712         u8 bit;
 713
 714         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 715
 716         ret = -EINVAL;
 717         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
 718                 if (rockchip_perpin_drv_list[i] == strength) {
 719                         ret = i;
 720                         break;
 721                 }
 722         }
 723
 724         if (ret < 0) {
 725                 dev_err(info->dev, "unsupported driver strength %d\n",
 726                         strength);
 727                 return ret;
 728         }
 729
 730         spin_lock_irqsave(&bank->slock, flags);
 731
 732         /* enable the write to the equivalent lower bits */
 733         data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 734         rmask = data | (data >> 16);
 735         data |= (ret << bit);
 736
 737         ret = regmap_update_bits(regmap, reg, rmask, data);
 738         spin_unlock_irqrestore(&bank->slock, flags);
 739
 740         return ret;
 741 }
 742
 743 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 744 {
 745         struct rockchip_pinctrl *info = bank->drvdata;
 746         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 747         struct regmap *regmap;
 748         int reg, ret;
 749         u8 bit;
 750         u32 data;
 751
 752         /* rk3066b does support any pulls */
 753         if (ctrl->type == RK3066B)
 754                 return PIN_CONFIG_BIAS_DISABLE;
 755
 756         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 757
 758         ret = regmap_read(regmap, reg, &data);
 759         if (ret)
 760                 return ret;
 761
 762         switch (ctrl->type) {
 763         case RK2928:
 764                 return !(data & BIT(bit))
 765                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 766                                 : PIN_CONFIG_BIAS_DISABLE;
 767         case RK3188:
 768         case RK3288:
 769         case RK3368:
 770                 data >>= bit;
 771                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 772
 773                 switch (data) {
 774                 case 0:
 775                         return PIN_CONFIG_BIAS_DISABLE;
 776                 case 1:
 777                         return PIN_CONFIG_BIAS_PULL_UP;
 778                 case 2:
 779                         return PIN_CONFIG_BIAS_PULL_DOWN;
 780                 case 3:
 781                         return PIN_CONFIG_BIAS_BUS_HOLD;
 782                 }
 783
 784                 dev_err(info->dev, "unknown pull setting\n");
 785                 return -EIO;
 786         default:
 787                 dev_err(info->dev, "unsupported pinctrl type\n");
 788                 return -EINVAL;
 789         };
 790 }
 791
 792 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 793                                         int pin_num, int pull)
 794 {
 795         struct rockchip_pinctrl *info = bank->drvdata;
 796         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 797         struct regmap *regmap;
 798         int reg, ret;
 799         unsigned long flags;
 800         u8 bit;
 801         u32 data, rmask;
 802
 803         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 804                  bank->bank_num, pin_num, pull);
 805
 806         /* rk3066b does support any pulls */
 807         if (ctrl->type == RK3066B)
 808                 return pull ? -EINVAL : 0;
 809
 810         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 811
 812         switch (ctrl->type) {
 813         case RK2928:
 814                 spin_lock_irqsave(&bank->slock, flags);
 815
 816                 data = BIT(bit + 16);
 817                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 818                         data |= BIT(bit);
 819                 ret = regmap_write(regmap, reg, data);
 820
 821                 spin_unlock_irqrestore(&bank->slock, flags);
 822                 break;
 823         case RK3188:
 824         case RK3288:
 825         case RK3368:
 826                 spin_lock_irqsave(&bank->slock, flags);
 827
 828                 /* enable the write to the equivalent lower bits */
 829                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 830                 rmask = data | (data >> 16);
 831
 832                 switch (pull) {
 833                 case PIN_CONFIG_BIAS_DISABLE:
 834                         break;
 835                 case PIN_CONFIG_BIAS_PULL_UP:
 836                         data |= (1 << bit);
 837                         break;
 838                 case PIN_CONFIG_BIAS_PULL_DOWN:
 839                         data |= (2 << bit);
 840                         break;
 841                 case PIN_CONFIG_BIAS_BUS_HOLD:
 842                         data |= (3 << bit);
 843                         break;
 844                 default:
 845                         spin_unlock_irqrestore(&bank->slock, flags);
 846                         dev_err(info->dev, "unsupported pull setting %d\n",
 847                                 pull);
 848                         return -EINVAL;
 849                 }
 850
 851                 ret = regmap_update_bits(regmap, reg, rmask, data);
 852
 853                 spin_unlock_irqrestore(&bank->slock, flags);
 854                 break;
 855         default:
 856                 dev_err(info->dev, "unsupported pinctrl type\n");
 857                 return -EINVAL;
 858         }
 859
 860         return ret;
 861 }
 862
 863 /*
 864  * Pinmux_ops handling
 865  */
 866
 867 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 868 {
 869         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 870
 871         return info->nfunctions;
 872 }
 873
 874 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 875                                           unsigned selector)
 876 {
 877         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 878
 879         return info->functions[selector].name;
 880 }
 881
 882 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 883                                 unsigned selector, const char * const **groups,
 884                                 unsigned * const num_groups)
 885 {
 886         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 887
 888         *groups = info->functions[selector].groups;
 889         *num_groups = info->functions[selector].ngroups;
 890
 891         return 0;
 892 }
 893
 894 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 895                             unsigned group)
 896 {
 897         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 898         const unsigned int *pins = info->groups[group].pins;
 899         const struct rockchip_pin_config *data = info->groups[group].data;
 900         struct rockchip_pin_bank *bank;
 901         int cnt, ret = 0;
 902
 903         dev_dbg(info->dev, "enable function %s group %s\n",
 904                 info->functions[selector].name, info->groups[group].name);
 905
 906         /*
 907          * for each pin in the pin group selected, program the correspoding pin
 908          * pin function number in the config register.
 909          */
 910         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 911                 bank = pin_to_bank(info, pins[cnt]);
 912                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 913                                        data[cnt].func);
 914                 if (ret)
 915                         break;
 916         }
 917
 918         if (ret) {
 919                 /* revert the already done pin settings */
 920                 for (cnt--; cnt >= 0; cnt--)
 921                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 922
 923                 return ret;
 924         }
 925
 926         return 0;
 927 }
 928
 929 /*
 930  * The calls to gpio_direction_output() and gpio_direction_input()
 931  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 932  * function called from the gpiolib interface).
 933  */
 934 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
 935                                             int pin, bool input)
 936 {
 937         struct rockchip_pin_bank *bank;
 938         int ret;
 939         unsigned long flags;
 940         u32 data;
 941
 942         bank = gc_to_pin_bank(chip);
 943
 944         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 945         if (ret < 0)
 946                 return ret;
 947
 948         clk_enable(bank->clk);
 949         spin_lock_irqsave(&bank->slock, flags);
 950
 951         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 952         /* set bit to 1 for output, 0 for input */
 953         if (!input)
 954                 data |= BIT(pin);
 955         else
 956                 data &= ~BIT(pin);
 957         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 958
 959         spin_unlock_irqrestore(&bank->slock, flags);
 960         clk_disable(bank->clk);
 961
 962         return 0;
 963 }
 964
 965 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 966                                               struct pinctrl_gpio_range *range,
 967                                               unsigned offset, bool input)
 968 {
 969         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 970         struct gpio_chip *chip;
 971         int pin;
 972
 973         chip = range->gc;
 974         pin = offset - chip->base;
 975         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 976                  offset, range->name, pin, input ? "input" : "output");
 977
 978         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
 979                                                 input);
 980 }
 981
 982 static const struct pinmux_ops rockchip_pmx_ops = {
 983         .get_functions_count    = rockchip_pmx_get_funcs_count,
 984         .get_function_name      = rockchip_pmx_get_func_name,
 985         .get_function_groups    = rockchip_pmx_get_groups,
 986         .set_mux                = rockchip_pmx_set,
 987         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 988 };
 989
 990 /*
 991  * Pinconf_ops handling
 992  */
 993
 994 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 995                                         enum pin_config_param pull)
 996 {
 997         switch (ctrl->type) {
 998         case RK2928:
 999                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1000                                         pull == PIN_CONFIG_BIAS_DISABLE);
1001         case RK3066B:
1002                 return pull ? false : true;
1003         case RK3188:
1004         case RK3288:
1005         case RK3368:
1006                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1007         }
1008
1009         return false;
1010 }
1011
1012 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1013 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1014
1015 /* set the pin config settings for a specified pin */
1016 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1017                                 unsigned long *configs, unsigned num_configs)
1018 {
1019         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1020         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1021         enum pin_config_param param;
1022         u16 arg;
1023         int i;
1024         int rc;
1025
1026         for (i = 0; i < num_configs; i++) {
1027                 param = pinconf_to_config_param(configs[i]);
1028                 arg = pinconf_to_config_argument(configs[i]);
1029
1030                 switch (param) {
1031                 case PIN_CONFIG_BIAS_DISABLE:
1032                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1033                                 param);
1034                         if (rc)
1035                                 return rc;
1036                         break;
1037                 case PIN_CONFIG_BIAS_PULL_UP:
1038                 case PIN_CONFIG_BIAS_PULL_DOWN:
1039                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1040                 case PIN_CONFIG_BIAS_BUS_HOLD:
1041                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1042                                 return -ENOTSUPP;
1043
1044                         if (!arg)
1045                                 return -EINVAL;
1046
1047                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
1048                                 param);
1049                         if (rc)
1050                                 return rc;
1051                         break;
1052                 case PIN_CONFIG_OUTPUT:
1053                         rockchip_gpio_set(&bank->gpio_chip,
1054                                           pin - bank->pin_base, arg);
1055                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1056                                           pin - bank->pin_base, false);
1057                         if (rc)
1058                                 return rc;
1059                         break;
1060                 case PIN_CONFIG_DRIVE_STRENGTH:
1061                         /* rk3288 is the first with per-pin drive-strength */
1062                         if (!info->ctrl->drv_calc_reg)
1063                                 return -ENOTSUPP;
1064
1065                         rc = rockchip_set_drive_perpin(bank,
1066                                                 pin - bank->pin_base, arg);
1067                         if (rc < 0)
1068                                 return rc;
1069                         break;
1070                 default:
1071                         return -ENOTSUPP;
1072                         break;
1073                 }
1074         } /* for each config */
1075
1076         return 0;
1077 }
1078
1079 /* get the pin config settings for a specified pin */
1080 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1081                                                         unsigned long *config)
1082 {
1083         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1084         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1085         enum pin_config_param param = pinconf_to_config_param(*config);
1086         u16 arg;
1087         int rc;
1088
1089         switch (param) {
1090         case PIN_CONFIG_BIAS_DISABLE:
1091                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1092                         return -EINVAL;
1093
1094                 arg = 0;
1095                 break;
1096         case PIN_CONFIG_BIAS_PULL_UP:
1097         case PIN_CONFIG_BIAS_PULL_DOWN:
1098         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1099         case PIN_CONFIG_BIAS_BUS_HOLD:
1100                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1101                         return -ENOTSUPP;
1102
1103                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1104                         return -EINVAL;
1105
1106                 arg = 1;
1107                 break;
1108         case PIN_CONFIG_OUTPUT:
1109                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1110                 if (rc != RK_FUNC_GPIO)
1111                         return -EINVAL;
1112
1113                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1114                 if (rc < 0)
1115                         return rc;
1116
1117                 arg = rc ? 1 : 0;
1118                 break;
1119         case PIN_CONFIG_DRIVE_STRENGTH:
1120                 /* rk3288 is the first with per-pin drive-strength */
1121                 if (!info->ctrl->drv_calc_reg)
1122                         return -ENOTSUPP;
1123
1124                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1125                 if (rc < 0)
1126                         return rc;
1127
1128                 arg = rc;
1129                 break;
1130         default:
1131                 return -ENOTSUPP;
1132                 break;
1133         }
1134
1135         *config = pinconf_to_config_packed(param, arg);
1136
1137         return 0;
1138 }
1139
1140 static const struct pinconf_ops rockchip_pinconf_ops = {
1141         .pin_config_get                 = rockchip_pinconf_get,
1142         .pin_config_set                 = rockchip_pinconf_set,
1143         .is_generic                     = true,
1144 };
1145
1146 static const struct of_device_id rockchip_bank_match[] = {
1147         { .compatible = "rockchip,gpio-bank" },
1148         { .compatible = "rockchip,rk3188-gpio-bank0" },
1149         {},
1150 };
1151
1152 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1153                                                 struct device_node *np)
1154 {
1155         struct device_node *child;
1156
1157         for_each_child_of_node(np, child) {
1158                 if (of_match_node(rockchip_bank_match, child))
1159                         continue;
1160
1161                 info->nfunctions++;
1162                 info->ngroups += of_get_child_count(child);
1163         }
1164 }
1165
1166 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1167                                               struct rockchip_pin_group *grp,
1168                                               struct rockchip_pinctrl *info,
1169                                               u32 index)
1170 {
1171         struct rockchip_pin_bank *bank;
1172         int size;
1173         const __be32 *list;
1174         int num;
1175         int i, j;
1176         int ret;
1177
1178         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1179
1180         /* Initialise group */
1181         grp->name = np->name;
1182
1183         /*
1184          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1185          * do sanity check and calculate pins number
1186          */
1187         list = of_get_property(np, "rockchip,pins", &size);
1188         /* we do not check return since it's safe node passed down */
1189         size /= sizeof(*list);
1190         if (!size || size % 4) {
1191                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1192                 return -EINVAL;
1193         }
1194
1195         grp->npins = size / 4;
1196
1197         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1198                                                 GFP_KERNEL);
1199         grp->data = devm_kzalloc(info->dev, grp->npins *
1200                                           sizeof(struct rockchip_pin_config),
1201                                         GFP_KERNEL);
1202         if (!grp->pins || !grp->data)
1203                 return -ENOMEM;
1204
1205         for (i = 0, j = 0; i < size; i += 4, j++) {
1206                 const __be32 *phandle;
1207                 struct device_node *np_config;
1208
1209                 num = be32_to_cpu(*list++);
1210                 bank = bank_num_to_bank(info, num);
1211                 if (IS_ERR(bank))
1212                         return PTR_ERR(bank);
1213
1214                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1215                 grp->data[j].func = be32_to_cpu(*list++);
1216
1217                 phandle = list++;
1218                 if (!phandle)
1219                         return -EINVAL;
1220
1221                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1222                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1223                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1224                 if (ret)
1225                         return ret;
1226         }
1227
1228         return 0;
1229 }
1230
1231 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1232                                                 struct rockchip_pinctrl *info,
1233                                                 u32 index)
1234 {
1235         struct device_node *child;
1236         struct rockchip_pmx_func *func;
1237         struct rockchip_pin_group *grp;
1238         int ret;
1239         static u32 grp_index;
1240         u32 i = 0;
1241
1242         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1243
1244         func = &info->functions[index];
1245
1246         /* Initialise function */
1247         func->name = np->name;
1248         func->ngroups = of_get_child_count(np);
1249         if (func->ngroups <= 0)
1250                 return 0;
1251
1252         func->groups = devm_kzalloc(info->dev,
1253                         func->ngroups * sizeof(char *), GFP_KERNEL);
1254         if (!func->groups)
1255                 return -ENOMEM;
1256
1257         for_each_child_of_node(np, child) {
1258                 func->groups[i] = child->name;
1259                 grp = &info->groups[grp_index++];
1260                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1261                 if (ret)
1262                         return ret;
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1269                                               struct rockchip_pinctrl *info)
1270 {
1271         struct device *dev = &pdev->dev;
1272         struct device_node *np = dev->of_node;
1273         struct device_node *child;
1274         int ret;
1275         int i;
1276
1277         rockchip_pinctrl_child_count(info, np);
1278
1279         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1280         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1281
1282         info->functions = devm_kzalloc(dev, info->nfunctions *
1283                                               sizeof(struct rockchip_pmx_func),
1284                                               GFP_KERNEL);
1285         if (!info->functions) {
1286                 dev_err(dev, "failed to allocate memory for function list\n");
1287                 return -EINVAL;
1288         }
1289
1290         info->groups = devm_kzalloc(dev, info->ngroups *
1291                                             sizeof(struct rockchip_pin_group),
1292                                             GFP_KERNEL);
1293         if (!info->groups) {
1294                 dev_err(dev, "failed allocate memory for ping group list\n");
1295                 return -EINVAL;
1296         }
1297
1298         i = 0;
1299
1300         for_each_child_of_node(np, child) {
1301                 if (of_match_node(rockchip_bank_match, child))
1302                         continue;
1303
1304                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1305                 if (ret) {
1306                         dev_err(&pdev->dev, "failed to parse function\n");
1307                         return ret;
1308                 }
1309         }
1310
1311         return 0;
1312 }
1313
1314 static int rockchip_pinctrl_register(struct platform_device *pdev,
1315                                         struct rockchip_pinctrl *info)
1316 {
1317         struct pinctrl_desc *ctrldesc = &info->pctl;
1318         struct pinctrl_pin_desc *pindesc, *pdesc;
1319         struct rockchip_pin_bank *pin_bank;
1320         int pin, bank, ret;
1321         int k;
1322
1323         ctrldesc->name = "rockchip-pinctrl";
1324         ctrldesc->owner = THIS_MODULE;
1325         ctrldesc->pctlops = &rockchip_pctrl_ops;
1326         ctrldesc->pmxops = &rockchip_pmx_ops;
1327         ctrldesc->confops = &rockchip_pinconf_ops;
1328
1329         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1330                         info->ctrl->nr_pins, GFP_KERNEL);
1331         if (!pindesc) {
1332                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1333                 return -ENOMEM;
1334         }
1335         ctrldesc->pins = pindesc;
1336         ctrldesc->npins = info->ctrl->nr_pins;
1337
1338         pdesc = pindesc;
1339         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1340                 pin_bank = &info->ctrl->pin_banks[bank];
1341                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1342                         pdesc->number = k;
1343                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1344                                                 pin_bank->name, pin);
1345                         pdesc++;
1346                 }
1347         }
1348
1349         ret = rockchip_pinctrl_parse_dt(pdev, info);
1350         if (ret)
1351                 return ret;
1352
1353         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1354         if (IS_ERR(info->pctl_dev)) {
1355                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1356                 return PTR_ERR(info->pctl_dev);
1357         }
1358
1359         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1360                 pin_bank = &info->ctrl->pin_banks[bank];
1361                 pin_bank->grange.name = pin_bank->name;
1362                 pin_bank->grange.id = bank;
1363                 pin_bank->grange.pin_base = pin_bank->pin_base;
1364                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1365                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1366                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1367                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1368         }
1369
1370         return 0;
1371 }
1372
1373 /*
1374  * GPIO handling
1375  */
1376
1377 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1378 {
1379         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1380         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1381         unsigned long flags;
1382         u32 data;
1383
1384         clk_enable(bank->clk);
1385         spin_lock_irqsave(&bank->slock, flags);
1386
1387         data = readl(reg);
1388         data &= ~BIT(offset);
1389         if (value)
1390                 data |= BIT(offset);
1391         writel(data, reg);
1392
1393         spin_unlock_irqrestore(&bank->slock, flags);
1394         clk_disable(bank->clk);
1395 }
1396
1397 /*
1398  * Returns the level of the pin for input direction and setting of the DR
1399  * register for output gpios.
1400  */
1401 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1402 {
1403         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1404         u32 data;
1405
1406         clk_enable(bank->clk);
1407         data = readl(bank->reg_base + GPIO_EXT_PORT);
1408         clk_disable(bank->clk);
1409         data >>= offset;
1410         data &= 1;
1411         return data;
1412 }
1413
1414 /*
1415  * gpiolib gpio_direction_input callback function. The setting of the pin
1416  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1417  * interface.
1418  */
1419 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1420 {
1421         return pinctrl_gpio_direction_input(gc->base + offset);
1422 }
1423
1424 /*
1425  * gpiolib gpio_direction_output callback function. The setting of the pin
1426  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1427  * interface.
1428  */
1429 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1430                                           unsigned offset, int value)
1431 {
1432         rockchip_gpio_set(gc, offset, value);
1433         return pinctrl_gpio_direction_output(gc->base + offset);
1434 }
1435
1436 /*
1437  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1438  * and a virtual IRQ, if not already present.
1439  */
1440 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1441 {
1442         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1443         unsigned int virq;
1444
1445         if (!bank->domain)
1446                 return -ENXIO;
1447
1448         clk_enable(bank->clk);
1449         virq = irq_create_mapping(bank->domain, offset);
1450         clk_disable(bank->clk);
1451
1452         return (virq) ? : -ENXIO;
1453 }
1454
1455 static const struct gpio_chip rockchip_gpiolib_chip = {
1456         .request = gpiochip_generic_request,
1457         .free = gpiochip_generic_free,
1458         .set = rockchip_gpio_set,
1459         .get = rockchip_gpio_get,
1460         .direction_input = rockchip_gpio_direction_input,
1461         .direction_output = rockchip_gpio_direction_output,
1462         .to_irq = rockchip_gpio_to_irq,
1463         .owner = THIS_MODULE,
1464 };
1465
1466 /*
1467  * Interrupt handling
1468  */
1469
1470 static void rockchip_irq_demux(struct irq_desc *desc)
1471 {
1472         struct irq_chip *chip = irq_desc_get_chip(desc);
1473         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
1474         u32 pend;
1475
1476         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1477
1478         chained_irq_enter(chip, desc);
1479
1480         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1481
1482         while (pend) {
1483                 unsigned int irq, virq;
1484
1485                 irq = __ffs(pend);
1486                 pend &= ~BIT(irq);
1487                 virq = irq_linear_revmap(bank->domain, irq);
1488
1489                 if (!virq) {
1490                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1491                         continue;
1492                 }
1493
1494                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1495
1496                 /*
1497                  * Triggering IRQ on both rising and falling edge
1498                  * needs manual intervention.
1499                  */
1500                 if (bank->toggle_edge_mode & BIT(irq)) {
1501                         u32 data, data_old, polarity;
1502                         unsigned long flags;
1503
1504                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1505                         do {
1506                                 spin_lock_irqsave(&bank->slock, flags);
1507
1508                                 polarity = readl_relaxed(bank->reg_base +
1509                                                          GPIO_INT_POLARITY);
1510                                 if (data & BIT(irq))
1511                                         polarity &= ~BIT(irq);
1512                                 else
1513                                         polarity |= BIT(irq);
1514                                 writel(polarity,
1515                                        bank->reg_base + GPIO_INT_POLARITY);
1516
1517                                 spin_unlock_irqrestore(&bank->slock, flags);
1518
1519                                 data_old = data;
1520                                 data = readl_relaxed(bank->reg_base +
1521                                                      GPIO_EXT_PORT);
1522                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
1523                 }
1524
1525                 generic_handle_irq(virq);
1526         }
1527
1528         chained_irq_exit(chip, desc);
1529 }
1530
1531 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1532 {
1533         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1534         struct rockchip_pin_bank *bank = gc->private;
1535         u32 mask = BIT(d->hwirq);
1536         u32 polarity;
1537         u32 level;
1538         u32 data;
1539         unsigned long flags;
1540         int ret;
1541
1542         /* make sure the pin is configured as gpio input */
1543         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1544         if (ret < 0)
1545                 return ret;
1546
1547         clk_enable(bank->clk);
1548         spin_lock_irqsave(&bank->slock, flags);
1549
1550         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1551         data &= ~mask;
1552         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1553
1554         spin_unlock_irqrestore(&bank->slock, flags);
1555
1556         if (type & IRQ_TYPE_EDGE_BOTH)
1557                 irq_set_handler_locked(d, handle_edge_irq);
1558         else
1559                 irq_set_handler_locked(d, handle_level_irq);
1560
1561         spin_lock_irqsave(&bank->slock, flags);
1562         irq_gc_lock(gc);
1563
1564         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1565         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1566
1567         switch (type) {
1568         case IRQ_TYPE_EDGE_BOTH:
1569                 bank->toggle_edge_mode |= mask;
1570                 level |= mask;
1571
1572                 /*
1573                  * Determine gpio state. If 1 next interrupt should be falling
1574                  * otherwise rising.
1575                  */
1576                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1577                 if (data & mask)
1578                         polarity &= ~mask;
1579                 else
1580                         polarity |= mask;
1581                 break;
1582         case IRQ_TYPE_EDGE_RISING:
1583                 bank->toggle_edge_mode &= ~mask;
1584                 level |= mask;
1585                 polarity |= mask;
1586                 break;
1587         case IRQ_TYPE_EDGE_FALLING:
1588                 bank->toggle_edge_mode &= ~mask;
1589                 level |= mask;
1590                 polarity &= ~mask;
1591                 break;
1592         case IRQ_TYPE_LEVEL_HIGH:
1593                 bank->toggle_edge_mode &= ~mask;
1594                 level &= ~mask;
1595                 polarity |= mask;
1596                 break;
1597         case IRQ_TYPE_LEVEL_LOW:
1598                 bank->toggle_edge_mode &= ~mask;
1599                 level &= ~mask;
1600                 polarity &= ~mask;
1601                 break;
1602         default:
1603                 irq_gc_unlock(gc);
1604                 spin_unlock_irqrestore(&bank->slock, flags);
1605                 clk_disable(bank->clk);
1606                 return -EINVAL;
1607         }
1608
1609         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1610         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1611
1612         irq_gc_unlock(gc);
1613         spin_unlock_irqrestore(&bank->slock, flags);
1614         clk_disable(bank->clk);
1615
1616         return 0;
1617 }
1618
1619 static void rockchip_irq_suspend(struct irq_data *d)
1620 {
1621         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1622         struct rockchip_pin_bank *bank = gc->private;
1623
1624         clk_enable(bank->clk);
1625         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1626         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
1627         clk_disable(bank->clk);
1628 }
1629
1630 static void rockchip_irq_resume(struct irq_data *d)
1631 {
1632         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1633         struct rockchip_pin_bank *bank = gc->private;
1634
1635         clk_enable(bank->clk);
1636         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
1637         clk_disable(bank->clk);
1638 }
1639
1640 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
1641 {
1642         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1643         struct rockchip_pin_bank *bank = gc->private;
1644
1645         clk_enable(bank->clk);
1646         irq_gc_mask_clr_bit(d);
1647 }
1648
1649 void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
1650 {
1651         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1652         struct rockchip_pin_bank *bank = gc->private;
1653
1654         irq_gc_mask_set_bit(d);
1655         clk_disable(bank->clk);
1656 }
1657
1658 static int rockchip_interrupts_register(struct platform_device *pdev,
1659                                                 struct rockchip_pinctrl *info)
1660 {
1661         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1662         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1663         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1664         struct irq_chip_generic *gc;
1665         int ret;
1666         int i, j;
1667
1668         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1669                 if (!bank->valid) {
1670                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1671                                  bank->name);
1672                         continue;
1673                 }
1674
1675                 ret = clk_enable(bank->clk);
1676                 if (ret) {
1677                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
1678                                 bank->name);
1679                         continue;
1680                 }
1681
1682                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1683                                                 &irq_generic_chip_ops, NULL);
1684                 if (!bank->domain) {
1685                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1686                                  bank->name);
1687                         clk_disable(bank->clk);
1688                         continue;
1689                 }
1690
1691                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1692                                          "rockchip_gpio_irq", handle_level_irq,
1693                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1694                 if (ret) {
1695                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1696                                 bank->name);
1697                         irq_domain_remove(bank->domain);
1698                         clk_disable(bank->clk);
1699                         continue;
1700                 }
1701
1702                 /*
1703                  * Linux assumes that all interrupts start out disabled/masked.
1704                  * Our driver only uses the concept of masked and always keeps
1705                  * things enabled, so for us that's all masked and all enabled.
1706                  */
1707                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
1708                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
1709
1710                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1711                 gc->reg_base = bank->reg_base;
1712                 gc->private = bank;
1713                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
1714                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1715                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1716                 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
1717                 gc->chip_types[0].chip.irq_unmask =
1718                                                   rockchip_irq_gc_mask_clr_bit;
1719                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1720                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1721                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
1722                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1723                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
1724
1725                 irq_set_chained_handler_and_data(bank->irq,
1726                                                  rockchip_irq_demux, bank);
1727
1728                 /* map the gpio irqs here, when the clock is still running */
1729                 for (j = 0 ; j < 32 ; j++)
1730                         irq_create_mapping(bank->domain, j);
1731
1732                 clk_disable(bank->clk);
1733         }
1734
1735         return 0;
1736 }
1737
1738 static int rockchip_gpiolib_register(struct platform_device *pdev,
1739                                                 struct rockchip_pinctrl *info)
1740 {
1741         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1742         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1743         struct gpio_chip *gc;
1744         int ret;
1745         int i;
1746
1747         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1748                 if (!bank->valid) {
1749                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1750                                  bank->name);
1751                         continue;
1752                 }
1753
1754                 bank->gpio_chip = rockchip_gpiolib_chip;
1755
1756                 gc = &bank->gpio_chip;
1757                 gc->base = bank->pin_base;
1758                 gc->ngpio = bank->nr_pins;
1759                 gc->dev = &pdev->dev;
1760                 gc->of_node = bank->of_node;
1761                 gc->label = bank->name;
1762
1763                 ret = gpiochip_add(gc);
1764                 if (ret) {
1765                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1766                                                         gc->label, ret);
1767                         goto fail;
1768                 }
1769         }
1770
1771         rockchip_interrupts_register(pdev, info);
1772
1773         return 0;
1774
1775 fail:
1776         for (--i, --bank; i >= 0; --i, --bank) {
1777                 if (!bank->valid)
1778                         continue;
1779                 gpiochip_remove(&bank->gpio_chip);
1780         }
1781         return ret;
1782 }
1783
1784 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1785                                                 struct rockchip_pinctrl *info)
1786 {
1787         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1788         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1789         int i;
1790
1791         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1792                 if (!bank->valid)
1793                         continue;
1794                 gpiochip_remove(&bank->gpio_chip);
1795         }
1796
1797         return 0;
1798 }
1799
1800 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1801                                   struct rockchip_pinctrl *info)
1802 {
1803         struct resource res;
1804         void __iomem *base;
1805
1806         if (of_address_to_resource(bank->of_node, 0, &res)) {
1807                 dev_err(info->dev, "cannot find IO resource for bank\n");
1808                 return -ENOENT;
1809         }
1810
1811         bank->reg_base = devm_ioremap_resource(info->dev, &res);
1812         if (IS_ERR(bank->reg_base))
1813                 return PTR_ERR(bank->reg_base);
1814
1815         /*
1816          * special case, where parts of the pull setting-registers are
1817          * part of the PMU register space
1818          */
1819         if (of_device_is_compatible(bank->of_node,
1820                                     "rockchip,rk3188-gpio-bank0")) {
1821                 struct device_node *node;
1822
1823                 node = of_parse_phandle(bank->of_node->parent,
1824                                         "rockchip,pmu", 0);
1825                 if (!node) {
1826                         if (of_address_to_resource(bank->of_node, 1, &res)) {
1827                                 dev_err(info->dev, "cannot find IO resource for bank\n");
1828                                 return -ENOENT;
1829                         }
1830
1831                         base = devm_ioremap_resource(info->dev, &res);
1832                         if (IS_ERR(base))
1833                                 return PTR_ERR(base);
1834                         rockchip_regmap_config.max_register =
1835                                                     resource_size(&res) - 4;
1836                         rockchip_regmap_config.name =
1837                                             "rockchip,rk3188-gpio-bank0-pull";
1838                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1839                                                     base,
1840                                                     &rockchip_regmap_config);
1841                 }
1842                 of_node_put(node);
1843         }
1844
1845         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1846
1847         bank->clk = of_clk_get(bank->of_node, 0);
1848         if (IS_ERR(bank->clk))
1849                 return PTR_ERR(bank->clk);
1850
1851         return clk_prepare(bank->clk);
1852 }
1853
1854 static const struct of_device_id rockchip_pinctrl_dt_match[];
1855
1856 /* retrieve the soc specific data */
1857 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1858                                                 struct rockchip_pinctrl *d,
1859                                                 struct platform_device *pdev)
1860 {
1861         const struct of_device_id *match;
1862         struct device_node *node = pdev->dev.of_node;
1863         struct device_node *np;
1864         struct rockchip_pin_ctrl *ctrl;
1865         struct rockchip_pin_bank *bank;
1866         int grf_offs, pmu_offs, i, j;
1867
1868         match = of_match_node(rockchip_pinctrl_dt_match, node);
1869         ctrl = (struct rockchip_pin_ctrl *)match->data;
1870
1871         for_each_child_of_node(node, np) {
1872                 if (!of_find_property(np, "gpio-controller", NULL))
1873                         continue;
1874
1875                 bank = ctrl->pin_banks;
1876                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1877                         if (!strcmp(bank->name, np->name)) {
1878                                 bank->of_node = np;
1879
1880                                 if (!rockchip_get_bank_data(bank, d))
1881                                         bank->valid = true;
1882
1883                                 break;
1884                         }
1885                 }
1886         }
1887
1888         grf_offs = ctrl->grf_mux_offset;
1889         pmu_offs = ctrl->pmu_mux_offset;
1890         bank = ctrl->pin_banks;
1891         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1892                 int bank_pins = 0;
1893
1894                 spin_lock_init(&bank->slock);
1895                 bank->drvdata = d;
1896                 bank->pin_base = ctrl->nr_pins;
1897                 ctrl->nr_pins += bank->nr_pins;
1898
1899                 /* calculate iomux offsets */
1900                 for (j = 0; j < 4; j++) {
1901                         struct rockchip_iomux *iom = &bank->iomux[j];
1902                         int inc;
1903
1904                         if (bank_pins >= bank->nr_pins)
1905                                 break;
1906
1907                         /* preset offset value, set new start value */
1908                         if (iom->offset >= 0) {
1909                                 if (iom->type & IOMUX_SOURCE_PMU)
1910                                         pmu_offs = iom->offset;
1911                                 else
1912                                         grf_offs = iom->offset;
1913                         } else { /* set current offset */
1914                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1915                                                         pmu_offs : grf_offs;
1916                         }
1917
1918                         dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1919                                  i, j, iom->offset);
1920
1921                         /*
1922                          * Increase offset according to iomux width.
1923                          * 4bit iomux'es are spread over two registers.
1924                          */
1925                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1926                         if (iom->type & IOMUX_SOURCE_PMU)
1927                                 pmu_offs += inc;
1928                         else
1929                                 grf_offs += inc;
1930
1931                         bank_pins += 8;
1932                 }
1933         }
1934
1935         return ctrl;
1936 }
1937
1938 #define RK3288_GRF_GPIO6C_IOMUX         0x64
1939 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
1940
1941 static u32 rk3288_grf_gpio6c_iomux;
1942
1943 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
1944 {
1945         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
1946         int ret = pinctrl_force_sleep(info->pctl_dev);
1947
1948         if (ret)
1949                 return ret;
1950
1951         /*
1952          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
1953          * the setting here, and restore it at resume.
1954          */
1955         if (info->ctrl->type == RK3288) {
1956                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1957                                   &rk3288_grf_gpio6c_iomux);
1958                 if (ret) {
1959                         pinctrl_force_default(info->pctl_dev);
1960                         return ret;
1961                 }
1962         }
1963
1964         return 0;
1965 }
1966
1967 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
1968 {
1969         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
1970         int ret;
1971
1972         if (info->ctrl->type == RK3288) {
1973                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1974                                    rk3288_grf_gpio6c_iomux |
1975                                    GPIO6C6_SEL_WRITE_ENABLE);
1976                 if (ret)
1977                         return ret;
1978         }
1979
1980         return pinctrl_force_default(info->pctl_dev);
1981 }
1982
1983 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
1984                          rockchip_pinctrl_resume);
1985
1986 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1987 {
1988         struct rockchip_pinctrl *info;
1989         struct device *dev = &pdev->dev;
1990         struct rockchip_pin_ctrl *ctrl;
1991         struct device_node *np = pdev->dev.of_node, *node;
1992         struct resource *res;
1993         void __iomem *base;
1994         int ret;
1995
1996         if (!dev->of_node) {
1997                 dev_err(dev, "device tree node not found\n");
1998                 return -ENODEV;
1999         }
2000
2001         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2002         if (!info)
2003                 return -ENOMEM;
2004
2005         info->dev = dev;
2006
2007         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2008         if (!ctrl) {
2009                 dev_err(dev, "driver data not available\n");
2010                 return -EINVAL;
2011         }
2012         info->ctrl = ctrl;
2013
2014         node = of_parse_phandle(np, "rockchip,grf", 0);
2015         if (node) {
2016                 info->regmap_base = syscon_node_to_regmap(node);
2017                 if (IS_ERR(info->regmap_base))
2018                         return PTR_ERR(info->regmap_base);
2019         } else {
2020                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021                 base = devm_ioremap_resource(&pdev->dev, res);
2022                 if (IS_ERR(base))
2023                         return PTR_ERR(base);
2024
2025                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2026                 rockchip_regmap_config.name = "rockchip,pinctrl";
2027                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2028                                                     &rockchip_regmap_config);
2029
2030                 /* to check for the old dt-bindings */
2031                 info->reg_size = resource_size(res);
2032
2033                 /* Honor the old binding, with pull registers as 2nd resource */
2034                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2035                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2036                         base = devm_ioremap_resource(&pdev->dev, res);
2037                         if (IS_ERR(base))
2038                                 return PTR_ERR(base);
2039
2040                         rockchip_regmap_config.max_register =
2041                                                         resource_size(res) - 4;
2042                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2043                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2044                                                     base,
2045                                                     &rockchip_regmap_config);
2046                 }
2047         }
2048
2049         /* try to find the optional reference to the pmu syscon */
2050         node = of_parse_phandle(np, "rockchip,pmu", 0);
2051         if (node) {
2052                 info->regmap_pmu = syscon_node_to_regmap(node);
2053                 if (IS_ERR(info->regmap_pmu))
2054                         return PTR_ERR(info->regmap_pmu);
2055         }
2056
2057         ret = rockchip_gpiolib_register(pdev, info);
2058         if (ret)
2059                 return ret;
2060
2061         ret = rockchip_pinctrl_register(pdev, info);
2062         if (ret) {
2063                 rockchip_gpiolib_unregister(pdev, info);
2064                 return ret;
2065         }
2066
2067         platform_set_drvdata(pdev, info);
2068
2069         return 0;
2070 }
2071
2072 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2073         PIN_BANK(0, 32, "gpio0"),
2074         PIN_BANK(1, 32, "gpio1"),
2075         PIN_BANK(2, 32, "gpio2"),
2076         PIN_BANK(3, 32, "gpio3"),
2077 };
2078
2079 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2080                 .pin_banks              = rk2928_pin_banks,
2081                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2082                 .label                  = "RK2928-GPIO",
2083                 .type                   = RK2928,
2084                 .grf_mux_offset         = 0xa8,
2085                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2086 };
2087
2088 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2089         PIN_BANK(0, 32, "gpio0"),
2090         PIN_BANK(1, 32, "gpio1"),
2091         PIN_BANK(2, 32, "gpio2"),
2092 };
2093
2094 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2095                 .pin_banks              = rk3036_pin_banks,
2096                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2097                 .label                  = "RK3036-GPIO",
2098                 .type                   = RK2928,
2099                 .grf_mux_offset         = 0xa8,
2100                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2101 };
2102
2103 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2104         PIN_BANK(0, 32, "gpio0"),
2105         PIN_BANK(1, 32, "gpio1"),
2106         PIN_BANK(2, 32, "gpio2"),
2107         PIN_BANK(3, 32, "gpio3"),
2108         PIN_BANK(4, 32, "gpio4"),
2109         PIN_BANK(6, 16, "gpio6"),
2110 };
2111
2112 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2113                 .pin_banks              = rk3066a_pin_banks,
2114                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2115                 .label                  = "RK3066a-GPIO",
2116                 .type                   = RK2928,
2117                 .grf_mux_offset         = 0xa8,
2118                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2119 };
2120
2121 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2122         PIN_BANK(0, 32, "gpio0"),
2123         PIN_BANK(1, 32, "gpio1"),
2124         PIN_BANK(2, 32, "gpio2"),
2125         PIN_BANK(3, 32, "gpio3"),
2126 };
2127
2128 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2129                 .pin_banks      = rk3066b_pin_banks,
2130                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2131                 .label          = "RK3066b-GPIO",
2132                 .type           = RK3066B,
2133                 .grf_mux_offset = 0x60,
2134 };
2135
2136 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2137         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2138         PIN_BANK(1, 32, "gpio1"),
2139         PIN_BANK(2, 32, "gpio2"),
2140         PIN_BANK(3, 32, "gpio3"),
2141 };
2142
2143 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2144                 .pin_banks              = rk3188_pin_banks,
2145                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2146                 .label                  = "RK3188-GPIO",
2147                 .type                   = RK3188,
2148                 .grf_mux_offset         = 0x60,
2149                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2150 };
2151
2152 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2153         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2154                                              IOMUX_SOURCE_PMU,
2155                                              IOMUX_SOURCE_PMU,
2156                                              IOMUX_UNROUTED
2157                             ),
2158         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2159                                              IOMUX_UNROUTED,
2160                                              IOMUX_UNROUTED,
2161                                              0
2162                             ),
2163         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2164         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2165         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2166                                              IOMUX_WIDTH_4BIT,
2167                                              0,
2168                                              0
2169                             ),
2170         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2171                                              0,
2172                                              0,
2173                                              IOMUX_UNROUTED
2174                             ),
2175         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2176         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2177                                              0,
2178                                              IOMUX_WIDTH_4BIT,
2179                                              IOMUX_UNROUTED
2180                             ),
2181         PIN_BANK(8, 16, "gpio8"),
2182 };
2183
2184 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2185                 .pin_banks              = rk3288_pin_banks,
2186                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
2187                 .label                  = "RK3288-GPIO",
2188                 .type                   = RK3288,
2189                 .grf_mux_offset         = 0x0,
2190                 .pmu_mux_offset         = 0x84,
2191                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2192                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
2193 };
2194
2195 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2196         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2197                                              IOMUX_SOURCE_PMU,
2198                                              IOMUX_SOURCE_PMU,
2199                                              IOMUX_SOURCE_PMU
2200                             ),
2201         PIN_BANK(1, 32, "gpio1"),
2202         PIN_BANK(2, 32, "gpio2"),
2203         PIN_BANK(3, 32, "gpio3"),
2204 };
2205
2206 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2207                 .pin_banks              = rk3368_pin_banks,
2208                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
2209                 .label                  = "RK3368-GPIO",
2210                 .type                   = RK3368,
2211                 .grf_mux_offset         = 0x0,
2212                 .pmu_mux_offset         = 0x0,
2213                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
2214                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
2215 };
2216
2217
2218 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2219         { .compatible = "rockchip,rk2928-pinctrl",
2220                 .data = (void *)&rk2928_pin_ctrl },
2221         { .compatible = "rockchip,rk3036-pinctrl",
2222                 .data = (void *)&rk3036_pin_ctrl },
2223         { .compatible = "rockchip,rk3066a-pinctrl",
2224                 .data = (void *)&rk3066a_pin_ctrl },
2225         { .compatible = "rockchip,rk3066b-pinctrl",
2226                 .data = (void *)&rk3066b_pin_ctrl },
2227         { .compatible = "rockchip,rk3188-pinctrl",
2228                 .data = (void *)&rk3188_pin_ctrl },
2229         { .compatible = "rockchip,rk3288-pinctrl",
2230                 .data = (void *)&rk3288_pin_ctrl },
2231         { .compatible = "rockchip,rk3368-pinctrl",
2232                 .data = (void *)&rk3368_pin_ctrl },
2233         {},
2234 };
2235 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2236
2237 static struct platform_driver rockchip_pinctrl_driver = {
2238         .probe          = rockchip_pinctrl_probe,
2239         .driver = {
2240                 .name   = "rockchip-pinctrl",
2241                 .pm = &rockchip_pinctrl_dev_pm_ops,
2242                 .of_match_table = rockchip_pinctrl_dt_match,
2243         },
2244 };
2245
2246 static int __init rockchip_pinctrl_drv_register(void)
2247 {
2248         return platform_driver_register(&rockchip_pinctrl_driver);
2249 }
2250 postcore_initcall(rockchip_pinctrl_drv_register);
2251
2252 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2253 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2254 MODULE_LICENSE("GPL v2");