drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <heiko@sntech.de>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              http://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/io.h>
  21 #include <linux/bitops.h>
  22 #include <linux/gpio/driver.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pinctrl/machine.h>
  26 #include <linux/pinctrl/pinconf.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/clk.h>
  32 #include <linux/regmap.h>
  33 #include <linux/mfd/syscon.h>
  34 #include <dt-bindings/pinctrl/rockchip.h>
  35
  36 #include "core.h"
  37 #include "pinconf.h"
  38
  39 /* GPIO control registers */
  40 #define GPIO_SWPORT_DR          0x00
  41 #define GPIO_SWPORT_DDR         0x04
  42 #define GPIO_INTEN              0x30
  43 #define GPIO_INTMASK            0x34
  44 #define GPIO_INTTYPE_LEVEL      0x38
  45 #define GPIO_INT_POLARITY       0x3c
  46 #define GPIO_INT_STATUS         0x40
  47 #define GPIO_INT_RAWSTATUS      0x44
  48 #define GPIO_DEBOUNCE           0x48
  49 #define GPIO_PORTS_EOI          0x4c
  50 #define GPIO_EXT_PORT           0x50
  51 #define GPIO_LS_SYNC            0x60
  52
  53 enum rockchip_pinctrl_type {
  54         PX30,
  55         RV1108,
  56         RK2928,
  57         RK3066B,
  58         RK3128,
  59         RK3188,
  60         RK3288,
  61         RK3368,
  62         RK3399,
  63 };
  64
  65 /**
  66  * Encode variants of iomux registers into a type variable
  67  */
  68 #define IOMUX_GPIO_ONLY         BIT(0)
  69 #define IOMUX_WIDTH_4BIT        BIT(1)
  70 #define IOMUX_SOURCE_PMU        BIT(2)
  71 #define IOMUX_UNROUTED          BIT(3)
  72 #define IOMUX_WIDTH_3BIT        BIT(4)
  73
  74 /**
  75  * @type: iomux variant using IOMUX_* constants
  76  * @offset: if initialized to -1 it will be autocalculated, by specifying
  77  *          an initial offset value the relevant source offset can be reset
  78  *          to a new value for autocalculating the following iomux registers.
  79  */
  80 struct rockchip_iomux {
  81         int                             type;
  82         int                             offset;
  83 };
  84
  85 /**
  86  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  87  */
  88 enum rockchip_pin_drv_type {
  89         DRV_TYPE_IO_DEFAULT = 0,
  90         DRV_TYPE_IO_1V8_OR_3V0,
  91         DRV_TYPE_IO_1V8_ONLY,
  92         DRV_TYPE_IO_1V8_3V0_AUTO,
  93         DRV_TYPE_IO_3V3_ONLY,
  94         DRV_TYPE_MAX
  95 };
  96
  97 /**
  98  * enum type index corresponding to rockchip_pull_list arrays index.
  99  */
 100 enum rockchip_pin_pull_type {
 101         PULL_TYPE_IO_DEFAULT = 0,
 102         PULL_TYPE_IO_1V8_ONLY,
 103         PULL_TYPE_MAX
 104 };
 105
 106 /**
 107  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 108  * @offset: if initialized to -1 it will be autocalculated, by specifying
 109  *          an initial offset value the relevant source offset can be reset
 110  *          to a new value for autocalculating the following drive strength
 111  *          registers. if used chips own cal_drv func instead to calculate
 112  *          registers offset, the variant could be ignored.
 113  */
 114 struct rockchip_drv {
 115         enum rockchip_pin_drv_type      drv_type;
 116         int                             offset;
 117 };
 118
 119 /**
 120  * @reg_base: register base of the gpio bank
 121  * @reg_pull: optional separate register for additional pull settings
 122  * @clk: clock of the gpio bank
 123  * @irq: interrupt of the gpio bank
 124  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 125  * @pin_base: first pin number
 126  * @nr_pins: number of pins in this bank
 127  * @name: name of the bank
 128  * @bank_num: number of the bank, to account for holes
 129  * @iomux: array describing the 4 iomux sources of the bank
 130  * @drv: array describing the 4 drive strength sources of the bank
 131  * @pull_type: array describing the 4 pull type sources of the bank
 132  * @valid: is all necessary information present
 133  * @of_node: dt node of this bank
 134  * @drvdata: common pinctrl basedata
 135  * @domain: irqdomain of the gpio bank
 136  * @gpio_chip: gpiolib chip
 137  * @grange: gpio range
 138  * @slock: spinlock for the gpio bank
 139  * @route_mask: bits describing the routing pins of per bank
 140  */
 141 struct rockchip_pin_bank {
 142         void __iomem                    *reg_base;
 143         struct regmap                   *regmap_pull;
 144         struct clk                      *clk;
 145         int                             irq;
 146         u32                             saved_masks;
 147         u32                             pin_base;
 148         u8                              nr_pins;
 149         char                            *name;
 150         u8                              bank_num;
 151         struct rockchip_iomux           iomux[4];
 152         struct rockchip_drv             drv[4];
 153         enum rockchip_pin_pull_type     pull_type[4];
 154         bool                            valid;
 155         struct device_node              *of_node;
 156         struct rockchip_pinctrl         *drvdata;
 157         struct irq_domain               *domain;
 158         struct gpio_chip                gpio_chip;
 159         struct pinctrl_gpio_range       grange;
 160         raw_spinlock_t                  slock;
 161         u32                             toggle_edge_mode;
 162         u32                             recalced_mask;
 163         u32                             route_mask;
 164 };
 165
 166 #define PIN_BANK(id, pins, label)                       \
 167         {                                               \
 168                 .bank_num       = id,                   \
 169                 .nr_pins        = pins,                 \
 170                 .name           = label,                \
 171                 .iomux          = {                     \
 172                         { .offset = -1 },               \
 173                         { .offset = -1 },               \
 174                         { .offset = -1 },               \
 175                         { .offset = -1 },               \
 176                 },                                      \
 177         }
 178
 179 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 180         {                                                               \
 181                 .bank_num       = id,                                   \
 182                 .nr_pins        = pins,                                 \
 183                 .name           = label,                                \
 184                 .iomux          = {                                     \
 185                         { .type = iom0, .offset = -1 },                 \
 186                         { .type = iom1, .offset = -1 },                 \
 187                         { .type = iom2, .offset = -1 },                 \
 188                         { .type = iom3, .offset = -1 },                 \
 189                 },                                                      \
 190         }
 191
 192 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 193         {                                                               \
 194                 .bank_num       = id,                                   \
 195                 .nr_pins        = pins,                                 \
 196                 .name           = label,                                \
 197                 .iomux          = {                                     \
 198                         { .offset = -1 },                               \
 199                         { .offset = -1 },                               \
 200                         { .offset = -1 },                               \
 201                         { .offset = -1 },                               \
 202                 },                                                      \
 203                 .drv            = {                                     \
 204                         { .drv_type = type0, .offset = -1 },            \
 205                         { .drv_type = type1, .offset = -1 },            \
 206                         { .drv_type = type2, .offset = -1 },            \
 207                         { .drv_type = type3, .offset = -1 },            \
 208                 },                                                      \
 209         }
 210
 211 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 212                                       drv2, drv3, pull0, pull1,         \
 213                                       pull2, pull3)                     \
 214         {                                                               \
 215                 .bank_num       = id,                                   \
 216                 .nr_pins        = pins,                                 \
 217                 .name           = label,                                \
 218                 .iomux          = {                                     \
 219                         { .offset = -1 },                               \
 220                         { .offset = -1 },                               \
 221                         { .offset = -1 },                               \
 222                         { .offset = -1 },                               \
 223                 },                                                      \
 224                 .drv            = {                                     \
 225                         { .drv_type = drv0, .offset = -1 },             \
 226                         { .drv_type = drv1, .offset = -1 },             \
 227                         { .drv_type = drv2, .offset = -1 },             \
 228                         { .drv_type = drv3, .offset = -1 },             \
 229                 },                                                      \
 230                 .pull_type[0] = pull0,                                  \
 231                 .pull_type[1] = pull1,                                  \
 232                 .pull_type[2] = pull2,                                  \
 233                 .pull_type[3] = pull3,                                  \
 234         }
 235
 236 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 237                                         iom2, iom3, drv0, drv1, drv2,   \
 238                                         drv3, offset0, offset1,         \
 239                                         offset2, offset3)               \
 240         {                                                               \
 241                 .bank_num       = id,                                   \
 242                 .nr_pins        = pins,                                 \
 243                 .name           = label,                                \
 244                 .iomux          = {                                     \
 245                         { .type = iom0, .offset = -1 },                 \
 246                         { .type = iom1, .offset = -1 },                 \
 247                         { .type = iom2, .offset = -1 },                 \
 248                         { .type = iom3, .offset = -1 },                 \
 249                 },                                                      \
 250                 .drv            = {                                     \
 251                         { .drv_type = drv0, .offset = offset0 },        \
 252                         { .drv_type = drv1, .offset = offset1 },        \
 253                         { .drv_type = drv2, .offset = offset2 },        \
 254                         { .drv_type = drv3, .offset = offset3 },        \
 255                 },                                                      \
 256         }
 257
 258 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 259                                               label, iom0, iom1, iom2,  \
 260                                               iom3, drv0, drv1, drv2,   \
 261                                               drv3, offset0, offset1,   \
 262                                               offset2, offset3, pull0,  \
 263                                               pull1, pull2, pull3)      \
 264         {                                                               \
 265                 .bank_num       = id,                                   \
 266                 .nr_pins        = pins,                                 \
 267                 .name           = label,                                \
 268                 .iomux          = {                                     \
 269                         { .type = iom0, .offset = -1 },                 \
 270                         { .type = iom1, .offset = -1 },                 \
 271                         { .type = iom2, .offset = -1 },                 \
 272                         { .type = iom3, .offset = -1 },                 \
 273                 },                                                      \
 274                 .drv            = {                                     \
 275                         { .drv_type = drv0, .offset = offset0 },        \
 276                         { .drv_type = drv1, .offset = offset1 },        \
 277                         { .drv_type = drv2, .offset = offset2 },        \
 278                         { .drv_type = drv3, .offset = offset3 },        \
 279                 },                                                      \
 280                 .pull_type[0] = pull0,                                  \
 281                 .pull_type[1] = pull1,                                  \
 282                 .pull_type[2] = pull2,                                  \
 283                 .pull_type[3] = pull3,                                  \
 284         }
 285
 286 /**
 287  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 288  * @num: bank number.
 289  * @pin: pin number.
 290  * @bit: index at register.
 291  * @reg: register offset.
 292  * @mask: mask bit
 293  */
 294 struct rockchip_mux_recalced_data {
 295         u8 num;
 296         u8 pin;
 297         u32 reg;
 298         u8 bit;
 299         u8 mask;
 300 };
 301
 302 enum rockchip_mux_route_location {
 303         ROCKCHIP_ROUTE_SAME = 0,
 304         ROCKCHIP_ROUTE_PMU,
 305         ROCKCHIP_ROUTE_GRF,
 306 };
 307
 308 /**
 309  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 310  * @bank_num: bank number.
 311  * @pin: index at register or used to calc index.
 312  * @func: the min pin.
 313  * @route_offset: the max pin.
 314  * @route_val: the register offset.
 315  */
 316 struct rockchip_mux_route_data {
 317         u8 bank_num;
 318         u8 pin;
 319         u8 func;
 320         enum rockchip_mux_route_location route_location;
 321         u32 route_offset;
 322         u32 route_val;
 323 };
 324
 325 /**
 326  */
 327 struct rockchip_pin_ctrl {
 328         struct rockchip_pin_bank        *pin_banks;
 329         u32                             nr_banks;
 330         u32                             nr_pins;
 331         char                            *label;
 332         enum rockchip_pinctrl_type      type;
 333         int                             grf_mux_offset;
 334         int                             pmu_mux_offset;
 335         int                             grf_drv_offset;
 336         int                             pmu_drv_offset;
 337         struct rockchip_mux_recalced_data *iomux_recalced;
 338         u32                             niomux_recalced;
 339         struct rockchip_mux_route_data *iomux_routes;
 340         u32                             niomux_routes;
 341
 342         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 343                                     int pin_num, struct regmap **regmap,
 344                                     int *reg, u8 *bit);
 345         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 346                                     int pin_num, struct regmap **regmap,
 347                                     int *reg, u8 *bit);
 348         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 349                                     int pin_num, struct regmap **regmap,
 350                                     int *reg, u8 *bit);
 351 };
 352
 353 struct rockchip_pin_config {
 354         unsigned int            func;
 355         unsigned long           *configs;
 356         unsigned int            nconfigs;
 357 };
 358
 359 /**
 360  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 361  * @name: name of the pin group, used to lookup the group.
 362  * @pins: the pins included in this group.
 363  * @npins: number of pins included in this group.
 364  * @func: the mux function number to be programmed when selected.
 365  * @configs: the config values to be set for each pin
 366  * @nconfigs: number of configs for each pin
 367  */
 368 struct rockchip_pin_group {
 369         const char                      *name;
 370         unsigned int                    npins;
 371         unsigned int                    *pins;
 372         struct rockchip_pin_config      *data;
 373 };
 374
 375 /**
 376  * struct rockchip_pmx_func: represent a pin function.
 377  * @name: name of the pin function, used to lookup the function.
 378  * @groups: one or more names of pin groups that provide this function.
 379  * @num_groups: number of groups included in @groups.
 380  */
 381 struct rockchip_pmx_func {
 382         const char              *name;
 383         const char              **groups;
 384         u8                      ngroups;
 385 };
 386
 387 struct rockchip_pinctrl {
 388         struct regmap                   *regmap_base;
 389         int                             reg_size;
 390         struct regmap                   *regmap_pull;
 391         struct regmap                   *regmap_pmu;
 392         struct device                   *dev;
 393         struct rockchip_pin_ctrl        *ctrl;
 394         struct pinctrl_desc             pctl;
 395         struct pinctrl_dev              *pctl_dev;
 396         struct rockchip_pin_group       *groups;
 397         unsigned int                    ngroups;
 398         struct rockchip_pmx_func        *functions;
 399         unsigned int                    nfunctions;
 400 };
 401
 402 static struct regmap_config rockchip_regmap_config = {
 403         .reg_bits = 32,
 404         .val_bits = 32,
 405         .reg_stride = 4,
 406 };
 407
 408 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 409                                         const struct rockchip_pinctrl *info,
 410                                         const char *name)
 411 {
 412         int i;
 413
 414         for (i = 0; i < info->ngroups; i++) {
 415                 if (!strcmp(info->groups[i].name, name))
 416                         return &info->groups[i];
 417         }
 418
 419         return NULL;
 420 }
 421
 422 /*
 423  * given a pin number that is local to a pin controller, find out the pin bank
 424  * and the register base of the pin bank.
 425  */
 426 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 427                                                                 unsigned pin)
 428 {
 429         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 430
 431         while (pin >= (b->pin_base + b->nr_pins))
 432                 b++;
 433
 434         return b;
 435 }
 436
 437 static struct rockchip_pin_bank *bank_num_to_bank(
 438                                         struct rockchip_pinctrl *info,
 439                                         unsigned num)
 440 {
 441         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 442         int i;
 443
 444         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 445                 if (b->bank_num == num)
 446                         return b;
 447         }
 448
 449         return ERR_PTR(-EINVAL);
 450 }
 451
 452 /*
 453  * Pinctrl_ops handling
 454  */
 455
 456 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 457 {
 458         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 459
 460         return info->ngroups;
 461 }
 462
 463 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 464                                                         unsigned selector)
 465 {
 466         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 467
 468         return info->groups[selector].name;
 469 }
 470
 471 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 472                                       unsigned selector, const unsigned **pins,
 473                                       unsigned *npins)
 474 {
 475         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 476
 477         if (selector >= info->ngroups)
 478                 return -EINVAL;
 479
 480         *pins = info->groups[selector].pins;
 481         *npins = info->groups[selector].npins;
 482
 483         return 0;
 484 }
 485
 486 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 487                                  struct device_node *np,
 488                                  struct pinctrl_map **map, unsigned *num_maps)
 489 {
 490         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 491         const struct rockchip_pin_group *grp;
 492         struct pinctrl_map *new_map;
 493         struct device_node *parent;
 494         int map_num = 1;
 495         int i;
 496
 497         /*
 498          * first find the group of this node and check if we need to create
 499          * config maps for pins
 500          */
 501         grp = pinctrl_name_to_group(info, np->name);
 502         if (!grp) {
 503                 dev_err(info->dev, "unable to find group for node %pOFn\n",
 504                         np);
 505                 return -EINVAL;
 506         }
 507
 508         map_num += grp->npins;
 509
 510         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 511         if (!new_map)
 512                 return -ENOMEM;
 513
 514         *map = new_map;
 515         *num_maps = map_num;
 516
 517         /* create mux map */
 518         parent = of_get_parent(np);
 519         if (!parent) {
 520                 kfree(new_map);
 521                 return -EINVAL;
 522         }
 523         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 524         new_map[0].data.mux.function = parent->name;
 525         new_map[0].data.mux.group = np->name;
 526         of_node_put(parent);
 527
 528         /* create config map */
 529         new_map++;
 530         for (i = 0; i < grp->npins; i++) {
 531                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 532                 new_map[i].data.configs.group_or_pin =
 533                                 pin_get_name(pctldev, grp->pins[i]);
 534                 new_map[i].data.configs.configs = grp->data[i].configs;
 535                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 536         }
 537
 538         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 539                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 540
 541         return 0;
 542 }
 543
 544 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 545                                     struct pinctrl_map *map, unsigned num_maps)
 546 {
 547         kfree(map);
 548 }
 549
 550 static const struct pinctrl_ops rockchip_pctrl_ops = {
 551         .get_groups_count       = rockchip_get_groups_count,
 552         .get_group_name         = rockchip_get_group_name,
 553         .get_group_pins         = rockchip_get_group_pins,
 554         .dt_node_to_map         = rockchip_dt_node_to_map,
 555         .dt_free_map            = rockchip_dt_free_map,
 556 };
 557
 558 /*
 559  * Hardware access
 560  */
 561
 562 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 563         {
 564                 .num = 1,
 565                 .pin = 0,
 566                 .reg = 0x418,
 567                 .bit = 0,
 568                 .mask = 0x3
 569         }, {
 570                 .num = 1,
 571                 .pin = 1,
 572                 .reg = 0x418,
 573                 .bit = 2,
 574                 .mask = 0x3
 575         }, {
 576                 .num = 1,
 577                 .pin = 2,
 578                 .reg = 0x418,
 579                 .bit = 4,
 580                 .mask = 0x3
 581         }, {
 582                 .num = 1,
 583                 .pin = 3,
 584                 .reg = 0x418,
 585                 .bit = 6,
 586                 .mask = 0x3
 587         }, {
 588                 .num = 1,
 589                 .pin = 4,
 590                 .reg = 0x418,
 591                 .bit = 8,
 592                 .mask = 0x3
 593         }, {
 594                 .num = 1,
 595                 .pin = 5,
 596                 .reg = 0x418,
 597                 .bit = 10,
 598                 .mask = 0x3
 599         }, {
 600                 .num = 1,
 601                 .pin = 6,
 602                 .reg = 0x418,
 603                 .bit = 12,
 604                 .mask = 0x3
 605         }, {
 606                 .num = 1,
 607                 .pin = 7,
 608                 .reg = 0x418,
 609                 .bit = 14,
 610                 .mask = 0x3
 611         }, {
 612                 .num = 1,
 613                 .pin = 8,
 614                 .reg = 0x41c,
 615                 .bit = 0,
 616                 .mask = 0x3
 617         }, {
 618                 .num = 1,
 619                 .pin = 9,
 620                 .reg = 0x41c,
 621                 .bit = 2,
 622                 .mask = 0x3
 623         },
 624 };
 625
 626 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 627         {
 628                 .num = 2,
 629                 .pin = 20,
 630                 .reg = 0xe8,
 631                 .bit = 0,
 632                 .mask = 0x7
 633         }, {
 634                 .num = 2,
 635                 .pin = 21,
 636                 .reg = 0xe8,
 637                 .bit = 4,
 638                 .mask = 0x7
 639         }, {
 640                 .num = 2,
 641                 .pin = 22,
 642                 .reg = 0xe8,
 643                 .bit = 8,
 644                 .mask = 0x7
 645         }, {
 646                 .num = 2,
 647                 .pin = 23,
 648                 .reg = 0xe8,
 649                 .bit = 12,
 650                 .mask = 0x7
 651         }, {
 652                 .num = 2,
 653                 .pin = 24,
 654                 .reg = 0xd4,
 655                 .bit = 12,
 656                 .mask = 0x7
 657         },
 658 };
 659
 660 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 661         {
 662                 .num = 2,
 663                 .pin = 12,
 664                 .reg = 0x24,
 665                 .bit = 8,
 666                 .mask = 0x3
 667         }, {
 668                 .num = 2,
 669                 .pin = 15,
 670                 .reg = 0x28,
 671                 .bit = 0,
 672                 .mask = 0x7
 673         }, {
 674                 .num = 2,
 675                 .pin = 23,
 676                 .reg = 0x30,
 677                 .bit = 14,
 678                 .mask = 0x3
 679         },
 680 };
 681
 682 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 683                                       int *reg, u8 *bit, int *mask)
 684 {
 685         struct rockchip_pinctrl *info = bank->drvdata;
 686         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 687         struct rockchip_mux_recalced_data *data;
 688         int i;
 689
 690         for (i = 0; i < ctrl->niomux_recalced; i++) {
 691                 data = &ctrl->iomux_recalced[i];
 692                 if (data->num == bank->bank_num &&
 693                     data->pin == pin)
 694                         break;
 695         }
 696
 697         if (i >= ctrl->niomux_recalced)
 698                 return;
 699
 700         *reg = data->reg;
 701         *mask = data->mask;
 702         *bit = data->bit;
 703 }
 704
 705 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 706         {
 707                 /* cif-d2m0 */
 708                 .bank_num = 2,
 709                 .pin = 0,
 710                 .func = 1,
 711                 .route_offset = 0x184,
 712                 .route_val = BIT(16 + 7),
 713         }, {
 714                 /* cif-d2m1 */
 715                 .bank_num = 3,
 716                 .pin = 3,
 717                 .func = 3,
 718                 .route_offset = 0x184,
 719                 .route_val = BIT(16 + 7) | BIT(7),
 720         }, {
 721                 /* pdm-m0 */
 722                 .bank_num = 3,
 723                 .pin = 22,
 724                 .func = 2,
 725                 .route_offset = 0x184,
 726                 .route_val = BIT(16 + 8),
 727         }, {
 728                 /* pdm-m1 */
 729                 .bank_num = 2,
 730                 .pin = 22,
 731                 .func = 1,
 732                 .route_offset = 0x184,
 733                 .route_val = BIT(16 + 8) | BIT(8),
 734         }, {
 735                 /* uart2-rxm0 */
 736                 .bank_num = 1,
 737                 .pin = 27,
 738                 .func = 2,
 739                 .route_offset = 0x184,
 740                 .route_val = BIT(16 + 10),
 741         }, {
 742                 /* uart2-rxm1 */
 743                 .bank_num = 2,
 744                 .pin = 14,
 745                 .func = 2,
 746                 .route_offset = 0x184,
 747                 .route_val = BIT(16 + 10) | BIT(10),
 748         }, {
 749                 /* uart3-rxm0 */
 750                 .bank_num = 0,
 751                 .pin = 17,
 752                 .func = 2,
 753                 .route_offset = 0x184,
 754                 .route_val = BIT(16 + 9),
 755         }, {
 756                 /* uart3-rxm1 */
 757                 .bank_num = 1,
 758                 .pin = 15,
 759                 .func = 2,
 760                 .route_offset = 0x184,
 761                 .route_val = BIT(16 + 9) | BIT(9),
 762         },
 763 };
 764
 765 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 766         {
 767                 /* spi-0 */
 768                 .bank_num = 1,
 769                 .pin = 10,
 770                 .func = 1,
 771                 .route_offset = 0x144,
 772                 .route_val = BIT(16 + 3) | BIT(16 + 4),
 773         }, {
 774                 /* spi-1 */
 775                 .bank_num = 1,
 776                 .pin = 27,
 777                 .func = 3,
 778                 .route_offset = 0x144,
 779                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
 780         }, {
 781                 /* spi-2 */
 782                 .bank_num = 0,
 783                 .pin = 13,
 784                 .func = 2,
 785                 .route_offset = 0x144,
 786                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
 787         }, {
 788                 /* i2s-0 */
 789                 .bank_num = 1,
 790                 .pin = 5,
 791                 .func = 1,
 792                 .route_offset = 0x144,
 793                 .route_val = BIT(16 + 5),
 794         }, {
 795                 /* i2s-1 */
 796                 .bank_num = 0,
 797                 .pin = 14,
 798                 .func = 1,
 799                 .route_offset = 0x144,
 800                 .route_val = BIT(16 + 5) | BIT(5),
 801         }, {
 802                 /* emmc-0 */
 803                 .bank_num = 1,
 804                 .pin = 22,
 805                 .func = 2,
 806                 .route_offset = 0x144,
 807                 .route_val = BIT(16 + 6),
 808         }, {
 809                 /* emmc-1 */
 810                 .bank_num = 2,
 811                 .pin = 4,
 812                 .func = 2,
 813                 .route_offset = 0x144,
 814                 .route_val = BIT(16 + 6) | BIT(6),
 815         },
 816 };
 817
 818 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 819         {
 820                 /* non-iomuxed emmc/flash pins on flash-dqs */
 821                 .bank_num = 0,
 822                 .pin = 24,
 823                 .func = 1,
 824                 .route_location = ROCKCHIP_ROUTE_GRF,
 825                 .route_offset = 0xa0,
 826                 .route_val = BIT(16 + 11),
 827         }, {
 828                 /* non-iomuxed emmc/flash pins on emmc-clk */
 829                 .bank_num = 0,
 830                 .pin = 24,
 831                 .func = 2,
 832                 .route_location = ROCKCHIP_ROUTE_GRF,
 833                 .route_offset = 0xa0,
 834                 .route_val = BIT(16 + 11) | BIT(11),
 835         },
 836 };
 837
 838 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 839         {
 840                 /* pwm0-0 */
 841                 .bank_num = 0,
 842                 .pin = 26,
 843                 .func = 1,
 844                 .route_offset = 0x50,
 845                 .route_val = BIT(16),
 846         }, {
 847                 /* pwm0-1 */
 848                 .bank_num = 3,
 849                 .pin = 21,
 850                 .func = 1,
 851                 .route_offset = 0x50,
 852                 .route_val = BIT(16) | BIT(0),
 853         }, {
 854                 /* pwm1-0 */
 855                 .bank_num = 0,
 856                 .pin = 27,
 857                 .func = 1,
 858                 .route_offset = 0x50,
 859                 .route_val = BIT(16 + 1),
 860         }, {
 861                 /* pwm1-1 */
 862                 .bank_num = 0,
 863                 .pin = 30,
 864                 .func = 2,
 865                 .route_offset = 0x50,
 866                 .route_val = BIT(16 + 1) | BIT(1),
 867         }, {
 868                 /* pwm2-0 */
 869                 .bank_num = 0,
 870                 .pin = 28,
 871                 .func = 1,
 872                 .route_offset = 0x50,
 873                 .route_val = BIT(16 + 2),
 874         }, {
 875                 /* pwm2-1 */
 876                 .bank_num = 1,
 877                 .pin = 12,
 878                 .func = 2,
 879                 .route_offset = 0x50,
 880                 .route_val = BIT(16 + 2) | BIT(2),
 881         }, {
 882                 /* pwm3-0 */
 883                 .bank_num = 3,
 884                 .pin = 26,
 885                 .func = 1,
 886                 .route_offset = 0x50,
 887                 .route_val = BIT(16 + 3),
 888         }, {
 889                 /* pwm3-1 */
 890                 .bank_num = 1,
 891                 .pin = 11,
 892                 .func = 2,
 893                 .route_offset = 0x50,
 894                 .route_val = BIT(16 + 3) | BIT(3),
 895         }, {
 896                 /* sdio-0_d0 */
 897                 .bank_num = 1,
 898                 .pin = 1,
 899                 .func = 1,
 900                 .route_offset = 0x50,
 901                 .route_val = BIT(16 + 4),
 902         }, {
 903                 /* sdio-1_d0 */
 904                 .bank_num = 3,
 905                 .pin = 2,
 906                 .func = 1,
 907                 .route_offset = 0x50,
 908                 .route_val = BIT(16 + 4) | BIT(4),
 909         }, {
 910                 /* spi-0_rx */
 911                 .bank_num = 0,
 912                 .pin = 13,
 913                 .func = 2,
 914                 .route_offset = 0x50,
 915                 .route_val = BIT(16 + 5),
 916         }, {
 917                 /* spi-1_rx */
 918                 .bank_num = 2,
 919                 .pin = 0,
 920                 .func = 2,
 921                 .route_offset = 0x50,
 922                 .route_val = BIT(16 + 5) | BIT(5),
 923         }, {
 924                 /* emmc-0_cmd */
 925                 .bank_num = 1,
 926                 .pin = 22,
 927                 .func = 2,
 928                 .route_offset = 0x50,
 929                 .route_val = BIT(16 + 7),
 930         }, {
 931                 /* emmc-1_cmd */
 932                 .bank_num = 2,
 933                 .pin = 4,
 934                 .func = 2,
 935                 .route_offset = 0x50,
 936                 .route_val = BIT(16 + 7) | BIT(7),
 937         }, {
 938                 /* uart2-0_rx */
 939                 .bank_num = 1,
 940                 .pin = 19,
 941                 .func = 2,
 942                 .route_offset = 0x50,
 943                 .route_val = BIT(16 + 8),
 944         }, {
 945                 /* uart2-1_rx */
 946                 .bank_num = 1,
 947                 .pin = 10,
 948                 .func = 2,
 949                 .route_offset = 0x50,
 950                 .route_val = BIT(16 + 8) | BIT(8),
 951         }, {
 952                 /* uart1-0_rx */
 953                 .bank_num = 1,
 954                 .pin = 10,
 955                 .func = 1,
 956                 .route_offset = 0x50,
 957                 .route_val = BIT(16 + 11),
 958         }, {
 959                 /* uart1-1_rx */
 960                 .bank_num = 3,
 961                 .pin = 13,
 962                 .func = 1,
 963                 .route_offset = 0x50,
 964                 .route_val = BIT(16 + 11) | BIT(11),
 965         },
 966 };
 967
 968 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 969         {
 970                 /* edphdmi_cecinoutt1 */
 971                 .bank_num = 7,
 972                 .pin = 16,
 973                 .func = 2,
 974                 .route_offset = 0x264,
 975                 .route_val = BIT(16 + 12) | BIT(12),
 976         }, {
 977                 /* edphdmi_cecinout */
 978                 .bank_num = 7,
 979                 .pin = 23,
 980                 .func = 4,
 981                 .route_offset = 0x264,
 982                 .route_val = BIT(16 + 12),
 983         },
 984 };
 985
 986 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 987         {
 988                 /* uart2dbg_rxm0 */
 989                 .bank_num = 1,
 990                 .pin = 1,
 991                 .func = 2,
 992                 .route_offset = 0x50,
 993                 .route_val = BIT(16) | BIT(16 + 1),
 994         }, {
 995                 /* uart2dbg_rxm1 */
 996                 .bank_num = 2,
 997                 .pin = 1,
 998                 .func = 1,
 999                 .route_offset = 0x50,
1000                 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1001         }, {
1002                 /* gmac-m1_rxd0 */
1003                 .bank_num = 1,
1004                 .pin = 11,
1005                 .func = 2,
1006                 .route_offset = 0x50,
1007                 .route_val = BIT(16 + 2) | BIT(2),
1008         }, {
1009                 /* gmac-m1-optimized_rxd3 */
1010                 .bank_num = 1,
1011                 .pin = 14,
1012                 .func = 2,
1013                 .route_offset = 0x50,
1014                 .route_val = BIT(16 + 10) | BIT(10),
1015         }, {
1016                 /* pdm_sdi0m0 */
1017                 .bank_num = 2,
1018                 .pin = 19,
1019                 .func = 2,
1020                 .route_offset = 0x50,
1021                 .route_val = BIT(16 + 3),
1022         }, {
1023                 /* pdm_sdi0m1 */
1024                 .bank_num = 1,
1025                 .pin = 23,
1026                 .func = 3,
1027                 .route_offset = 0x50,
1028                 .route_val =  BIT(16 + 3) | BIT(3),
1029         }, {
1030                 /* spi_rxdm2 */
1031                 .bank_num = 3,
1032                 .pin = 2,
1033                 .func = 4,
1034                 .route_offset = 0x50,
1035                 .route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1036         }, {
1037                 /* i2s2_sdim0 */
1038                 .bank_num = 1,
1039                 .pin = 24,
1040                 .func = 1,
1041                 .route_offset = 0x50,
1042                 .route_val = BIT(16 + 6),
1043         }, {
1044                 /* i2s2_sdim1 */
1045                 .bank_num = 3,
1046                 .pin = 2,
1047                 .func = 6,
1048                 .route_offset = 0x50,
1049                 .route_val =  BIT(16 + 6) | BIT(6),
1050         }, {
1051                 /* card_iom1 */
1052                 .bank_num = 2,
1053                 .pin = 22,
1054                 .func = 3,
1055                 .route_offset = 0x50,
1056                 .route_val =  BIT(16 + 7) | BIT(7),
1057         }, {
1058                 /* tsp_d5m1 */
1059                 .bank_num = 2,
1060                 .pin = 16,
1061                 .func = 3,
1062                 .route_offset = 0x50,
1063                 .route_val =  BIT(16 + 8) | BIT(8),
1064         }, {
1065                 /* cif_data5m1 */
1066                 .bank_num = 2,
1067                 .pin = 16,
1068                 .func = 4,
1069                 .route_offset = 0x50,
1070                 .route_val =  BIT(16 + 9) | BIT(9),
1071         },
1072 };
1073
1074 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1075         {
1076                 /* uart2dbga_rx */
1077                 .bank_num = 4,
1078                 .pin = 8,
1079                 .func = 2,
1080                 .route_offset = 0xe21c,
1081                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1082         }, {
1083                 /* uart2dbgb_rx */
1084                 .bank_num = 4,
1085                 .pin = 16,
1086                 .func = 2,
1087                 .route_offset = 0xe21c,
1088                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1089         }, {
1090                 /* uart2dbgc_rx */
1091                 .bank_num = 4,
1092                 .pin = 19,
1093                 .func = 1,
1094                 .route_offset = 0xe21c,
1095                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1096         }, {
1097                 /* pcie_clkreqn */
1098                 .bank_num = 2,
1099                 .pin = 26,
1100                 .func = 2,
1101                 .route_offset = 0xe21c,
1102                 .route_val = BIT(16 + 14),
1103         }, {
1104                 /* pcie_clkreqnb */
1105                 .bank_num = 4,
1106                 .pin = 24,
1107                 .func = 1,
1108                 .route_offset = 0xe21c,
1109                 .route_val = BIT(16 + 14) | BIT(14),
1110         },
1111 };
1112
1113 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1114                                    int mux, u32 *loc, u32 *reg, u32 *value)
1115 {
1116         struct rockchip_pinctrl *info = bank->drvdata;
1117         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1118         struct rockchip_mux_route_data *data;
1119         int i;
1120
1121         for (i = 0; i < ctrl->niomux_routes; i++) {
1122                 data = &ctrl->iomux_routes[i];
1123                 if ((data->bank_num == bank->bank_num) &&
1124                     (data->pin == pin) && (data->func == mux))
1125                         break;
1126         }
1127
1128         if (i >= ctrl->niomux_routes)
1129                 return false;
1130
1131         *loc = data->route_location;
1132         *reg = data->route_offset;
1133         *value = data->route_val;
1134
1135         return true;
1136 }
1137
1138 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1139 {
1140         struct rockchip_pinctrl *info = bank->drvdata;
1141         int iomux_num = (pin / 8);
1142         struct regmap *regmap;
1143         unsigned int val;
1144         int reg, ret, mask, mux_type;
1145         u8 bit;
1146
1147         if (iomux_num > 3)
1148                 return -EINVAL;
1149
1150         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1151                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1152                 return -EINVAL;
1153         }
1154
1155         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1156                 return RK_FUNC_GPIO;
1157
1158         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1159                                 ? info->regmap_pmu : info->regmap_base;
1160
1161         /* get basic quadrupel of mux registers and the correct reg inside */
1162         mux_type = bank->iomux[iomux_num].type;
1163         reg = bank->iomux[iomux_num].offset;
1164         if (mux_type & IOMUX_WIDTH_4BIT) {
1165                 if ((pin % 8) >= 4)
1166                         reg += 0x4;
1167                 bit = (pin % 4) * 4;
1168                 mask = 0xf;
1169         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1170                 if ((pin % 8) >= 5)
1171                         reg += 0x4;
1172                 bit = (pin % 8 % 5) * 3;
1173                 mask = 0x7;
1174         } else {
1175                 bit = (pin % 8) * 2;
1176                 mask = 0x3;
1177         }
1178
1179         if (bank->recalced_mask & BIT(pin))
1180                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1181
1182         ret = regmap_read(regmap, reg, &val);
1183         if (ret)
1184                 return ret;
1185
1186         return ((val >> bit) & mask);
1187 }
1188
1189 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1190                                int pin, int mux)
1191 {
1192         struct rockchip_pinctrl *info = bank->drvdata;
1193         int iomux_num = (pin / 8);
1194
1195         if (iomux_num > 3)
1196                 return -EINVAL;
1197
1198         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1199                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1200                 return -EINVAL;
1201         }
1202
1203         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1204                 if (mux != RK_FUNC_GPIO) {
1205                         dev_err(info->dev,
1206                                 "pin %d only supports a gpio mux\n", pin);
1207                         return -ENOTSUPP;
1208                 }
1209         }
1210
1211         return 0;
1212 }
1213
1214 /*
1215  * Set a new mux function for a pin.
1216  *
1217  * The register is divided into the upper and lower 16 bit. When changing
1218  * a value, the previous register value is not read and changed. Instead
1219  * it seems the changed bits are marked in the upper 16 bit, while the
1220  * changed value gets set in the same offset in the lower 16 bit.
1221  * All pin settings seem to be 2 bit wide in both the upper and lower
1222  * parts.
1223  * @bank: pin bank to change
1224  * @pin: pin to change
1225  * @mux: new mux function to set
1226  */
1227 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1228 {
1229         struct rockchip_pinctrl *info = bank->drvdata;
1230         int iomux_num = (pin / 8);
1231         struct regmap *regmap;
1232         int reg, ret, mask, mux_type;
1233         u8 bit;
1234         u32 data, rmask, route_location, route_reg, route_val;
1235
1236         ret = rockchip_verify_mux(bank, pin, mux);
1237         if (ret < 0)
1238                 return ret;
1239
1240         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1241                 return 0;
1242
1243         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1244                                                 bank->bank_num, pin, mux);
1245
1246         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1247                                 ? info->regmap_pmu : info->regmap_base;
1248
1249         /* get basic quadrupel of mux registers and the correct reg inside */
1250         mux_type = bank->iomux[iomux_num].type;
1251         reg = bank->iomux[iomux_num].offset;
1252         if (mux_type & IOMUX_WIDTH_4BIT) {
1253                 if ((pin % 8) >= 4)
1254                         reg += 0x4;
1255                 bit = (pin % 4) * 4;
1256                 mask = 0xf;
1257         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1258                 if ((pin % 8) >= 5)
1259                         reg += 0x4;
1260                 bit = (pin % 8 % 5) * 3;
1261                 mask = 0x7;
1262         } else {
1263                 bit = (pin % 8) * 2;
1264                 mask = 0x3;
1265         }
1266
1267         if (bank->recalced_mask & BIT(pin))
1268                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1269
1270         if (bank->route_mask & BIT(pin)) {
1271                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1272                                            &route_reg, &route_val)) {
1273                         struct regmap *route_regmap = regmap;
1274
1275                         /* handle special locations */
1276                         switch (route_location) {
1277                         case ROCKCHIP_ROUTE_PMU:
1278                                 route_regmap = info->regmap_pmu;
1279                                 break;
1280                         case ROCKCHIP_ROUTE_GRF:
1281                                 route_regmap = info->regmap_base;
1282                                 break;
1283                         }
1284
1285                         ret = regmap_write(route_regmap, route_reg, route_val);
1286                         if (ret)
1287                                 return ret;
1288                 }
1289         }
1290
1291         data = (mask << (bit + 16));
1292         rmask = data | (data >> 16);
1293         data |= (mux & mask) << bit;
1294         ret = regmap_update_bits(regmap, reg, rmask, data);
1295
1296         return ret;
1297 }
1298
1299 #define PX30_PULL_PMU_OFFSET            0x10
1300 #define PX30_PULL_GRF_OFFSET            0x60
1301 #define PX30_PULL_BITS_PER_PIN          2
1302 #define PX30_PULL_PINS_PER_REG          8
1303 #define PX30_PULL_BANK_STRIDE           16
1304
1305 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1306                                        int pin_num, struct regmap **regmap,
1307                                        int *reg, u8 *bit)
1308 {
1309         struct rockchip_pinctrl *info = bank->drvdata;
1310
1311         /* The first 32 pins of the first bank are located in PMU */
1312         if (bank->bank_num == 0) {
1313                 *regmap = info->regmap_pmu;
1314                 *reg = PX30_PULL_PMU_OFFSET;
1315         } else {
1316                 *regmap = info->regmap_base;
1317                 *reg = PX30_PULL_GRF_OFFSET;
1318
1319                 /* correct the offset, as we're starting with the 2nd bank */
1320                 *reg -= 0x10;
1321                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1322         }
1323
1324         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1325         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1326         *bit *= PX30_PULL_BITS_PER_PIN;
1327 }
1328
1329 #define PX30_DRV_PMU_OFFSET             0x20
1330 #define PX30_DRV_GRF_OFFSET             0xf0
1331 #define PX30_DRV_BITS_PER_PIN           2
1332 #define PX30_DRV_PINS_PER_REG           8
1333 #define PX30_DRV_BANK_STRIDE            16
1334
1335 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1336                                       int pin_num, struct regmap **regmap,
1337                                       int *reg, u8 *bit)
1338 {
1339         struct rockchip_pinctrl *info = bank->drvdata;
1340
1341         /* The first 32 pins of the first bank are located in PMU */
1342         if (bank->bank_num == 0) {
1343                 *regmap = info->regmap_pmu;
1344                 *reg = PX30_DRV_PMU_OFFSET;
1345         } else {
1346                 *regmap = info->regmap_base;
1347                 *reg = PX30_DRV_GRF_OFFSET;
1348
1349                 /* correct the offset, as we're starting with the 2nd bank */
1350                 *reg -= 0x10;
1351                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1352         }
1353
1354         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1355         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1356         *bit *= PX30_DRV_BITS_PER_PIN;
1357 }
1358
1359 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1360 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1361 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1362 #define PX30_SCHMITT_BANK_STRIDE                16
1363 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1364
1365 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1366                                          int pin_num,
1367                                          struct regmap **regmap,
1368                                          int *reg, u8 *bit)
1369 {
1370         struct rockchip_pinctrl *info = bank->drvdata;
1371         int pins_per_reg;
1372
1373         if (bank->bank_num == 0) {
1374                 *regmap = info->regmap_pmu;
1375                 *reg = PX30_SCHMITT_PMU_OFFSET;
1376                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1377         } else {
1378                 *regmap = info->regmap_base;
1379                 *reg = PX30_SCHMITT_GRF_OFFSET;
1380                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1381                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1382         }
1383
1384         *reg += ((pin_num / pins_per_reg) * 4);
1385         *bit = pin_num % pins_per_reg;
1386
1387         return 0;
1388 }
1389
1390 #define RV1108_PULL_PMU_OFFSET          0x10
1391 #define RV1108_PULL_OFFSET              0x110
1392 #define RV1108_PULL_PINS_PER_REG        8
1393 #define RV1108_PULL_BITS_PER_PIN        2
1394 #define RV1108_PULL_BANK_STRIDE         16
1395
1396 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1397                                          int pin_num, struct regmap **regmap,
1398                                          int *reg, u8 *bit)
1399 {
1400         struct rockchip_pinctrl *info = bank->drvdata;
1401
1402         /* The first 24 pins of the first bank are located in PMU */
1403         if (bank->bank_num == 0) {
1404                 *regmap = info->regmap_pmu;
1405                 *reg = RV1108_PULL_PMU_OFFSET;
1406         } else {
1407                 *reg = RV1108_PULL_OFFSET;
1408                 *regmap = info->regmap_base;
1409                 /* correct the offset, as we're starting with the 2nd bank */
1410                 *reg -= 0x10;
1411                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1412         }
1413
1414         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1415         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1416         *bit *= RV1108_PULL_BITS_PER_PIN;
1417 }
1418
1419 #define RV1108_DRV_PMU_OFFSET           0x20
1420 #define RV1108_DRV_GRF_OFFSET           0x210
1421 #define RV1108_DRV_BITS_PER_PIN         2
1422 #define RV1108_DRV_PINS_PER_REG         8
1423 #define RV1108_DRV_BANK_STRIDE          16
1424
1425 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1426                                         int pin_num, struct regmap **regmap,
1427                                         int *reg, u8 *bit)
1428 {
1429         struct rockchip_pinctrl *info = bank->drvdata;
1430
1431         /* The first 24 pins of the first bank are located in PMU */
1432         if (bank->bank_num == 0) {
1433                 *regmap = info->regmap_pmu;
1434                 *reg = RV1108_DRV_PMU_OFFSET;
1435         } else {
1436                 *regmap = info->regmap_base;
1437                 *reg = RV1108_DRV_GRF_OFFSET;
1438
1439                 /* correct the offset, as we're starting with the 2nd bank */
1440                 *reg -= 0x10;
1441                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1442         }
1443
1444         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1445         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1446         *bit *= RV1108_DRV_BITS_PER_PIN;
1447 }
1448
1449 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1450 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1451 #define RV1108_SCHMITT_BANK_STRIDE              8
1452 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1453 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1454
1455 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1456                                            int pin_num,
1457                                            struct regmap **regmap,
1458                                            int *reg, u8 *bit)
1459 {
1460         struct rockchip_pinctrl *info = bank->drvdata;
1461         int pins_per_reg;
1462
1463         if (bank->bank_num == 0) {
1464                 *regmap = info->regmap_pmu;
1465                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1466                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1467         } else {
1468                 *regmap = info->regmap_base;
1469                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1470                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1471                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1472         }
1473         *reg += ((pin_num / pins_per_reg) * 4);
1474         *bit = pin_num % pins_per_reg;
1475
1476         return 0;
1477 }
1478
1479 #define RK2928_PULL_OFFSET              0x118
1480 #define RK2928_PULL_PINS_PER_REG        16
1481 #define RK2928_PULL_BANK_STRIDE         8
1482
1483 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1484                                     int pin_num, struct regmap **regmap,
1485                                     int *reg, u8 *bit)
1486 {
1487         struct rockchip_pinctrl *info = bank->drvdata;
1488
1489         *regmap = info->regmap_base;
1490         *reg = RK2928_PULL_OFFSET;
1491         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1492         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1493
1494         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1495 };
1496
1497 #define RK3128_PULL_OFFSET      0x118
1498
1499 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1500                                          int pin_num, struct regmap **regmap,
1501                                          int *reg, u8 *bit)
1502 {
1503         struct rockchip_pinctrl *info = bank->drvdata;
1504
1505         *regmap = info->regmap_base;
1506         *reg = RK3128_PULL_OFFSET;
1507         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1508         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1509
1510         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1511 }
1512
1513 #define RK3188_PULL_OFFSET              0x164
1514 #define RK3188_PULL_BITS_PER_PIN        2
1515 #define RK3188_PULL_PINS_PER_REG        8
1516 #define RK3188_PULL_BANK_STRIDE         16
1517 #define RK3188_PULL_PMU_OFFSET          0x64
1518
1519 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1520                                     int pin_num, struct regmap **regmap,
1521                                     int *reg, u8 *bit)
1522 {
1523         struct rockchip_pinctrl *info = bank->drvdata;
1524
1525         /* The first 12 pins of the first bank are located elsewhere */
1526         if (bank->bank_num == 0 && pin_num < 12) {
1527                 *regmap = info->regmap_pmu ? info->regmap_pmu
1528                                            : bank->regmap_pull;
1529                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1530                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1531                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1532                 *bit *= RK3188_PULL_BITS_PER_PIN;
1533         } else {
1534                 *regmap = info->regmap_pull ? info->regmap_pull
1535                                             : info->regmap_base;
1536                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1537
1538                 /* correct the offset, as it is the 2nd pull register */
1539                 *reg -= 4;
1540                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1541                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1542
1543                 /*
1544                  * The bits in these registers have an inverse ordering
1545                  * with the lowest pin being in bits 15:14 and the highest
1546                  * pin in bits 1:0
1547                  */
1548                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1549                 *bit *= RK3188_PULL_BITS_PER_PIN;
1550         }
1551 }
1552
1553 #define RK3288_PULL_OFFSET              0x140
1554 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1555                                     int pin_num, struct regmap **regmap,
1556                                     int *reg, u8 *bit)
1557 {
1558         struct rockchip_pinctrl *info = bank->drvdata;
1559
1560         /* The first 24 pins of the first bank are located in PMU */
1561         if (bank->bank_num == 0) {
1562                 *regmap = info->regmap_pmu;
1563                 *reg = RK3188_PULL_PMU_OFFSET;
1564
1565                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1566                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1567                 *bit *= RK3188_PULL_BITS_PER_PIN;
1568         } else {
1569                 *regmap = info->regmap_base;
1570                 *reg = RK3288_PULL_OFFSET;
1571
1572                 /* correct the offset, as we're starting with the 2nd bank */
1573                 *reg -= 0x10;
1574                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1575                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1576
1577                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1578                 *bit *= RK3188_PULL_BITS_PER_PIN;
1579         }
1580 }
1581
1582 #define RK3288_DRV_PMU_OFFSET           0x70
1583 #define RK3288_DRV_GRF_OFFSET           0x1c0
1584 #define RK3288_DRV_BITS_PER_PIN         2
1585 #define RK3288_DRV_PINS_PER_REG         8
1586 #define RK3288_DRV_BANK_STRIDE          16
1587
1588 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1589                                     int pin_num, struct regmap **regmap,
1590                                     int *reg, u8 *bit)
1591 {
1592         struct rockchip_pinctrl *info = bank->drvdata;
1593
1594         /* The first 24 pins of the first bank are located in PMU */
1595         if (bank->bank_num == 0) {
1596                 *regmap = info->regmap_pmu;
1597                 *reg = RK3288_DRV_PMU_OFFSET;
1598
1599                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1600                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1601                 *bit *= RK3288_DRV_BITS_PER_PIN;
1602         } else {
1603                 *regmap = info->regmap_base;
1604                 *reg = RK3288_DRV_GRF_OFFSET;
1605
1606                 /* correct the offset, as we're starting with the 2nd bank */
1607                 *reg -= 0x10;
1608                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1609                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1610
1611                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1612                 *bit *= RK3288_DRV_BITS_PER_PIN;
1613         }
1614 }
1615
1616 #define RK3228_PULL_OFFSET              0x100
1617
1618 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1619                                     int pin_num, struct regmap **regmap,
1620                                     int *reg, u8 *bit)
1621 {
1622         struct rockchip_pinctrl *info = bank->drvdata;
1623
1624         *regmap = info->regmap_base;
1625         *reg = RK3228_PULL_OFFSET;
1626         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1627         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1628
1629         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1630         *bit *= RK3188_PULL_BITS_PER_PIN;
1631 }
1632
1633 #define RK3228_DRV_GRF_OFFSET           0x200
1634
1635 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1636                                     int pin_num, struct regmap **regmap,
1637                                     int *reg, u8 *bit)
1638 {
1639         struct rockchip_pinctrl *info = bank->drvdata;
1640
1641         *regmap = info->regmap_base;
1642         *reg = RK3228_DRV_GRF_OFFSET;
1643         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1644         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1645
1646         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1647         *bit *= RK3288_DRV_BITS_PER_PIN;
1648 }
1649
1650 #define RK3368_PULL_GRF_OFFSET          0x100
1651 #define RK3368_PULL_PMU_OFFSET          0x10
1652
1653 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1654                                     int pin_num, struct regmap **regmap,
1655                                     int *reg, u8 *bit)
1656 {
1657         struct rockchip_pinctrl *info = bank->drvdata;
1658
1659         /* The first 32 pins of the first bank are located in PMU */
1660         if (bank->bank_num == 0) {
1661                 *regmap = info->regmap_pmu;
1662                 *reg = RK3368_PULL_PMU_OFFSET;
1663
1664                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1665                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1666                 *bit *= RK3188_PULL_BITS_PER_PIN;
1667         } else {
1668                 *regmap = info->regmap_base;
1669                 *reg = RK3368_PULL_GRF_OFFSET;
1670
1671                 /* correct the offset, as we're starting with the 2nd bank */
1672                 *reg -= 0x10;
1673                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1674                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1675
1676                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1677                 *bit *= RK3188_PULL_BITS_PER_PIN;
1678         }
1679 }
1680
1681 #define RK3368_DRV_PMU_OFFSET           0x20
1682 #define RK3368_DRV_GRF_OFFSET           0x200
1683
1684 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1685                                     int pin_num, struct regmap **regmap,
1686                                     int *reg, u8 *bit)
1687 {
1688         struct rockchip_pinctrl *info = bank->drvdata;
1689
1690         /* The first 32 pins of the first bank are located in PMU */
1691         if (bank->bank_num == 0) {
1692                 *regmap = info->regmap_pmu;
1693                 *reg = RK3368_DRV_PMU_OFFSET;
1694
1695                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1696                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1697                 *bit *= RK3288_DRV_BITS_PER_PIN;
1698         } else {
1699                 *regmap = info->regmap_base;
1700                 *reg = RK3368_DRV_GRF_OFFSET;
1701
1702                 /* correct the offset, as we're starting with the 2nd bank */
1703                 *reg -= 0x10;
1704                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1705                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1706
1707                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1708                 *bit *= RK3288_DRV_BITS_PER_PIN;
1709         }
1710 }
1711
1712 #define RK3399_PULL_GRF_OFFSET          0xe040
1713 #define RK3399_PULL_PMU_OFFSET          0x40
1714 #define RK3399_DRV_3BITS_PER_PIN        3
1715
1716 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1717                                          int pin_num, struct regmap **regmap,
1718                                          int *reg, u8 *bit)
1719 {
1720         struct rockchip_pinctrl *info = bank->drvdata;
1721
1722         /* The bank0:16 and bank1:32 pins are located in PMU */
1723         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1724                 *regmap = info->regmap_pmu;
1725                 *reg = RK3399_PULL_PMU_OFFSET;
1726
1727                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1728
1729                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1730                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1731                 *bit *= RK3188_PULL_BITS_PER_PIN;
1732         } else {
1733                 *regmap = info->regmap_base;
1734                 *reg = RK3399_PULL_GRF_OFFSET;
1735
1736                 /* correct the offset, as we're starting with the 3rd bank */
1737                 *reg -= 0x20;
1738                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1739                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1740
1741                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1742                 *bit *= RK3188_PULL_BITS_PER_PIN;
1743         }
1744 }
1745
1746 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1747                                         int pin_num, struct regmap **regmap,
1748                                         int *reg, u8 *bit)
1749 {
1750         struct rockchip_pinctrl *info = bank->drvdata;
1751         int drv_num = (pin_num / 8);
1752
1753         /*  The bank0:16 and bank1:32 pins are located in PMU */
1754         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1755                 *regmap = info->regmap_pmu;
1756         else
1757                 *regmap = info->regmap_base;
1758
1759         *reg = bank->drv[drv_num].offset;
1760         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1761             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1762                 *bit = (pin_num % 8) * 3;
1763         else
1764                 *bit = (pin_num % 8) * 2;
1765 }
1766
1767 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1768         { 2, 4, 8, 12, -1, -1, -1, -1 },
1769         { 3, 6, 9, 12, -1, -1, -1, -1 },
1770         { 5, 10, 15, 20, -1, -1, -1, -1 },
1771         { 4, 6, 8, 10, 12, 14, 16, 18 },
1772         { 4, 7, 10, 13, 16, 19, 22, 26 }
1773 };
1774
1775 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1776                                      int pin_num)
1777 {
1778         struct rockchip_pinctrl *info = bank->drvdata;
1779         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1780         struct regmap *regmap;
1781         int reg, ret;
1782         u32 data, temp, rmask_bits;
1783         u8 bit;
1784         int drv_type = bank->drv[pin_num / 8].drv_type;
1785
1786         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1787
1788         switch (drv_type) {
1789         case DRV_TYPE_IO_1V8_3V0_AUTO:
1790         case DRV_TYPE_IO_3V3_ONLY:
1791                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1792                 switch (bit) {
1793                 case 0 ... 12:
1794                         /* regular case, nothing to do */
1795                         break;
1796                 case 15:
1797                         /*
1798                          * drive-strength offset is special, as it is
1799                          * spread over 2 registers
1800                          */
1801                         ret = regmap_read(regmap, reg, &data);
1802                         if (ret)
1803                                 return ret;
1804
1805                         ret = regmap_read(regmap, reg + 0x4, &temp);
1806                         if (ret)
1807                                 return ret;
1808
1809                         /*
1810                          * the bit data[15] contains bit 0 of the value
1811                          * while temp[1:0] contains bits 2 and 1
1812                          */
1813                         data >>= 15;
1814                         temp &= 0x3;
1815                         temp <<= 1;
1816                         data |= temp;
1817
1818                         return rockchip_perpin_drv_list[drv_type][data];
1819                 case 18 ... 21:
1820                         /* setting fully enclosed in the second register */
1821                         reg += 4;
1822                         bit -= 16;
1823                         break;
1824                 default:
1825                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1826                                 bit, drv_type);
1827                         return -EINVAL;
1828                 }
1829
1830                 break;
1831         case DRV_TYPE_IO_DEFAULT:
1832         case DRV_TYPE_IO_1V8_OR_3V0:
1833         case DRV_TYPE_IO_1V8_ONLY:
1834                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1835                 break;
1836         default:
1837                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1838                         drv_type);
1839                 return -EINVAL;
1840         }
1841
1842         ret = regmap_read(regmap, reg, &data);
1843         if (ret)
1844                 return ret;
1845
1846         data >>= bit;
1847         data &= (1 << rmask_bits) - 1;
1848
1849         return rockchip_perpin_drv_list[drv_type][data];
1850 }
1851
1852 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1853                                      int pin_num, int strength)
1854 {
1855         struct rockchip_pinctrl *info = bank->drvdata;
1856         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1857         struct regmap *regmap;
1858         int reg, ret, i;
1859         u32 data, rmask, rmask_bits, temp;
1860         u8 bit;
1861         int drv_type = bank->drv[pin_num / 8].drv_type;
1862
1863         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1864                 bank->bank_num, pin_num, strength);
1865
1866         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1867
1868         ret = -EINVAL;
1869         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1870                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1871                         ret = i;
1872                         break;
1873                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1874                         ret = rockchip_perpin_drv_list[drv_type][i];
1875                         break;
1876                 }
1877         }
1878
1879         if (ret < 0) {
1880                 dev_err(info->dev, "unsupported driver strength %d\n",
1881                         strength);
1882                 return ret;
1883         }
1884
1885         switch (drv_type) {
1886         case DRV_TYPE_IO_1V8_3V0_AUTO:
1887         case DRV_TYPE_IO_3V3_ONLY:
1888                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1889                 switch (bit) {
1890                 case 0 ... 12:
1891                         /* regular case, nothing to do */
1892                         break;
1893                 case 15:
1894                         /*
1895                          * drive-strength offset is special, as it is spread
1896                          * over 2 registers, the bit data[15] contains bit 0
1897                          * of the value while temp[1:0] contains bits 2 and 1
1898                          */
1899                         data = (ret & 0x1) << 15;
1900                         temp = (ret >> 0x1) & 0x3;
1901
1902                         rmask = BIT(15) | BIT(31);
1903                         data |= BIT(31);
1904                         ret = regmap_update_bits(regmap, reg, rmask, data);
1905                         if (ret)
1906                                 return ret;
1907
1908                         rmask = 0x3 | (0x3 << 16);
1909                         temp |= (0x3 << 16);
1910                         reg += 0x4;
1911                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1912
1913                         return ret;
1914                 case 18 ... 21:
1915                         /* setting fully enclosed in the second register */
1916                         reg += 4;
1917                         bit -= 16;
1918                         break;
1919                 default:
1920                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1921                                 bit, drv_type);
1922                         return -EINVAL;
1923                 }
1924                 break;
1925         case DRV_TYPE_IO_DEFAULT:
1926         case DRV_TYPE_IO_1V8_OR_3V0:
1927         case DRV_TYPE_IO_1V8_ONLY:
1928                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1929                 break;
1930         default:
1931                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1932                         drv_type);
1933                 return -EINVAL;
1934         }
1935
1936         /* enable the write to the equivalent lower bits */
1937         data = ((1 << rmask_bits) - 1) << (bit + 16);
1938         rmask = data | (data >> 16);
1939         data |= (ret << bit);
1940
1941         ret = regmap_update_bits(regmap, reg, rmask, data);
1942
1943         return ret;
1944 }
1945
1946 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1947         {
1948                 PIN_CONFIG_BIAS_DISABLE,
1949                 PIN_CONFIG_BIAS_PULL_UP,
1950                 PIN_CONFIG_BIAS_PULL_DOWN,
1951                 PIN_CONFIG_BIAS_BUS_HOLD
1952         },
1953         {
1954                 PIN_CONFIG_BIAS_DISABLE,
1955                 PIN_CONFIG_BIAS_PULL_DOWN,
1956                 PIN_CONFIG_BIAS_DISABLE,
1957                 PIN_CONFIG_BIAS_PULL_UP
1958         },
1959 };
1960
1961 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1962 {
1963         struct rockchip_pinctrl *info = bank->drvdata;
1964         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1965         struct regmap *regmap;
1966         int reg, ret, pull_type;
1967         u8 bit;
1968         u32 data;
1969
1970         /* rk3066b does support any pulls */
1971         if (ctrl->type == RK3066B)
1972                 return PIN_CONFIG_BIAS_DISABLE;
1973
1974         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1975
1976         ret = regmap_read(regmap, reg, &data);
1977         if (ret)
1978                 return ret;
1979
1980         switch (ctrl->type) {
1981         case RK2928:
1982         case RK3128:
1983                 return !(data & BIT(bit))
1984                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1985                                 : PIN_CONFIG_BIAS_DISABLE;
1986         case PX30:
1987         case RV1108:
1988         case RK3188:
1989         case RK3288:
1990         case RK3368:
1991         case RK3399:
1992                 pull_type = bank->pull_type[pin_num / 8];
1993                 data >>= bit;
1994                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1995
1996                 return rockchip_pull_list[pull_type][data];
1997         default:
1998                 dev_err(info->dev, "unsupported pinctrl type\n");
1999                 return -EINVAL;
2000         };
2001 }
2002
2003 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2004                                         int pin_num, int pull)
2005 {
2006         struct rockchip_pinctrl *info = bank->drvdata;
2007         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2008         struct regmap *regmap;
2009         int reg, ret, i, pull_type;
2010         u8 bit;
2011         u32 data, rmask;
2012
2013         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2014                  bank->bank_num, pin_num, pull);
2015
2016         /* rk3066b does support any pulls */
2017         if (ctrl->type == RK3066B)
2018                 return pull ? -EINVAL : 0;
2019
2020         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2021
2022         switch (ctrl->type) {
2023         case RK2928:
2024         case RK3128:
2025                 data = BIT(bit + 16);
2026                 if (pull == PIN_CONFIG_BIAS_DISABLE)
2027                         data |= BIT(bit);
2028                 ret = regmap_write(regmap, reg, data);
2029                 break;
2030         case PX30:
2031         case RV1108:
2032         case RK3188:
2033         case RK3288:
2034         case RK3368:
2035         case RK3399:
2036                 pull_type = bank->pull_type[pin_num / 8];
2037                 ret = -EINVAL;
2038                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2039                         i++) {
2040                         if (rockchip_pull_list[pull_type][i] == pull) {
2041                                 ret = i;
2042                                 break;
2043                         }
2044                 }
2045
2046                 if (ret < 0) {
2047                         dev_err(info->dev, "unsupported pull setting %d\n",
2048                                 pull);
2049                         return ret;
2050                 }
2051
2052                 /* enable the write to the equivalent lower bits */
2053                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2054                 rmask = data | (data >> 16);
2055                 data |= (ret << bit);
2056
2057                 ret = regmap_update_bits(regmap, reg, rmask, data);
2058                 break;
2059         default:
2060                 dev_err(info->dev, "unsupported pinctrl type\n");
2061                 return -EINVAL;
2062         }
2063
2064         return ret;
2065 }
2066
2067 #define RK3328_SCHMITT_BITS_PER_PIN             1
2068 #define RK3328_SCHMITT_PINS_PER_REG             16
2069 #define RK3328_SCHMITT_BANK_STRIDE              8
2070 #define RK3328_SCHMITT_GRF_OFFSET               0x380
2071
2072 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2073                                            int pin_num,
2074                                            struct regmap **regmap,
2075                                            int *reg, u8 *bit)
2076 {
2077         struct rockchip_pinctrl *info = bank->drvdata;
2078
2079         *regmap = info->regmap_base;
2080         *reg = RK3328_SCHMITT_GRF_OFFSET;
2081
2082         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2083         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2084         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2085
2086         return 0;
2087 }
2088
2089 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2090 {
2091         struct rockchip_pinctrl *info = bank->drvdata;
2092         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2093         struct regmap *regmap;
2094         int reg, ret;
2095         u8 bit;
2096         u32 data;
2097
2098         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2099         if (ret)
2100                 return ret;
2101
2102         ret = regmap_read(regmap, reg, &data);
2103         if (ret)
2104                 return ret;
2105
2106         data >>= bit;
2107         return data & 0x1;
2108 }
2109
2110 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2111                                 int pin_num, int enable)
2112 {
2113         struct rockchip_pinctrl *info = bank->drvdata;
2114         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2115         struct regmap *regmap;
2116         int reg, ret;
2117         u8 bit;
2118         u32 data, rmask;
2119
2120         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2121                 bank->bank_num, pin_num, enable);
2122
2123         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2124         if (ret)
2125                 return ret;
2126
2127         /* enable the write to the equivalent lower bits */
2128         data = BIT(bit + 16) | (enable << bit);
2129         rmask = BIT(bit + 16) | BIT(bit);
2130
2131         return regmap_update_bits(regmap, reg, rmask, data);
2132 }
2133
2134 /*
2135  * Pinmux_ops handling
2136  */
2137
2138 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2139 {
2140         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2141
2142         return info->nfunctions;
2143 }
2144
2145 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2146                                           unsigned selector)
2147 {
2148         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2149
2150         return info->functions[selector].name;
2151 }
2152
2153 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2154                                 unsigned selector, const char * const **groups,
2155                                 unsigned * const num_groups)
2156 {
2157         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2158
2159         *groups = info->functions[selector].groups;
2160         *num_groups = info->functions[selector].ngroups;
2161
2162         return 0;
2163 }
2164
2165 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2166                             unsigned group)
2167 {
2168         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2169         const unsigned int *pins = info->groups[group].pins;
2170         const struct rockchip_pin_config *data = info->groups[group].data;
2171         struct rockchip_pin_bank *bank;
2172         int cnt, ret = 0;
2173
2174         dev_dbg(info->dev, "enable function %s group %s\n",
2175                 info->functions[selector].name, info->groups[group].name);
2176
2177         /*
2178          * for each pin in the pin group selected, program the corresponding
2179          * pin function number in the config register.
2180          */
2181         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2182                 bank = pin_to_bank(info, pins[cnt]);
2183                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2184                                        data[cnt].func);
2185                 if (ret)
2186                         break;
2187         }
2188
2189         if (ret) {
2190                 /* revert the already done pin settings */
2191                 for (cnt--; cnt >= 0; cnt--)
2192                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2193
2194                 return ret;
2195         }
2196
2197         return 0;
2198 }
2199
2200 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2201 {
2202         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2203         u32 data;
2204         int ret;
2205
2206         ret = clk_enable(bank->clk);
2207         if (ret < 0) {
2208                 dev_err(bank->drvdata->dev,
2209                         "failed to enable clock for bank %s\n", bank->name);
2210                 return ret;
2211         }
2212         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2213         clk_disable(bank->clk);
2214
2215         return !(data & BIT(offset));
2216 }
2217
2218 /*
2219  * The calls to gpio_direction_output() and gpio_direction_input()
2220  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2221  * function called from the gpiolib interface).
2222  */
2223 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2224                                             int pin, bool input)
2225 {
2226         struct rockchip_pin_bank *bank;
2227         int ret;
2228         unsigned long flags;
2229         u32 data;
2230
2231         bank = gpiochip_get_data(chip);
2232
2233         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2234         if (ret < 0)
2235                 return ret;
2236
2237         clk_enable(bank->clk);
2238         raw_spin_lock_irqsave(&bank->slock, flags);
2239
2240         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2241         /* set bit to 1 for output, 0 for input */
2242         if (!input)
2243                 data |= BIT(pin);
2244         else
2245                 data &= ~BIT(pin);
2246         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2247
2248         raw_spin_unlock_irqrestore(&bank->slock, flags);
2249         clk_disable(bank->clk);
2250
2251         return 0;
2252 }
2253
2254 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2255                                               struct pinctrl_gpio_range *range,
2256                                               unsigned offset, bool input)
2257 {
2258         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2259         struct gpio_chip *chip;
2260         int pin;
2261
2262         chip = range->gc;
2263         pin = offset - chip->base;
2264         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2265                  offset, range->name, pin, input ? "input" : "output");
2266
2267         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2268                                                 input);
2269 }
2270
2271 static const struct pinmux_ops rockchip_pmx_ops = {
2272         .get_functions_count    = rockchip_pmx_get_funcs_count,
2273         .get_function_name      = rockchip_pmx_get_func_name,
2274         .get_function_groups    = rockchip_pmx_get_groups,
2275         .set_mux                = rockchip_pmx_set,
2276         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2277 };
2278
2279 /*
2280  * Pinconf_ops handling
2281  */
2282
2283 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2284                                         enum pin_config_param pull)
2285 {
2286         switch (ctrl->type) {
2287         case RK2928:
2288         case RK3128:
2289                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2290                                         pull == PIN_CONFIG_BIAS_DISABLE);
2291         case RK3066B:
2292                 return pull ? false : true;
2293         case PX30:
2294         case RV1108:
2295         case RK3188:
2296         case RK3288:
2297         case RK3368:
2298         case RK3399:
2299                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2300         }
2301
2302         return false;
2303 }
2304
2305 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2306 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2307
2308 /* set the pin config settings for a specified pin */
2309 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2310                                 unsigned long *configs, unsigned num_configs)
2311 {
2312         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2313         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2314         enum pin_config_param param;
2315         u32 arg;
2316         int i;
2317         int rc;
2318
2319         for (i = 0; i < num_configs; i++) {
2320                 param = pinconf_to_config_param(configs[i]);
2321                 arg = pinconf_to_config_argument(configs[i]);
2322
2323                 switch (param) {
2324                 case PIN_CONFIG_BIAS_DISABLE:
2325                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2326                                 param);
2327                         if (rc)
2328                                 return rc;
2329                         break;
2330                 case PIN_CONFIG_BIAS_PULL_UP:
2331                 case PIN_CONFIG_BIAS_PULL_DOWN:
2332                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2333                 case PIN_CONFIG_BIAS_BUS_HOLD:
2334                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2335                                 return -ENOTSUPP;
2336
2337                         if (!arg)
2338                                 return -EINVAL;
2339
2340                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2341                                 param);
2342                         if (rc)
2343                                 return rc;
2344                         break;
2345                 case PIN_CONFIG_OUTPUT:
2346                         rockchip_gpio_set(&bank->gpio_chip,
2347                                           pin - bank->pin_base, arg);
2348                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2349                                           pin - bank->pin_base, false);
2350                         if (rc)
2351                                 return rc;
2352                         break;
2353                 case PIN_CONFIG_DRIVE_STRENGTH:
2354                         /* rk3288 is the first with per-pin drive-strength */
2355                         if (!info->ctrl->drv_calc_reg)
2356                                 return -ENOTSUPP;
2357
2358                         rc = rockchip_set_drive_perpin(bank,
2359                                                 pin - bank->pin_base, arg);
2360                         if (rc < 0)
2361                                 return rc;
2362                         break;
2363                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2364                         if (!info->ctrl->schmitt_calc_reg)
2365                                 return -ENOTSUPP;
2366
2367                         rc = rockchip_set_schmitt(bank,
2368                                                   pin - bank->pin_base, arg);
2369                         if (rc < 0)
2370                                 return rc;
2371                         break;
2372                 default:
2373                         return -ENOTSUPP;
2374                         break;
2375                 }
2376         } /* for each config */
2377
2378         return 0;
2379 }
2380
2381 /* get the pin config settings for a specified pin */
2382 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2383                                                         unsigned long *config)
2384 {
2385         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2386         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2387         enum pin_config_param param = pinconf_to_config_param(*config);
2388         u16 arg;
2389         int rc;
2390
2391         switch (param) {
2392         case PIN_CONFIG_BIAS_DISABLE:
2393                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2394                         return -EINVAL;
2395
2396                 arg = 0;
2397                 break;
2398         case PIN_CONFIG_BIAS_PULL_UP:
2399         case PIN_CONFIG_BIAS_PULL_DOWN:
2400         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2401         case PIN_CONFIG_BIAS_BUS_HOLD:
2402                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2403                         return -ENOTSUPP;
2404
2405                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2406                         return -EINVAL;
2407
2408                 arg = 1;
2409                 break;
2410         case PIN_CONFIG_OUTPUT:
2411                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2412                 if (rc != RK_FUNC_GPIO)
2413                         return -EINVAL;
2414
2415                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2416                 if (rc < 0)
2417                         return rc;
2418
2419                 arg = rc ? 1 : 0;
2420                 break;
2421         case PIN_CONFIG_DRIVE_STRENGTH:
2422                 /* rk3288 is the first with per-pin drive-strength */
2423                 if (!info->ctrl->drv_calc_reg)
2424                         return -ENOTSUPP;
2425
2426                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2427                 if (rc < 0)
2428                         return rc;
2429
2430                 arg = rc;
2431                 break;
2432         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2433                 if (!info->ctrl->schmitt_calc_reg)
2434                         return -ENOTSUPP;
2435
2436                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2437                 if (rc < 0)
2438                         return rc;
2439
2440                 arg = rc;
2441                 break;
2442         default:
2443                 return -ENOTSUPP;
2444                 break;
2445         }
2446
2447         *config = pinconf_to_config_packed(param, arg);
2448
2449         return 0;
2450 }
2451
2452 static const struct pinconf_ops rockchip_pinconf_ops = {
2453         .pin_config_get                 = rockchip_pinconf_get,
2454         .pin_config_set                 = rockchip_pinconf_set,
2455         .is_generic                     = true,
2456 };
2457
2458 static const struct of_device_id rockchip_bank_match[] = {
2459         { .compatible = "rockchip,gpio-bank" },
2460         { .compatible = "rockchip,rk3188-gpio-bank0" },
2461         {},
2462 };
2463
2464 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2465                                                 struct device_node *np)
2466 {
2467         struct device_node *child;
2468
2469         for_each_child_of_node(np, child) {
2470                 if (of_match_node(rockchip_bank_match, child))
2471                         continue;
2472
2473                 info->nfunctions++;
2474                 info->ngroups += of_get_child_count(child);
2475         }
2476 }
2477
2478 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2479                                               struct rockchip_pin_group *grp,
2480                                               struct rockchip_pinctrl *info,
2481                                               u32 index)
2482 {
2483         struct rockchip_pin_bank *bank;
2484         int size;
2485         const __be32 *list;
2486         int num;
2487         int i, j;
2488         int ret;
2489
2490         dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2491
2492         /* Initialise group */
2493         grp->name = np->name;
2494
2495         /*
2496          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2497          * do sanity check and calculate pins number
2498          */
2499         list = of_get_property(np, "rockchip,pins", &size);
2500         /* we do not check return since it's safe node passed down */
2501         size /= sizeof(*list);
2502         if (!size || size % 4) {
2503                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2504                 return -EINVAL;
2505         }
2506
2507         grp->npins = size / 4;
2508
2509         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2510                                                 GFP_KERNEL);
2511         grp->data = devm_kcalloc(info->dev,
2512                                         grp->npins,
2513                                         sizeof(struct rockchip_pin_config),
2514                                         GFP_KERNEL);
2515         if (!grp->pins || !grp->data)
2516                 return -ENOMEM;
2517
2518         for (i = 0, j = 0; i < size; i += 4, j++) {
2519                 const __be32 *phandle;
2520                 struct device_node *np_config;
2521
2522                 num = be32_to_cpu(*list++);
2523                 bank = bank_num_to_bank(info, num);
2524                 if (IS_ERR(bank))
2525                         return PTR_ERR(bank);
2526
2527                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2528                 grp->data[j].func = be32_to_cpu(*list++);
2529
2530                 phandle = list++;
2531                 if (!phandle)
2532                         return -EINVAL;
2533
2534                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2535                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2536                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2537                 if (ret)
2538                         return ret;
2539         }
2540
2541         return 0;
2542 }
2543
2544 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2545                                                 struct rockchip_pinctrl *info,
2546                                                 u32 index)
2547 {
2548         struct device_node *child;
2549         struct rockchip_pmx_func *func;
2550         struct rockchip_pin_group *grp;
2551         int ret;
2552         static u32 grp_index;
2553         u32 i = 0;
2554
2555         dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2556
2557         func = &info->functions[index];
2558
2559         /* Initialise function */
2560         func->name = np->name;
2561         func->ngroups = of_get_child_count(np);
2562         if (func->ngroups <= 0)
2563                 return 0;
2564
2565         func->groups = devm_kcalloc(info->dev,
2566                         func->ngroups, sizeof(char *), GFP_KERNEL);
2567         if (!func->groups)
2568                 return -ENOMEM;
2569
2570         for_each_child_of_node(np, child) {
2571                 func->groups[i] = child->name;
2572                 grp = &info->groups[grp_index++];
2573                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2574                 if (ret) {
2575                         of_node_put(child);
2576                         return ret;
2577                 }
2578         }
2579
2580         return 0;
2581 }
2582
2583 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2584                                               struct rockchip_pinctrl *info)
2585 {
2586         struct device *dev = &pdev->dev;
2587         struct device_node *np = dev->of_node;
2588         struct device_node *child;
2589         int ret;
2590         int i;
2591
2592         rockchip_pinctrl_child_count(info, np);
2593
2594         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2595         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2596
2597         info->functions = devm_kcalloc(dev,
2598                                               info->nfunctions,
2599                                               sizeof(struct rockchip_pmx_func),
2600                                               GFP_KERNEL);
2601         if (!info->functions)
2602                 return -EINVAL;
2603
2604         info->groups = devm_kcalloc(dev,
2605                                             info->ngroups,
2606                                             sizeof(struct rockchip_pin_group),
2607                                             GFP_KERNEL);
2608         if (!info->groups)
2609                 return -EINVAL;
2610
2611         i = 0;
2612
2613         for_each_child_of_node(np, child) {
2614                 if (of_match_node(rockchip_bank_match, child))
2615                         continue;
2616
2617                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2618                 if (ret) {
2619                         dev_err(&pdev->dev, "failed to parse function\n");
2620                         of_node_put(child);
2621                         return ret;
2622                 }
2623         }
2624
2625         return 0;
2626 }
2627
2628 static int rockchip_pinctrl_register(struct platform_device *pdev,
2629                                         struct rockchip_pinctrl *info)
2630 {
2631         struct pinctrl_desc *ctrldesc = &info->pctl;
2632         struct pinctrl_pin_desc *pindesc, *pdesc;
2633         struct rockchip_pin_bank *pin_bank;
2634         int pin, bank, ret;
2635         int k;
2636
2637         ctrldesc->name = "rockchip-pinctrl";
2638         ctrldesc->owner = THIS_MODULE;
2639         ctrldesc->pctlops = &rockchip_pctrl_ops;
2640         ctrldesc->pmxops = &rockchip_pmx_ops;
2641         ctrldesc->confops = &rockchip_pinconf_ops;
2642
2643         pindesc = devm_kcalloc(&pdev->dev,
2644                                info->ctrl->nr_pins, sizeof(*pindesc),
2645                                GFP_KERNEL);
2646         if (!pindesc)
2647                 return -ENOMEM;
2648
2649         ctrldesc->pins = pindesc;
2650         ctrldesc->npins = info->ctrl->nr_pins;
2651
2652         pdesc = pindesc;
2653         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2654                 pin_bank = &info->ctrl->pin_banks[bank];
2655                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2656                         pdesc->number = k;
2657                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2658                                                 pin_bank->name, pin);
2659                         pdesc++;
2660                 }
2661         }
2662
2663         ret = rockchip_pinctrl_parse_dt(pdev, info);
2664         if (ret)
2665                 return ret;
2666
2667         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2668         if (IS_ERR(info->pctl_dev)) {
2669                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2670                 return PTR_ERR(info->pctl_dev);
2671         }
2672
2673         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2674                 pin_bank = &info->ctrl->pin_banks[bank];
2675                 pin_bank->grange.name = pin_bank->name;
2676                 pin_bank->grange.id = bank;
2677                 pin_bank->grange.pin_base = pin_bank->pin_base;
2678                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2679                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2680                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2681                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2682         }
2683
2684         return 0;
2685 }
2686
2687 /*
2688  * GPIO handling
2689  */
2690
2691 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2692 {
2693         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2694         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2695         unsigned long flags;
2696         u32 data;
2697
2698         clk_enable(bank->clk);
2699         raw_spin_lock_irqsave(&bank->slock, flags);
2700
2701         data = readl(reg);
2702         data &= ~BIT(offset);
2703         if (value)
2704                 data |= BIT(offset);
2705         writel(data, reg);
2706
2707         raw_spin_unlock_irqrestore(&bank->slock, flags);
2708         clk_disable(bank->clk);
2709 }
2710
2711 /*
2712  * Returns the level of the pin for input direction and setting of the DR
2713  * register for output gpios.
2714  */
2715 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2716 {
2717         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2718         u32 data;
2719
2720         clk_enable(bank->clk);
2721         data = readl(bank->reg_base + GPIO_EXT_PORT);
2722         clk_disable(bank->clk);
2723         data >>= offset;
2724         data &= 1;
2725         return data;
2726 }
2727
2728 /*
2729  * gpiolib gpio_direction_input callback function. The setting of the pin
2730  * mux function as 'gpio input' will be handled by the pinctrl subsystem
2731  * interface.
2732  */
2733 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2734 {
2735         return pinctrl_gpio_direction_input(gc->base + offset);
2736 }
2737
2738 /*
2739  * gpiolib gpio_direction_output callback function. The setting of the pin
2740  * mux function as 'gpio output' will be handled by the pinctrl subsystem
2741  * interface.
2742  */
2743 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2744                                           unsigned offset, int value)
2745 {
2746         rockchip_gpio_set(gc, offset, value);
2747         return pinctrl_gpio_direction_output(gc->base + offset);
2748 }
2749
2750 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2751                                        unsigned int offset, bool enable)
2752 {
2753         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2754         void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2755         unsigned long flags;
2756         u32 data;
2757
2758         clk_enable(bank->clk);
2759         raw_spin_lock_irqsave(&bank->slock, flags);
2760
2761         data = readl(reg);
2762         if (enable)
2763                 data |= BIT(offset);
2764         else
2765                 data &= ~BIT(offset);
2766         writel(data, reg);
2767
2768         raw_spin_unlock_irqrestore(&bank->slock, flags);
2769         clk_disable(bank->clk);
2770 }
2771
2772 /*
2773  * gpiolib set_config callback function. The setting of the pin
2774  * mux function as 'gpio output' will be handled by the pinctrl subsystem
2775  * interface.
2776  */
2777 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2778                                   unsigned long config)
2779 {
2780         enum pin_config_param param = pinconf_to_config_param(config);
2781
2782         switch (param) {
2783         case PIN_CONFIG_INPUT_DEBOUNCE:
2784                 rockchip_gpio_set_debounce(gc, offset, true);
2785                 /*
2786                  * Rockchip's gpio could only support up to one period
2787                  * of the debounce clock(pclk), which is far away from
2788                  * satisftying the requirement, as pclk is usually near
2789                  * 100MHz shared by all peripherals. So the fact is it
2790                  * has crippled debounce capability could only be useful
2791                  * to prevent any spurious glitches from waking up the system
2792                  * if the gpio is conguired as wakeup interrupt source. Let's
2793                  * still return -ENOTSUPP as before, to make sure the caller
2794                  * of gpiod_set_debounce won't change its behaviour.
2795                  */
2796                 return -ENOTSUPP;
2797         default:
2798                 return -ENOTSUPP;
2799         }
2800 }
2801
2802 /*
2803  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2804  * and a virtual IRQ, if not already present.
2805  */
2806 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2807 {
2808         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2809         unsigned int virq;
2810
2811         if (!bank->domain)
2812                 return -ENXIO;
2813
2814         clk_enable(bank->clk);
2815         virq = irq_create_mapping(bank->domain, offset);
2816         clk_disable(bank->clk);
2817
2818         return (virq) ? : -ENXIO;
2819 }
2820
2821 static const struct gpio_chip rockchip_gpiolib_chip = {
2822         .request = gpiochip_generic_request,
2823         .free = gpiochip_generic_free,
2824         .set = rockchip_gpio_set,
2825         .get = rockchip_gpio_get,
2826         .get_direction  = rockchip_gpio_get_direction,
2827         .direction_input = rockchip_gpio_direction_input,
2828         .direction_output = rockchip_gpio_direction_output,
2829         .set_config = rockchip_gpio_set_config,
2830         .to_irq = rockchip_gpio_to_irq,
2831         .owner = THIS_MODULE,
2832 };
2833
2834 /*
2835  * Interrupt handling
2836  */
2837
2838 static void rockchip_irq_demux(struct irq_desc *desc)
2839 {
2840         struct irq_chip *chip = irq_desc_get_chip(desc);
2841         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2842         u32 pend;
2843
2844         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2845
2846         chained_irq_enter(chip, desc);
2847
2848         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2849
2850         while (pend) {
2851                 unsigned int irq, virq;
2852
2853                 irq = __ffs(pend);
2854                 pend &= ~BIT(irq);
2855                 virq = irq_linear_revmap(bank->domain, irq);
2856
2857                 if (!virq) {
2858                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2859                         continue;
2860                 }
2861
2862                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2863
2864                 /*
2865                  * Triggering IRQ on both rising and falling edge
2866                  * needs manual intervention.
2867                  */
2868                 if (bank->toggle_edge_mode & BIT(irq)) {
2869                         u32 data, data_old, polarity;
2870                         unsigned long flags;
2871
2872                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2873                         do {
2874                                 raw_spin_lock_irqsave(&bank->slock, flags);
2875
2876                                 polarity = readl_relaxed(bank->reg_base +
2877                                                          GPIO_INT_POLARITY);
2878                                 if (data & BIT(irq))
2879                                         polarity &= ~BIT(irq);
2880                                 else
2881                                         polarity |= BIT(irq);
2882                                 writel(polarity,
2883                                        bank->reg_base + GPIO_INT_POLARITY);
2884
2885                                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2886
2887                                 data_old = data;
2888                                 data = readl_relaxed(bank->reg_base +
2889                                                      GPIO_EXT_PORT);
2890                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2891                 }
2892
2893                 generic_handle_irq(virq);
2894         }
2895
2896         chained_irq_exit(chip, desc);
2897 }
2898
2899 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2900 {
2901         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2902         struct rockchip_pin_bank *bank = gc->private;
2903         u32 mask = BIT(d->hwirq);
2904         u32 polarity;
2905         u32 level;
2906         u32 data;
2907         unsigned long flags;
2908         int ret;
2909
2910         /* make sure the pin is configured as gpio input */
2911         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2912         if (ret < 0)
2913                 return ret;
2914
2915         clk_enable(bank->clk);
2916         raw_spin_lock_irqsave(&bank->slock, flags);
2917
2918         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2919         data &= ~mask;
2920         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2921
2922         raw_spin_unlock_irqrestore(&bank->slock, flags);
2923
2924         if (type & IRQ_TYPE_EDGE_BOTH)
2925                 irq_set_handler_locked(d, handle_edge_irq);
2926         else
2927                 irq_set_handler_locked(d, handle_level_irq);
2928
2929         raw_spin_lock_irqsave(&bank->slock, flags);
2930         irq_gc_lock(gc);
2931
2932         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2933         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2934
2935         switch (type) {
2936         case IRQ_TYPE_EDGE_BOTH:
2937                 bank->toggle_edge_mode |= mask;
2938                 level |= mask;
2939
2940                 /*
2941                  * Determine gpio state. If 1 next interrupt should be falling
2942                  * otherwise rising.
2943                  */
2944                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2945                 if (data & mask)
2946                         polarity &= ~mask;
2947                 else
2948                         polarity |= mask;
2949                 break;
2950         case IRQ_TYPE_EDGE_RISING:
2951                 bank->toggle_edge_mode &= ~mask;
2952                 level |= mask;
2953                 polarity |= mask;
2954                 break;
2955         case IRQ_TYPE_EDGE_FALLING:
2956                 bank->toggle_edge_mode &= ~mask;
2957                 level |= mask;
2958                 polarity &= ~mask;
2959                 break;
2960         case IRQ_TYPE_LEVEL_HIGH:
2961                 bank->toggle_edge_mode &= ~mask;
2962                 level &= ~mask;
2963                 polarity |= mask;
2964                 break;
2965         case IRQ_TYPE_LEVEL_LOW:
2966                 bank->toggle_edge_mode &= ~mask;
2967                 level &= ~mask;
2968                 polarity &= ~mask;
2969                 break;
2970         default:
2971                 irq_gc_unlock(gc);
2972                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2973                 clk_disable(bank->clk);
2974                 return -EINVAL;
2975         }
2976
2977         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2978         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2979
2980         irq_gc_unlock(gc);
2981         raw_spin_unlock_irqrestore(&bank->slock, flags);
2982         clk_disable(bank->clk);
2983
2984         return 0;
2985 }
2986
2987 static void rockchip_irq_suspend(struct irq_data *d)
2988 {
2989         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2990         struct rockchip_pin_bank *bank = gc->private;
2991
2992         clk_enable(bank->clk);
2993         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2994         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2995         clk_disable(bank->clk);
2996 }
2997
2998 static void rockchip_irq_resume(struct irq_data *d)
2999 {
3000         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3001         struct rockchip_pin_bank *bank = gc->private;
3002
3003         clk_enable(bank->clk);
3004         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3005         clk_disable(bank->clk);
3006 }
3007
3008 static void rockchip_irq_enable(struct irq_data *d)
3009 {
3010         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3011         struct rockchip_pin_bank *bank = gc->private;
3012
3013         clk_enable(bank->clk);
3014         irq_gc_mask_clr_bit(d);
3015 }
3016
3017 static void rockchip_irq_disable(struct irq_data *d)
3018 {
3019         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3020         struct rockchip_pin_bank *bank = gc->private;
3021
3022         irq_gc_mask_set_bit(d);
3023         clk_disable(bank->clk);
3024 }
3025
3026 static int rockchip_interrupts_register(struct platform_device *pdev,
3027                                                 struct rockchip_pinctrl *info)
3028 {
3029         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3030         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3031         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3032         struct irq_chip_generic *gc;
3033         int ret;
3034         int i, j;
3035
3036         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3037                 if (!bank->valid) {
3038                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3039                                  bank->name);
3040                         continue;
3041                 }
3042
3043                 ret = clk_enable(bank->clk);
3044                 if (ret) {
3045                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3046                                 bank->name);
3047                         continue;
3048                 }
3049
3050                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3051                                                 &irq_generic_chip_ops, NULL);
3052                 if (!bank->domain) {
3053                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3054                                  bank->name);
3055                         clk_disable(bank->clk);
3056                         continue;
3057                 }
3058
3059                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3060                                          "rockchip_gpio_irq", handle_level_irq,
3061                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
3062                 if (ret) {
3063                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3064                                 bank->name);
3065                         irq_domain_remove(bank->domain);
3066                         clk_disable(bank->clk);
3067                         continue;
3068                 }
3069
3070                 /*
3071                  * Linux assumes that all interrupts start out disabled/masked.
3072                  * Our driver only uses the concept of masked and always keeps
3073                  * things enabled, so for us that's all masked and all enabled.
3074                  */
3075                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3076                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3077
3078                 gc = irq_get_domain_generic_chip(bank->domain, 0);
3079                 gc->reg_base = bank->reg_base;
3080                 gc->private = bank;
3081                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3082                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3083                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3084                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3085                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3086                 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3087                 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3088                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3089                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3090                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3091                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3092                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3093
3094                 irq_set_chained_handler_and_data(bank->irq,
3095                                                  rockchip_irq_demux, bank);
3096
3097                 /* map the gpio irqs here, when the clock is still running */
3098                 for (j = 0 ; j < 32 ; j++)
3099                         irq_create_mapping(bank->domain, j);
3100
3101                 clk_disable(bank->clk);
3102         }
3103
3104         return 0;
3105 }
3106
3107 static int rockchip_gpiolib_register(struct platform_device *pdev,
3108                                                 struct rockchip_pinctrl *info)
3109 {
3110         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3111         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3112         struct gpio_chip *gc;
3113         int ret;
3114         int i;
3115
3116         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3117                 if (!bank->valid) {
3118                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3119                                  bank->name);
3120                         continue;
3121                 }
3122
3123                 bank->gpio_chip = rockchip_gpiolib_chip;
3124
3125                 gc = &bank->gpio_chip;
3126                 gc->base = bank->pin_base;
3127                 gc->ngpio = bank->nr_pins;
3128                 gc->parent = &pdev->dev;
3129                 gc->of_node = bank->of_node;
3130                 gc->label = bank->name;
3131
3132                 ret = gpiochip_add_data(gc, bank);
3133                 if (ret) {
3134                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3135                                                         gc->label, ret);
3136                         goto fail;
3137                 }
3138         }
3139
3140         rockchip_interrupts_register(pdev, info);
3141
3142         return 0;
3143
3144 fail:
3145         for (--i, --bank; i >= 0; --i, --bank) {
3146                 if (!bank->valid)
3147                         continue;
3148                 gpiochip_remove(&bank->gpio_chip);
3149         }
3150         return ret;
3151 }
3152
3153 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3154                                                 struct rockchip_pinctrl *info)
3155 {
3156         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3157         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3158         int i;
3159
3160         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3161                 if (!bank->valid)
3162                         continue;
3163                 gpiochip_remove(&bank->gpio_chip);
3164         }
3165
3166         return 0;
3167 }
3168
3169 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3170                                   struct rockchip_pinctrl *info)
3171 {
3172         struct resource res;
3173         void __iomem *base;
3174
3175         if (of_address_to_resource(bank->of_node, 0, &res)) {
3176                 dev_err(info->dev, "cannot find IO resource for bank\n");
3177                 return -ENOENT;
3178         }
3179
3180         bank->reg_base = devm_ioremap_resource(info->dev, &res);
3181         if (IS_ERR(bank->reg_base))
3182                 return PTR_ERR(bank->reg_base);
3183
3184         /*
3185          * special case, where parts of the pull setting-registers are
3186          * part of the PMU register space
3187          */
3188         if (of_device_is_compatible(bank->of_node,
3189                                     "rockchip,rk3188-gpio-bank0")) {
3190                 struct device_node *node;
3191
3192                 node = of_parse_phandle(bank->of_node->parent,
3193                                         "rockchip,pmu", 0);
3194                 if (!node) {
3195                         if (of_address_to_resource(bank->of_node, 1, &res)) {
3196                                 dev_err(info->dev, "cannot find IO resource for bank\n");
3197                                 return -ENOENT;
3198                         }
3199
3200                         base = devm_ioremap_resource(info->dev, &res);
3201                         if (IS_ERR(base))
3202                                 return PTR_ERR(base);
3203                         rockchip_regmap_config.max_register =
3204                                                     resource_size(&res) - 4;
3205                         rockchip_regmap_config.name =
3206                                             "rockchip,rk3188-gpio-bank0-pull";
3207                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3208                                                     base,
3209                                                     &rockchip_regmap_config);
3210                 }
3211                 of_node_put(node);
3212         }
3213
3214         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3215
3216         bank->clk = of_clk_get(bank->of_node, 0);
3217         if (IS_ERR(bank->clk))
3218                 return PTR_ERR(bank->clk);
3219
3220         return clk_prepare(bank->clk);
3221 }
3222
3223 static const struct of_device_id rockchip_pinctrl_dt_match[];
3224
3225 /* retrieve the soc specific data */
3226 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3227                                                 struct rockchip_pinctrl *d,
3228                                                 struct platform_device *pdev)
3229 {
3230         const struct of_device_id *match;
3231         struct device_node *node = pdev->dev.of_node;
3232         struct device_node *np;
3233         struct rockchip_pin_ctrl *ctrl;
3234         struct rockchip_pin_bank *bank;
3235         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3236
3237         match = of_match_node(rockchip_pinctrl_dt_match, node);
3238         ctrl = (struct rockchip_pin_ctrl *)match->data;
3239
3240         for_each_child_of_node(node, np) {
3241                 if (!of_find_property(np, "gpio-controller", NULL))
3242                         continue;
3243
3244                 bank = ctrl->pin_banks;
3245                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3246                         if (!strcmp(bank->name, np->name)) {
3247                                 bank->of_node = np;
3248
3249                                 if (!rockchip_get_bank_data(bank, d))
3250                                         bank->valid = true;
3251
3252                                 break;
3253                         }
3254                 }
3255         }
3256
3257         grf_offs = ctrl->grf_mux_offset;
3258         pmu_offs = ctrl->pmu_mux_offset;
3259         drv_pmu_offs = ctrl->pmu_drv_offset;
3260         drv_grf_offs = ctrl->grf_drv_offset;
3261         bank = ctrl->pin_banks;
3262         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3263                 int bank_pins = 0;
3264
3265                 raw_spin_lock_init(&bank->slock);
3266                 bank->drvdata = d;
3267                 bank->pin_base = ctrl->nr_pins;
3268                 ctrl->nr_pins += bank->nr_pins;
3269
3270                 /* calculate iomux and drv offsets */
3271                 for (j = 0; j < 4; j++) {
3272                         struct rockchip_iomux *iom = &bank->iomux[j];
3273                         struct rockchip_drv *drv = &bank->drv[j];
3274                         int inc;
3275
3276                         if (bank_pins >= bank->nr_pins)
3277                                 break;
3278
3279                         /* preset iomux offset value, set new start value */
3280                         if (iom->offset >= 0) {
3281                                 if (iom->type & IOMUX_SOURCE_PMU)
3282                                         pmu_offs = iom->offset;
3283                                 else
3284                                         grf_offs = iom->offset;
3285                         } else { /* set current iomux offset */
3286                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3287                                                         pmu_offs : grf_offs;
3288                         }
3289
3290                         /* preset drv offset value, set new start value */
3291                         if (drv->offset >= 0) {
3292                                 if (iom->type & IOMUX_SOURCE_PMU)
3293                                         drv_pmu_offs = drv->offset;
3294                                 else
3295                                         drv_grf_offs = drv->offset;
3296                         } else { /* set current drv offset */
3297                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3298                                                 drv_pmu_offs : drv_grf_offs;
3299                         }
3300
3301                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3302                                 i, j, iom->offset, drv->offset);
3303
3304                         /*
3305                          * Increase offset according to iomux width.
3306                          * 4bit iomux'es are spread over two registers.
3307                          */
3308                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3309                                             IOMUX_WIDTH_3BIT)) ? 8 : 4;
3310                         if (iom->type & IOMUX_SOURCE_PMU)
3311                                 pmu_offs += inc;
3312                         else
3313                                 grf_offs += inc;
3314
3315                         /*
3316                          * Increase offset according to drv width.
3317                          * 3bit drive-strenth'es are spread over two registers.
3318                          */
3319                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3320                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3321                                 inc = 8;
3322                         else
3323                                 inc = 4;
3324
3325                         if (iom->type & IOMUX_SOURCE_PMU)
3326                                 drv_pmu_offs += inc;
3327                         else
3328                                 drv_grf_offs += inc;
3329
3330                         bank_pins += 8;
3331                 }
3332
3333                 /* calculate the per-bank recalced_mask */
3334                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3335                         int pin = 0;
3336
3337                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3338                                 pin = ctrl->iomux_recalced[j].pin;
3339                                 bank->recalced_mask |= BIT(pin);
3340                         }
3341                 }
3342
3343                 /* calculate the per-bank route_mask */
3344                 for (j = 0; j < ctrl->niomux_routes; j++) {
3345                         int pin = 0;
3346
3347                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3348                                 pin = ctrl->iomux_routes[j].pin;
3349                                 bank->route_mask |= BIT(pin);
3350                         }
3351                 }
3352         }
3353
3354         return ctrl;
3355 }
3356
3357 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3358 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3359
3360 static u32 rk3288_grf_gpio6c_iomux;
3361
3362 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3363 {
3364         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3365         int ret = pinctrl_force_sleep(info->pctl_dev);
3366
3367         if (ret)
3368                 return ret;
3369
3370         /*
3371          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3372          * the setting here, and restore it at resume.
3373          */
3374         if (info->ctrl->type == RK3288) {
3375                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3376                                   &rk3288_grf_gpio6c_iomux);
3377                 if (ret) {
3378                         pinctrl_force_default(info->pctl_dev);
3379                         return ret;
3380                 }
3381         }
3382
3383         return 0;
3384 }
3385
3386 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3387 {
3388         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3389         int ret;
3390
3391         if (info->ctrl->type == RK3288) {
3392                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3393                                    rk3288_grf_gpio6c_iomux |
3394                                    GPIO6C6_SEL_WRITE_ENABLE);
3395                 if (ret)
3396                         return ret;
3397         }
3398
3399         return pinctrl_force_default(info->pctl_dev);
3400 }
3401
3402 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3403                          rockchip_pinctrl_resume);
3404
3405 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3406 {
3407         struct rockchip_pinctrl *info;
3408         struct device *dev = &pdev->dev;
3409         struct rockchip_pin_ctrl *ctrl;
3410         struct device_node *np = pdev->dev.of_node, *node;
3411         struct resource *res;
3412         void __iomem *base;
3413         int ret;
3414
3415         if (!dev->of_node) {
3416                 dev_err(dev, "device tree node not found\n");
3417                 return -ENODEV;
3418         }
3419
3420         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3421         if (!info)
3422                 return -ENOMEM;
3423
3424         info->dev = dev;
3425
3426         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3427         if (!ctrl) {
3428                 dev_err(dev, "driver data not available\n");
3429                 return -EINVAL;
3430         }
3431         info->ctrl = ctrl;
3432
3433         node = of_parse_phandle(np, "rockchip,grf", 0);
3434         if (node) {
3435                 info->regmap_base = syscon_node_to_regmap(node);
3436                 of_node_put(node);
3437                 if (IS_ERR(info->regmap_base))
3438                         return PTR_ERR(info->regmap_base);
3439         } else {
3440                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3441                 base = devm_ioremap_resource(&pdev->dev, res);
3442                 if (IS_ERR(base))
3443                         return PTR_ERR(base);
3444
3445                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3446                 rockchip_regmap_config.name = "rockchip,pinctrl";
3447                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3448                                                     &rockchip_regmap_config);
3449
3450                 /* to check for the old dt-bindings */
3451                 info->reg_size = resource_size(res);
3452
3453                 /* Honor the old binding, with pull registers as 2nd resource */
3454                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3455                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3456                         base = devm_ioremap_resource(&pdev->dev, res);
3457                         if (IS_ERR(base))
3458                                 return PTR_ERR(base);
3459
3460                         rockchip_regmap_config.max_register =
3461                                                         resource_size(res) - 4;
3462                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3463                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3464                                                     base,
3465                                                     &rockchip_regmap_config);
3466                 }
3467         }
3468
3469         /* try to find the optional reference to the pmu syscon */
3470         node = of_parse_phandle(np, "rockchip,pmu", 0);
3471         if (node) {
3472                 info->regmap_pmu = syscon_node_to_regmap(node);
3473                 of_node_put(node);
3474                 if (IS_ERR(info->regmap_pmu))
3475                         return PTR_ERR(info->regmap_pmu);
3476         }
3477
3478         ret = rockchip_gpiolib_register(pdev, info);
3479         if (ret)
3480                 return ret;
3481
3482         ret = rockchip_pinctrl_register(pdev, info);
3483         if (ret) {
3484                 rockchip_gpiolib_unregister(pdev, info);
3485                 return ret;
3486         }
3487
3488         platform_set_drvdata(pdev, info);
3489
3490         return 0;
3491 }
3492
3493 static struct rockchip_pin_bank px30_pin_banks[] = {
3494         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3495                                              IOMUX_SOURCE_PMU,
3496                                              IOMUX_SOURCE_PMU,
3497                                              IOMUX_SOURCE_PMU
3498                             ),
3499         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3500                                              IOMUX_WIDTH_4BIT,
3501                                              IOMUX_WIDTH_4BIT,
3502                                              IOMUX_WIDTH_4BIT
3503                             ),
3504         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3505                                              IOMUX_WIDTH_4BIT,
3506                                              IOMUX_WIDTH_4BIT,
3507                                              IOMUX_WIDTH_4BIT
3508                             ),
3509         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3510                                              IOMUX_WIDTH_4BIT,
3511                                              IOMUX_WIDTH_4BIT,
3512                                              IOMUX_WIDTH_4BIT
3513                             ),
3514 };
3515
3516 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3517                 .pin_banks              = px30_pin_banks,
3518                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
3519                 .label                  = "PX30-GPIO",
3520                 .type                   = PX30,
3521                 .grf_mux_offset         = 0x0,
3522                 .pmu_mux_offset         = 0x0,
3523                 .iomux_routes           = px30_mux_route_data,
3524                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
3525                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
3526                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
3527                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
3528 };
3529
3530 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3531         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3532                                              IOMUX_SOURCE_PMU,
3533                                              IOMUX_SOURCE_PMU,
3534                                              IOMUX_SOURCE_PMU),
3535         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3536         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3537         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3538 };
3539
3540 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3541         .pin_banks              = rv1108_pin_banks,
3542         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3543         .label                  = "RV1108-GPIO",
3544         .type                   = RV1108,
3545         .grf_mux_offset         = 0x10,
3546         .pmu_mux_offset         = 0x0,
3547         .iomux_recalced         = rv1108_mux_recalced_data,
3548         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3549         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3550         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3551         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3552 };
3553
3554 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3555         PIN_BANK(0, 32, "gpio0"),
3556         PIN_BANK(1, 32, "gpio1"),
3557         PIN_BANK(2, 32, "gpio2"),
3558         PIN_BANK(3, 32, "gpio3"),
3559 };
3560
3561 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3562                 .pin_banks              = rk2928_pin_banks,
3563                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3564                 .label                  = "RK2928-GPIO",
3565                 .type                   = RK2928,
3566                 .grf_mux_offset         = 0xa8,
3567                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3568 };
3569
3570 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3571         PIN_BANK(0, 32, "gpio0"),
3572         PIN_BANK(1, 32, "gpio1"),
3573         PIN_BANK(2, 32, "gpio2"),
3574 };
3575
3576 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3577                 .pin_banks              = rk3036_pin_banks,
3578                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3579                 .label                  = "RK3036-GPIO",
3580                 .type                   = RK2928,
3581                 .grf_mux_offset         = 0xa8,
3582                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3583 };
3584
3585 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3586         PIN_BANK(0, 32, "gpio0"),
3587         PIN_BANK(1, 32, "gpio1"),
3588         PIN_BANK(2, 32, "gpio2"),
3589         PIN_BANK(3, 32, "gpio3"),
3590         PIN_BANK(4, 32, "gpio4"),
3591         PIN_BANK(6, 16, "gpio6"),
3592 };
3593
3594 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3595                 .pin_banks              = rk3066a_pin_banks,
3596                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3597                 .label                  = "RK3066a-GPIO",
3598                 .type                   = RK2928,
3599                 .grf_mux_offset         = 0xa8,
3600                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3601 };
3602
3603 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3604         PIN_BANK(0, 32, "gpio0"),
3605         PIN_BANK(1, 32, "gpio1"),
3606         PIN_BANK(2, 32, "gpio2"),
3607         PIN_BANK(3, 32, "gpio3"),
3608 };
3609
3610 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3611                 .pin_banks      = rk3066b_pin_banks,
3612                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3613                 .label          = "RK3066b-GPIO",
3614                 .type           = RK3066B,
3615                 .grf_mux_offset = 0x60,
3616 };
3617
3618 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3619         PIN_BANK(0, 32, "gpio0"),
3620         PIN_BANK(1, 32, "gpio1"),
3621         PIN_BANK(2, 32, "gpio2"),
3622         PIN_BANK(3, 32, "gpio3"),
3623 };
3624
3625 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3626                 .pin_banks              = rk3128_pin_banks,
3627                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3628                 .label                  = "RK3128-GPIO",
3629                 .type                   = RK3128,
3630                 .grf_mux_offset         = 0xa8,
3631                 .iomux_recalced         = rk3128_mux_recalced_data,
3632                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3633                 .iomux_routes           = rk3128_mux_route_data,
3634                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3635                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3636 };
3637
3638 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3639         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3640         PIN_BANK(1, 32, "gpio1"),
3641         PIN_BANK(2, 32, "gpio2"),
3642         PIN_BANK(3, 32, "gpio3"),
3643 };
3644
3645 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3646                 .pin_banks              = rk3188_pin_banks,
3647                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3648                 .label                  = "RK3188-GPIO",
3649                 .type                   = RK3188,
3650                 .grf_mux_offset         = 0x60,
3651                 .iomux_routes           = rk3188_mux_route_data,
3652                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
3653                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3654 };
3655
3656 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3657         PIN_BANK(0, 32, "gpio0"),
3658         PIN_BANK(1, 32, "gpio1"),
3659         PIN_BANK(2, 32, "gpio2"),
3660         PIN_BANK(3, 32, "gpio3"),
3661 };
3662
3663 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3664                 .pin_banks              = rk3228_pin_banks,
3665                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3666                 .label                  = "RK3228-GPIO",
3667                 .type                   = RK3288,
3668                 .grf_mux_offset         = 0x0,
3669                 .iomux_routes           = rk3228_mux_route_data,
3670                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3671                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3672                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3673 };
3674
3675 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3676         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3677                                              IOMUX_SOURCE_PMU,
3678                                              IOMUX_SOURCE_PMU,
3679                                              IOMUX_UNROUTED
3680                             ),
3681         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3682                                              IOMUX_UNROUTED,
3683                                              IOMUX_UNROUTED,
3684                                              0
3685                             ),
3686         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3687         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3688         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3689                                              IOMUX_WIDTH_4BIT,
3690                                              0,
3691                                              0
3692                             ),
3693         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3694                                              0,
3695                                              0,
3696                                              IOMUX_UNROUTED
3697                             ),
3698         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3699         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3700                                              0,
3701                                              IOMUX_WIDTH_4BIT,
3702                                              IOMUX_UNROUTED
3703                             ),
3704         PIN_BANK(8, 16, "gpio8"),
3705 };
3706
3707 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3708                 .pin_banks              = rk3288_pin_banks,
3709                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3710                 .label                  = "RK3288-GPIO",
3711                 .type                   = RK3288,
3712                 .grf_mux_offset         = 0x0,
3713                 .pmu_mux_offset         = 0x84,
3714                 .iomux_routes           = rk3288_mux_route_data,
3715                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3716                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3717                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3718 };
3719
3720 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3721         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3722         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3723         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3724                              IOMUX_WIDTH_3BIT,
3725                              IOMUX_WIDTH_3BIT,
3726                              0),
3727         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3728                              IOMUX_WIDTH_3BIT,
3729                              IOMUX_WIDTH_3BIT,
3730                              0,
3731                              0),
3732 };
3733
3734 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3735                 .pin_banks              = rk3328_pin_banks,
3736                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3737                 .label                  = "RK3328-GPIO",
3738                 .type                   = RK3288,
3739                 .grf_mux_offset         = 0x0,
3740                 .iomux_recalced         = rk3328_mux_recalced_data,
3741                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3742                 .iomux_routes           = rk3328_mux_route_data,
3743                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3744                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3745                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3746                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3747 };
3748
3749 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3750         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3751                                              IOMUX_SOURCE_PMU,
3752                                              IOMUX_SOURCE_PMU,
3753                                              IOMUX_SOURCE_PMU
3754                             ),
3755         PIN_BANK(1, 32, "gpio1"),
3756         PIN_BANK(2, 32, "gpio2"),
3757         PIN_BANK(3, 32, "gpio3"),
3758 };
3759
3760 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3761                 .pin_banks              = rk3368_pin_banks,
3762                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3763                 .label                  = "RK3368-GPIO",
3764                 .type                   = RK3368,
3765                 .grf_mux_offset         = 0x0,
3766                 .pmu_mux_offset         = 0x0,
3767                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3768                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3769 };
3770
3771 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3772         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3773                                                          IOMUX_SOURCE_PMU,
3774                                                          IOMUX_SOURCE_PMU,
3775                                                          IOMUX_SOURCE_PMU,
3776                                                          IOMUX_SOURCE_PMU,
3777                                                          DRV_TYPE_IO_1V8_ONLY,
3778                                                          DRV_TYPE_IO_1V8_ONLY,
3779                                                          DRV_TYPE_IO_DEFAULT,
3780                                                          DRV_TYPE_IO_DEFAULT,
3781                                                          0x80,
3782                                                          0x88,
3783                                                          -1,
3784                                                          -1,
3785                                                          PULL_TYPE_IO_1V8_ONLY,
3786                                                          PULL_TYPE_IO_1V8_ONLY,
3787                                                          PULL_TYPE_IO_DEFAULT,
3788                                                          PULL_TYPE_IO_DEFAULT
3789                                                         ),
3790         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3791                                         IOMUX_SOURCE_PMU,
3792                                         IOMUX_SOURCE_PMU,
3793                                         IOMUX_SOURCE_PMU,
3794                                         DRV_TYPE_IO_1V8_OR_3V0,
3795                                         DRV_TYPE_IO_1V8_OR_3V0,
3796                                         DRV_TYPE_IO_1V8_OR_3V0,
3797                                         DRV_TYPE_IO_1V8_OR_3V0,
3798                                         0xa0,
3799                                         0xa8,
3800                                         0xb0,
3801                                         0xb8
3802                                         ),
3803         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3804                                       DRV_TYPE_IO_1V8_OR_3V0,
3805                                       DRV_TYPE_IO_1V8_ONLY,
3806                                       DRV_TYPE_IO_1V8_ONLY,
3807                                       PULL_TYPE_IO_DEFAULT,
3808                                       PULL_TYPE_IO_DEFAULT,
3809                                       PULL_TYPE_IO_1V8_ONLY,
3810                                       PULL_TYPE_IO_1V8_ONLY
3811                                       ),
3812         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3813                            DRV_TYPE_IO_3V3_ONLY,
3814                            DRV_TYPE_IO_3V3_ONLY,
3815                            DRV_TYPE_IO_1V8_OR_3V0
3816                            ),
3817         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3818                            DRV_TYPE_IO_1V8_3V0_AUTO,
3819                            DRV_TYPE_IO_1V8_OR_3V0,
3820                            DRV_TYPE_IO_1V8_OR_3V0
3821                            ),
3822 };
3823
3824 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3825                 .pin_banks              = rk3399_pin_banks,
3826                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3827                 .label                  = "RK3399-GPIO",
3828                 .type                   = RK3399,
3829                 .grf_mux_offset         = 0xe000,
3830                 .pmu_mux_offset         = 0x0,
3831                 .grf_drv_offset         = 0xe100,
3832                 .pmu_drv_offset         = 0x80,
3833                 .iomux_routes           = rk3399_mux_route_data,
3834                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3835                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3836                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3837 };
3838
3839 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3840         { .compatible = "rockchip,px30-pinctrl",
3841                 .data = &px30_pin_ctrl },
3842         { .compatible = "rockchip,rv1108-pinctrl",
3843                 .data = &rv1108_pin_ctrl },
3844         { .compatible = "rockchip,rk2928-pinctrl",
3845                 .data = &rk2928_pin_ctrl },
3846         { .compatible = "rockchip,rk3036-pinctrl",
3847                 .data = &rk3036_pin_ctrl },
3848         { .compatible = "rockchip,rk3066a-pinctrl",
3849                 .data = &rk3066a_pin_ctrl },
3850         { .compatible = "rockchip,rk3066b-pinctrl",
3851                 .data = &rk3066b_pin_ctrl },
3852         { .compatible = "rockchip,rk3128-pinctrl",
3853                 .data = (void *)&rk3128_pin_ctrl },
3854         { .compatible = "rockchip,rk3188-pinctrl",
3855                 .data = &rk3188_pin_ctrl },
3856         { .compatible = "rockchip,rk3228-pinctrl",
3857                 .data = &rk3228_pin_ctrl },
3858         { .compatible = "rockchip,rk3288-pinctrl",
3859                 .data = &rk3288_pin_ctrl },
3860         { .compatible = "rockchip,rk3328-pinctrl",
3861                 .data = &rk3328_pin_ctrl },
3862         { .compatible = "rockchip,rk3368-pinctrl",
3863                 .data = &rk3368_pin_ctrl },
3864         { .compatible = "rockchip,rk3399-pinctrl",
3865                 .data = &rk3399_pin_ctrl },
3866         {},
3867 };
3868
3869 static struct platform_driver rockchip_pinctrl_driver = {
3870         .probe          = rockchip_pinctrl_probe,
3871         .driver = {
3872                 .name   = "rockchip-pinctrl",
3873                 .pm = &rockchip_pinctrl_dev_pm_ops,
3874                 .of_match_table = rockchip_pinctrl_dt_match,
3875         },
3876 };
3877
3878 static int __init rockchip_pinctrl_drv_register(void)
3879 {
3880         return platform_driver_register(&rockchip_pinctrl_driver);
3881 }
3882 postcore_initcall(rockchip_pinctrl_drv_register);