1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl driver for Rockchip SoCs
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * http://www.linaro.org
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
21 #include <linux/bitops.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/clk.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
39 /* GPIO control registers */
40 #define GPIO_SWPORT_DR 0x00
41 #define GPIO_SWPORT_DDR 0x04
42 #define GPIO_INTEN 0x30
43 #define GPIO_INTMASK 0x34
44 #define GPIO_INTTYPE_LEVEL 0x38
45 #define GPIO_INT_POLARITY 0x3c
46 #define GPIO_INT_STATUS 0x40
47 #define GPIO_INT_RAWSTATUS 0x44
48 #define GPIO_DEBOUNCE 0x48
49 #define GPIO_PORTS_EOI 0x4c
50 #define GPIO_EXT_PORT 0x50
51 #define GPIO_LS_SYNC 0x60
53 enum rockchip_pinctrl_type {
66 * Encode variants of iomux registers into a type variable
68 #define IOMUX_GPIO_ONLY BIT(0)
69 #define IOMUX_WIDTH_4BIT BIT(1)
70 #define IOMUX_SOURCE_PMU BIT(2)
71 #define IOMUX_UNROUTED BIT(3)
72 #define IOMUX_WIDTH_3BIT BIT(4)
75 * @type: iomux variant using IOMUX_* constants
76 * @offset: if initialized to -1 it will be autocalculated, by specifying
77 * an initial offset value the relevant source offset can be reset
78 * to a new value for autocalculating the following iomux registers.
80 struct rockchip_iomux {
86 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
88 enum rockchip_pin_drv_type {
89 DRV_TYPE_IO_DEFAULT = 0,
90 DRV_TYPE_IO_1V8_OR_3V0,
92 DRV_TYPE_IO_1V8_3V0_AUTO,
98 * enum type index corresponding to rockchip_pull_list arrays index.
100 enum rockchip_pin_pull_type {
101 PULL_TYPE_IO_DEFAULT = 0,
102 PULL_TYPE_IO_1V8_ONLY,
107 * @drv_type: drive strength variant using rockchip_perpin_drv_type
108 * @offset: if initialized to -1 it will be autocalculated, by specifying
109 * an initial offset value the relevant source offset can be reset
110 * to a new value for autocalculating the following drive strength
111 * registers. if used chips own cal_drv func instead to calculate
112 * registers offset, the variant could be ignored.
114 struct rockchip_drv {
115 enum rockchip_pin_drv_type drv_type;
120 * @reg_base: register base of the gpio bank
121 * @reg_pull: optional separate register for additional pull settings
122 * @clk: clock of the gpio bank
123 * @irq: interrupt of the gpio bank
124 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
125 * @pin_base: first pin number
126 * @nr_pins: number of pins in this bank
127 * @name: name of the bank
128 * @bank_num: number of the bank, to account for holes
129 * @iomux: array describing the 4 iomux sources of the bank
130 * @drv: array describing the 4 drive strength sources of the bank
131 * @pull_type: array describing the 4 pull type sources of the bank
132 * @valid: is all necessary information present
133 * @of_node: dt node of this bank
134 * @drvdata: common pinctrl basedata
135 * @domain: irqdomain of the gpio bank
136 * @gpio_chip: gpiolib chip
137 * @grange: gpio range
138 * @slock: spinlock for the gpio bank
139 * @route_mask: bits describing the routing pins of per bank
141 struct rockchip_pin_bank {
142 void __iomem *reg_base;
143 struct regmap *regmap_pull;
151 struct rockchip_iomux iomux[4];
152 struct rockchip_drv drv[4];
153 enum rockchip_pin_pull_type pull_type[4];
155 struct device_node *of_node;
156 struct rockchip_pinctrl *drvdata;
157 struct irq_domain *domain;
158 struct gpio_chip gpio_chip;
159 struct pinctrl_gpio_range grange;
160 raw_spinlock_t slock;
161 u32 toggle_edge_mode;
166 #define PIN_BANK(id, pins, label) \
179 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
185 { .type = iom0, .offset = -1 }, \
186 { .type = iom1, .offset = -1 }, \
187 { .type = iom2, .offset = -1 }, \
188 { .type = iom3, .offset = -1 }, \
192 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
204 { .drv_type = type0, .offset = -1 }, \
205 { .drv_type = type1, .offset = -1 }, \
206 { .drv_type = type2, .offset = -1 }, \
207 { .drv_type = type3, .offset = -1 }, \
211 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
212 drv2, drv3, pull0, pull1, \
225 { .drv_type = drv0, .offset = -1 }, \
226 { .drv_type = drv1, .offset = -1 }, \
227 { .drv_type = drv2, .offset = -1 }, \
228 { .drv_type = drv3, .offset = -1 }, \
230 .pull_type[0] = pull0, \
231 .pull_type[1] = pull1, \
232 .pull_type[2] = pull2, \
233 .pull_type[3] = pull3, \
236 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
237 iom2, iom3, drv0, drv1, drv2, \
238 drv3, offset0, offset1, \
245 { .type = iom0, .offset = -1 }, \
246 { .type = iom1, .offset = -1 }, \
247 { .type = iom2, .offset = -1 }, \
248 { .type = iom3, .offset = -1 }, \
251 { .drv_type = drv0, .offset = offset0 }, \
252 { .drv_type = drv1, .offset = offset1 }, \
253 { .drv_type = drv2, .offset = offset2 }, \
254 { .drv_type = drv3, .offset = offset3 }, \
258 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
259 label, iom0, iom1, iom2, \
260 iom3, drv0, drv1, drv2, \
261 drv3, offset0, offset1, \
262 offset2, offset3, pull0, \
263 pull1, pull2, pull3) \
269 { .type = iom0, .offset = -1 }, \
270 { .type = iom1, .offset = -1 }, \
271 { .type = iom2, .offset = -1 }, \
272 { .type = iom3, .offset = -1 }, \
275 { .drv_type = drv0, .offset = offset0 }, \
276 { .drv_type = drv1, .offset = offset1 }, \
277 { .drv_type = drv2, .offset = offset2 }, \
278 { .drv_type = drv3, .offset = offset3 }, \
280 .pull_type[0] = pull0, \
281 .pull_type[1] = pull1, \
282 .pull_type[2] = pull2, \
283 .pull_type[3] = pull3, \
287 * struct rockchip_mux_recalced_data: represent a pin iomux data.
290 * @bit: index at register.
291 * @reg: register offset.
294 struct rockchip_mux_recalced_data {
302 enum rockchip_mux_route_location {
303 ROCKCHIP_ROUTE_SAME = 0,
309 * struct rockchip_mux_recalced_data: represent a pin iomux data.
310 * @bank_num: bank number.
311 * @pin: index at register or used to calc index.
312 * @func: the min pin.
313 * @route_offset: the max pin.
314 * @route_val: the register offset.
316 struct rockchip_mux_route_data {
320 enum rockchip_mux_route_location route_location;
327 struct rockchip_pin_ctrl {
328 struct rockchip_pin_bank *pin_banks;
332 enum rockchip_pinctrl_type type;
337 struct rockchip_mux_recalced_data *iomux_recalced;
339 struct rockchip_mux_route_data *iomux_routes;
342 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
343 int pin_num, struct regmap **regmap,
345 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
346 int pin_num, struct regmap **regmap,
348 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
349 int pin_num, struct regmap **regmap,
353 struct rockchip_pin_config {
355 unsigned long *configs;
356 unsigned int nconfigs;
360 * struct rockchip_pin_group: represent group of pins of a pinmux function.
361 * @name: name of the pin group, used to lookup the group.
362 * @pins: the pins included in this group.
363 * @npins: number of pins included in this group.
364 * @func: the mux function number to be programmed when selected.
365 * @configs: the config values to be set for each pin
366 * @nconfigs: number of configs for each pin
368 struct rockchip_pin_group {
372 struct rockchip_pin_config *data;
376 * struct rockchip_pmx_func: represent a pin function.
377 * @name: name of the pin function, used to lookup the function.
378 * @groups: one or more names of pin groups that provide this function.
379 * @num_groups: number of groups included in @groups.
381 struct rockchip_pmx_func {
387 struct rockchip_pinctrl {
388 struct regmap *regmap_base;
390 struct regmap *regmap_pull;
391 struct regmap *regmap_pmu;
393 struct rockchip_pin_ctrl *ctrl;
394 struct pinctrl_desc pctl;
395 struct pinctrl_dev *pctl_dev;
396 struct rockchip_pin_group *groups;
397 unsigned int ngroups;
398 struct rockchip_pmx_func *functions;
399 unsigned int nfunctions;
402 static struct regmap_config rockchip_regmap_config = {
408 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
409 const struct rockchip_pinctrl *info,
414 for (i = 0; i < info->ngroups; i++) {
415 if (!strcmp(info->groups[i].name, name))
416 return &info->groups[i];
423 * given a pin number that is local to a pin controller, find out the pin bank
424 * and the register base of the pin bank.
426 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
429 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
431 while (pin >= (b->pin_base + b->nr_pins))
437 static struct rockchip_pin_bank *bank_num_to_bank(
438 struct rockchip_pinctrl *info,
441 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
444 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
445 if (b->bank_num == num)
449 return ERR_PTR(-EINVAL);
453 * Pinctrl_ops handling
456 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
460 return info->ngroups;
463 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
468 return info->groups[selector].name;
471 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
472 unsigned selector, const unsigned **pins,
475 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
477 if (selector >= info->ngroups)
480 *pins = info->groups[selector].pins;
481 *npins = info->groups[selector].npins;
486 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np,
488 struct pinctrl_map **map, unsigned *num_maps)
490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
491 const struct rockchip_pin_group *grp;
492 struct pinctrl_map *new_map;
493 struct device_node *parent;
498 * first find the group of this node and check if we need to create
499 * config maps for pins
501 grp = pinctrl_name_to_group(info, np->name);
503 dev_err(info->dev, "unable to find group for node %pOFn\n",
508 map_num += grp->npins;
510 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
518 parent = of_get_parent(np);
523 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
524 new_map[0].data.mux.function = parent->name;
525 new_map[0].data.mux.group = np->name;
528 /* create config map */
530 for (i = 0; i < grp->npins; i++) {
531 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
532 new_map[i].data.configs.group_or_pin =
533 pin_get_name(pctldev, grp->pins[i]);
534 new_map[i].data.configs.configs = grp->data[i].configs;
535 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
538 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
539 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
544 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
545 struct pinctrl_map *map, unsigned num_maps)
550 static const struct pinctrl_ops rockchip_pctrl_ops = {
551 .get_groups_count = rockchip_get_groups_count,
552 .get_group_name = rockchip_get_group_name,
553 .get_group_pins = rockchip_get_group_pins,
554 .dt_node_to_map = rockchip_dt_node_to_map,
555 .dt_free_map = rockchip_dt_free_map,
562 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
626 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
660 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
682 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
683 int *reg, u8 *bit, int *mask)
685 struct rockchip_pinctrl *info = bank->drvdata;
686 struct rockchip_pin_ctrl *ctrl = info->ctrl;
687 struct rockchip_mux_recalced_data *data;
690 for (i = 0; i < ctrl->niomux_recalced; i++) {
691 data = &ctrl->iomux_recalced[i];
692 if (data->num == bank->bank_num &&
697 if (i >= ctrl->niomux_recalced)
705 static struct rockchip_mux_route_data px30_mux_route_data[] = {
711 .route_offset = 0x184,
712 .route_val = BIT(16 + 7),
718 .route_offset = 0x184,
719 .route_val = BIT(16 + 7) | BIT(7),
725 .route_offset = 0x184,
726 .route_val = BIT(16 + 8),
732 .route_offset = 0x184,
733 .route_val = BIT(16 + 8) | BIT(8),
739 .route_offset = 0x184,
740 .route_val = BIT(16 + 10),
746 .route_offset = 0x184,
747 .route_val = BIT(16 + 10) | BIT(10),
753 .route_offset = 0x184,
754 .route_val = BIT(16 + 9),
760 .route_offset = 0x184,
761 .route_val = BIT(16 + 9) | BIT(9),
765 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
771 .route_offset = 0x144,
772 .route_val = BIT(16 + 3) | BIT(16 + 4),
778 .route_offset = 0x144,
779 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
785 .route_offset = 0x144,
786 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
792 .route_offset = 0x144,
793 .route_val = BIT(16 + 5),
799 .route_offset = 0x144,
800 .route_val = BIT(16 + 5) | BIT(5),
806 .route_offset = 0x144,
807 .route_val = BIT(16 + 6),
813 .route_offset = 0x144,
814 .route_val = BIT(16 + 6) | BIT(6),
818 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
820 /* non-iomuxed emmc/flash pins on flash-dqs */
824 .route_location = ROCKCHIP_ROUTE_GRF,
825 .route_offset = 0xa0,
826 .route_val = BIT(16 + 11),
828 /* non-iomuxed emmc/flash pins on emmc-clk */
832 .route_location = ROCKCHIP_ROUTE_GRF,
833 .route_offset = 0xa0,
834 .route_val = BIT(16 + 11) | BIT(11),
838 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
844 .route_offset = 0x50,
845 .route_val = BIT(16),
851 .route_offset = 0x50,
852 .route_val = BIT(16) | BIT(0),
858 .route_offset = 0x50,
859 .route_val = BIT(16 + 1),
865 .route_offset = 0x50,
866 .route_val = BIT(16 + 1) | BIT(1),
872 .route_offset = 0x50,
873 .route_val = BIT(16 + 2),
879 .route_offset = 0x50,
880 .route_val = BIT(16 + 2) | BIT(2),
886 .route_offset = 0x50,
887 .route_val = BIT(16 + 3),
893 .route_offset = 0x50,
894 .route_val = BIT(16 + 3) | BIT(3),
900 .route_offset = 0x50,
901 .route_val = BIT(16 + 4),
907 .route_offset = 0x50,
908 .route_val = BIT(16 + 4) | BIT(4),
914 .route_offset = 0x50,
915 .route_val = BIT(16 + 5),
921 .route_offset = 0x50,
922 .route_val = BIT(16 + 5) | BIT(5),
928 .route_offset = 0x50,
929 .route_val = BIT(16 + 7),
935 .route_offset = 0x50,
936 .route_val = BIT(16 + 7) | BIT(7),
942 .route_offset = 0x50,
943 .route_val = BIT(16 + 8),
949 .route_offset = 0x50,
950 .route_val = BIT(16 + 8) | BIT(8),
956 .route_offset = 0x50,
957 .route_val = BIT(16 + 11),
963 .route_offset = 0x50,
964 .route_val = BIT(16 + 11) | BIT(11),
968 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
970 /* edphdmi_cecinoutt1 */
974 .route_offset = 0x264,
975 .route_val = BIT(16 + 12) | BIT(12),
977 /* edphdmi_cecinout */
981 .route_offset = 0x264,
982 .route_val = BIT(16 + 12),
986 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
992 .route_offset = 0x50,
993 .route_val = BIT(16) | BIT(16 + 1),
999 .route_offset = 0x50,
1000 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1006 .route_offset = 0x50,
1007 .route_val = BIT(16 + 2) | BIT(2),
1009 /* gmac-m1-optimized_rxd3 */
1013 .route_offset = 0x50,
1014 .route_val = BIT(16 + 10) | BIT(10),
1020 .route_offset = 0x50,
1021 .route_val = BIT(16 + 3),
1027 .route_offset = 0x50,
1028 .route_val = BIT(16 + 3) | BIT(3),
1034 .route_offset = 0x50,
1035 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1041 .route_offset = 0x50,
1042 .route_val = BIT(16 + 6),
1048 .route_offset = 0x50,
1049 .route_val = BIT(16 + 6) | BIT(6),
1055 .route_offset = 0x50,
1056 .route_val = BIT(16 + 7) | BIT(7),
1062 .route_offset = 0x50,
1063 .route_val = BIT(16 + 8) | BIT(8),
1069 .route_offset = 0x50,
1070 .route_val = BIT(16 + 9) | BIT(9),
1074 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1080 .route_offset = 0xe21c,
1081 .route_val = BIT(16 + 10) | BIT(16 + 11),
1087 .route_offset = 0xe21c,
1088 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1094 .route_offset = 0xe21c,
1095 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1101 .route_offset = 0xe21c,
1102 .route_val = BIT(16 + 14),
1108 .route_offset = 0xe21c,
1109 .route_val = BIT(16 + 14) | BIT(14),
1113 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1114 int mux, u32 *loc, u32 *reg, u32 *value)
1116 struct rockchip_pinctrl *info = bank->drvdata;
1117 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1118 struct rockchip_mux_route_data *data;
1121 for (i = 0; i < ctrl->niomux_routes; i++) {
1122 data = &ctrl->iomux_routes[i];
1123 if ((data->bank_num == bank->bank_num) &&
1124 (data->pin == pin) && (data->func == mux))
1128 if (i >= ctrl->niomux_routes)
1131 *loc = data->route_location;
1132 *reg = data->route_offset;
1133 *value = data->route_val;
1138 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1140 struct rockchip_pinctrl *info = bank->drvdata;
1141 int iomux_num = (pin / 8);
1142 struct regmap *regmap;
1144 int reg, ret, mask, mux_type;
1150 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1151 dev_err(info->dev, "pin %d is unrouted\n", pin);
1155 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1156 return RK_FUNC_GPIO;
1158 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1159 ? info->regmap_pmu : info->regmap_base;
1161 /* get basic quadrupel of mux registers and the correct reg inside */
1162 mux_type = bank->iomux[iomux_num].type;
1163 reg = bank->iomux[iomux_num].offset;
1164 if (mux_type & IOMUX_WIDTH_4BIT) {
1167 bit = (pin % 4) * 4;
1169 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1172 bit = (pin % 8 % 5) * 3;
1175 bit = (pin % 8) * 2;
1179 if (bank->recalced_mask & BIT(pin))
1180 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1182 ret = regmap_read(regmap, reg, &val);
1186 return ((val >> bit) & mask);
1189 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1192 struct rockchip_pinctrl *info = bank->drvdata;
1193 int iomux_num = (pin / 8);
1198 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1199 dev_err(info->dev, "pin %d is unrouted\n", pin);
1203 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1204 if (mux != RK_FUNC_GPIO) {
1206 "pin %d only supports a gpio mux\n", pin);
1215 * Set a new mux function for a pin.
1217 * The register is divided into the upper and lower 16 bit. When changing
1218 * a value, the previous register value is not read and changed. Instead
1219 * it seems the changed bits are marked in the upper 16 bit, while the
1220 * changed value gets set in the same offset in the lower 16 bit.
1221 * All pin settings seem to be 2 bit wide in both the upper and lower
1223 * @bank: pin bank to change
1224 * @pin: pin to change
1225 * @mux: new mux function to set
1227 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1229 struct rockchip_pinctrl *info = bank->drvdata;
1230 int iomux_num = (pin / 8);
1231 struct regmap *regmap;
1232 int reg, ret, mask, mux_type;
1234 u32 data, rmask, route_location, route_reg, route_val;
1236 ret = rockchip_verify_mux(bank, pin, mux);
1240 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1243 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1244 bank->bank_num, pin, mux);
1246 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1247 ? info->regmap_pmu : info->regmap_base;
1249 /* get basic quadrupel of mux registers and the correct reg inside */
1250 mux_type = bank->iomux[iomux_num].type;
1251 reg = bank->iomux[iomux_num].offset;
1252 if (mux_type & IOMUX_WIDTH_4BIT) {
1255 bit = (pin % 4) * 4;
1257 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1260 bit = (pin % 8 % 5) * 3;
1263 bit = (pin % 8) * 2;
1267 if (bank->recalced_mask & BIT(pin))
1268 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1270 if (bank->route_mask & BIT(pin)) {
1271 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1272 &route_reg, &route_val)) {
1273 struct regmap *route_regmap = regmap;
1275 /* handle special locations */
1276 switch (route_location) {
1277 case ROCKCHIP_ROUTE_PMU:
1278 route_regmap = info->regmap_pmu;
1280 case ROCKCHIP_ROUTE_GRF:
1281 route_regmap = info->regmap_base;
1285 ret = regmap_write(route_regmap, route_reg, route_val);
1291 data = (mask << (bit + 16));
1292 rmask = data | (data >> 16);
1293 data |= (mux & mask) << bit;
1294 ret = regmap_update_bits(regmap, reg, rmask, data);
1299 #define PX30_PULL_PMU_OFFSET 0x10
1300 #define PX30_PULL_GRF_OFFSET 0x60
1301 #define PX30_PULL_BITS_PER_PIN 2
1302 #define PX30_PULL_PINS_PER_REG 8
1303 #define PX30_PULL_BANK_STRIDE 16
1305 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1306 int pin_num, struct regmap **regmap,
1309 struct rockchip_pinctrl *info = bank->drvdata;
1311 /* The first 32 pins of the first bank are located in PMU */
1312 if (bank->bank_num == 0) {
1313 *regmap = info->regmap_pmu;
1314 *reg = PX30_PULL_PMU_OFFSET;
1316 *regmap = info->regmap_base;
1317 *reg = PX30_PULL_GRF_OFFSET;
1319 /* correct the offset, as we're starting with the 2nd bank */
1321 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1324 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1325 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1326 *bit *= PX30_PULL_BITS_PER_PIN;
1329 #define PX30_DRV_PMU_OFFSET 0x20
1330 #define PX30_DRV_GRF_OFFSET 0xf0
1331 #define PX30_DRV_BITS_PER_PIN 2
1332 #define PX30_DRV_PINS_PER_REG 8
1333 #define PX30_DRV_BANK_STRIDE 16
1335 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1336 int pin_num, struct regmap **regmap,
1339 struct rockchip_pinctrl *info = bank->drvdata;
1341 /* The first 32 pins of the first bank are located in PMU */
1342 if (bank->bank_num == 0) {
1343 *regmap = info->regmap_pmu;
1344 *reg = PX30_DRV_PMU_OFFSET;
1346 *regmap = info->regmap_base;
1347 *reg = PX30_DRV_GRF_OFFSET;
1349 /* correct the offset, as we're starting with the 2nd bank */
1351 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1354 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1355 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1356 *bit *= PX30_DRV_BITS_PER_PIN;
1359 #define PX30_SCHMITT_PMU_OFFSET 0x38
1360 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1361 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1362 #define PX30_SCHMITT_BANK_STRIDE 16
1363 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1365 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1367 struct regmap **regmap,
1370 struct rockchip_pinctrl *info = bank->drvdata;
1373 if (bank->bank_num == 0) {
1374 *regmap = info->regmap_pmu;
1375 *reg = PX30_SCHMITT_PMU_OFFSET;
1376 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1378 *regmap = info->regmap_base;
1379 *reg = PX30_SCHMITT_GRF_OFFSET;
1380 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1381 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1384 *reg += ((pin_num / pins_per_reg) * 4);
1385 *bit = pin_num % pins_per_reg;
1390 #define RV1108_PULL_PMU_OFFSET 0x10
1391 #define RV1108_PULL_OFFSET 0x110
1392 #define RV1108_PULL_PINS_PER_REG 8
1393 #define RV1108_PULL_BITS_PER_PIN 2
1394 #define RV1108_PULL_BANK_STRIDE 16
1396 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1397 int pin_num, struct regmap **regmap,
1400 struct rockchip_pinctrl *info = bank->drvdata;
1402 /* The first 24 pins of the first bank are located in PMU */
1403 if (bank->bank_num == 0) {
1404 *regmap = info->regmap_pmu;
1405 *reg = RV1108_PULL_PMU_OFFSET;
1407 *reg = RV1108_PULL_OFFSET;
1408 *regmap = info->regmap_base;
1409 /* correct the offset, as we're starting with the 2nd bank */
1411 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1414 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1415 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1416 *bit *= RV1108_PULL_BITS_PER_PIN;
1419 #define RV1108_DRV_PMU_OFFSET 0x20
1420 #define RV1108_DRV_GRF_OFFSET 0x210
1421 #define RV1108_DRV_BITS_PER_PIN 2
1422 #define RV1108_DRV_PINS_PER_REG 8
1423 #define RV1108_DRV_BANK_STRIDE 16
1425 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1426 int pin_num, struct regmap **regmap,
1429 struct rockchip_pinctrl *info = bank->drvdata;
1431 /* The first 24 pins of the first bank are located in PMU */
1432 if (bank->bank_num == 0) {
1433 *regmap = info->regmap_pmu;
1434 *reg = RV1108_DRV_PMU_OFFSET;
1436 *regmap = info->regmap_base;
1437 *reg = RV1108_DRV_GRF_OFFSET;
1439 /* correct the offset, as we're starting with the 2nd bank */
1441 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1444 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1445 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1446 *bit *= RV1108_DRV_BITS_PER_PIN;
1449 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1450 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1451 #define RV1108_SCHMITT_BANK_STRIDE 8
1452 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1453 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1455 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1457 struct regmap **regmap,
1460 struct rockchip_pinctrl *info = bank->drvdata;
1463 if (bank->bank_num == 0) {
1464 *regmap = info->regmap_pmu;
1465 *reg = RV1108_SCHMITT_PMU_OFFSET;
1466 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1468 *regmap = info->regmap_base;
1469 *reg = RV1108_SCHMITT_GRF_OFFSET;
1470 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1471 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1473 *reg += ((pin_num / pins_per_reg) * 4);
1474 *bit = pin_num % pins_per_reg;
1479 #define RK2928_PULL_OFFSET 0x118
1480 #define RK2928_PULL_PINS_PER_REG 16
1481 #define RK2928_PULL_BANK_STRIDE 8
1483 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1484 int pin_num, struct regmap **regmap,
1487 struct rockchip_pinctrl *info = bank->drvdata;
1489 *regmap = info->regmap_base;
1490 *reg = RK2928_PULL_OFFSET;
1491 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1492 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1494 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1497 #define RK3128_PULL_OFFSET 0x118
1499 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1500 int pin_num, struct regmap **regmap,
1503 struct rockchip_pinctrl *info = bank->drvdata;
1505 *regmap = info->regmap_base;
1506 *reg = RK3128_PULL_OFFSET;
1507 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1508 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1510 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1513 #define RK3188_PULL_OFFSET 0x164
1514 #define RK3188_PULL_BITS_PER_PIN 2
1515 #define RK3188_PULL_PINS_PER_REG 8
1516 #define RK3188_PULL_BANK_STRIDE 16
1517 #define RK3188_PULL_PMU_OFFSET 0x64
1519 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1520 int pin_num, struct regmap **regmap,
1523 struct rockchip_pinctrl *info = bank->drvdata;
1525 /* The first 12 pins of the first bank are located elsewhere */
1526 if (bank->bank_num == 0 && pin_num < 12) {
1527 *regmap = info->regmap_pmu ? info->regmap_pmu
1528 : bank->regmap_pull;
1529 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1530 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1531 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1532 *bit *= RK3188_PULL_BITS_PER_PIN;
1534 *regmap = info->regmap_pull ? info->regmap_pull
1535 : info->regmap_base;
1536 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1538 /* correct the offset, as it is the 2nd pull register */
1540 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1541 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1544 * The bits in these registers have an inverse ordering
1545 * with the lowest pin being in bits 15:14 and the highest
1548 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1549 *bit *= RK3188_PULL_BITS_PER_PIN;
1553 #define RK3288_PULL_OFFSET 0x140
1554 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1555 int pin_num, struct regmap **regmap,
1558 struct rockchip_pinctrl *info = bank->drvdata;
1560 /* The first 24 pins of the first bank are located in PMU */
1561 if (bank->bank_num == 0) {
1562 *regmap = info->regmap_pmu;
1563 *reg = RK3188_PULL_PMU_OFFSET;
1565 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1566 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1567 *bit *= RK3188_PULL_BITS_PER_PIN;
1569 *regmap = info->regmap_base;
1570 *reg = RK3288_PULL_OFFSET;
1572 /* correct the offset, as we're starting with the 2nd bank */
1574 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1575 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1577 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1578 *bit *= RK3188_PULL_BITS_PER_PIN;
1582 #define RK3288_DRV_PMU_OFFSET 0x70
1583 #define RK3288_DRV_GRF_OFFSET 0x1c0
1584 #define RK3288_DRV_BITS_PER_PIN 2
1585 #define RK3288_DRV_PINS_PER_REG 8
1586 #define RK3288_DRV_BANK_STRIDE 16
1588 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1589 int pin_num, struct regmap **regmap,
1592 struct rockchip_pinctrl *info = bank->drvdata;
1594 /* The first 24 pins of the first bank are located in PMU */
1595 if (bank->bank_num == 0) {
1596 *regmap = info->regmap_pmu;
1597 *reg = RK3288_DRV_PMU_OFFSET;
1599 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1600 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1601 *bit *= RK3288_DRV_BITS_PER_PIN;
1603 *regmap = info->regmap_base;
1604 *reg = RK3288_DRV_GRF_OFFSET;
1606 /* correct the offset, as we're starting with the 2nd bank */
1608 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1609 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1611 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1612 *bit *= RK3288_DRV_BITS_PER_PIN;
1616 #define RK3228_PULL_OFFSET 0x100
1618 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1619 int pin_num, struct regmap **regmap,
1622 struct rockchip_pinctrl *info = bank->drvdata;
1624 *regmap = info->regmap_base;
1625 *reg = RK3228_PULL_OFFSET;
1626 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1627 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1629 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1630 *bit *= RK3188_PULL_BITS_PER_PIN;
1633 #define RK3228_DRV_GRF_OFFSET 0x200
1635 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1636 int pin_num, struct regmap **regmap,
1639 struct rockchip_pinctrl *info = bank->drvdata;
1641 *regmap = info->regmap_base;
1642 *reg = RK3228_DRV_GRF_OFFSET;
1643 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1644 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1646 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1647 *bit *= RK3288_DRV_BITS_PER_PIN;
1650 #define RK3368_PULL_GRF_OFFSET 0x100
1651 #define RK3368_PULL_PMU_OFFSET 0x10
1653 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1654 int pin_num, struct regmap **regmap,
1657 struct rockchip_pinctrl *info = bank->drvdata;
1659 /* The first 32 pins of the first bank are located in PMU */
1660 if (bank->bank_num == 0) {
1661 *regmap = info->regmap_pmu;
1662 *reg = RK3368_PULL_PMU_OFFSET;
1664 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1665 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1666 *bit *= RK3188_PULL_BITS_PER_PIN;
1668 *regmap = info->regmap_base;
1669 *reg = RK3368_PULL_GRF_OFFSET;
1671 /* correct the offset, as we're starting with the 2nd bank */
1673 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1674 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1676 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1677 *bit *= RK3188_PULL_BITS_PER_PIN;
1681 #define RK3368_DRV_PMU_OFFSET 0x20
1682 #define RK3368_DRV_GRF_OFFSET 0x200
1684 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1685 int pin_num, struct regmap **regmap,
1688 struct rockchip_pinctrl *info = bank->drvdata;
1690 /* The first 32 pins of the first bank are located in PMU */
1691 if (bank->bank_num == 0) {
1692 *regmap = info->regmap_pmu;
1693 *reg = RK3368_DRV_PMU_OFFSET;
1695 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1696 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1697 *bit *= RK3288_DRV_BITS_PER_PIN;
1699 *regmap = info->regmap_base;
1700 *reg = RK3368_DRV_GRF_OFFSET;
1702 /* correct the offset, as we're starting with the 2nd bank */
1704 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1705 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1707 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1708 *bit *= RK3288_DRV_BITS_PER_PIN;
1712 #define RK3399_PULL_GRF_OFFSET 0xe040
1713 #define RK3399_PULL_PMU_OFFSET 0x40
1714 #define RK3399_DRV_3BITS_PER_PIN 3
1716 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1717 int pin_num, struct regmap **regmap,
1720 struct rockchip_pinctrl *info = bank->drvdata;
1722 /* The bank0:16 and bank1:32 pins are located in PMU */
1723 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1724 *regmap = info->regmap_pmu;
1725 *reg = RK3399_PULL_PMU_OFFSET;
1727 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1729 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1730 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1731 *bit *= RK3188_PULL_BITS_PER_PIN;
1733 *regmap = info->regmap_base;
1734 *reg = RK3399_PULL_GRF_OFFSET;
1736 /* correct the offset, as we're starting with the 3rd bank */
1738 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1739 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1741 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1742 *bit *= RK3188_PULL_BITS_PER_PIN;
1746 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1747 int pin_num, struct regmap **regmap,
1750 struct rockchip_pinctrl *info = bank->drvdata;
1751 int drv_num = (pin_num / 8);
1753 /* The bank0:16 and bank1:32 pins are located in PMU */
1754 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1755 *regmap = info->regmap_pmu;
1757 *regmap = info->regmap_base;
1759 *reg = bank->drv[drv_num].offset;
1760 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1761 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1762 *bit = (pin_num % 8) * 3;
1764 *bit = (pin_num % 8) * 2;
1767 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1768 { 2, 4, 8, 12, -1, -1, -1, -1 },
1769 { 3, 6, 9, 12, -1, -1, -1, -1 },
1770 { 5, 10, 15, 20, -1, -1, -1, -1 },
1771 { 4, 6, 8, 10, 12, 14, 16, 18 },
1772 { 4, 7, 10, 13, 16, 19, 22, 26 }
1775 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1778 struct rockchip_pinctrl *info = bank->drvdata;
1779 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1780 struct regmap *regmap;
1782 u32 data, temp, rmask_bits;
1784 int drv_type = bank->drv[pin_num / 8].drv_type;
1786 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1789 case DRV_TYPE_IO_1V8_3V0_AUTO:
1790 case DRV_TYPE_IO_3V3_ONLY:
1791 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1794 /* regular case, nothing to do */
1798 * drive-strength offset is special, as it is
1799 * spread over 2 registers
1801 ret = regmap_read(regmap, reg, &data);
1805 ret = regmap_read(regmap, reg + 0x4, &temp);
1810 * the bit data[15] contains bit 0 of the value
1811 * while temp[1:0] contains bits 2 and 1
1818 return rockchip_perpin_drv_list[drv_type][data];
1820 /* setting fully enclosed in the second register */
1825 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1831 case DRV_TYPE_IO_DEFAULT:
1832 case DRV_TYPE_IO_1V8_OR_3V0:
1833 case DRV_TYPE_IO_1V8_ONLY:
1834 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1837 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1842 ret = regmap_read(regmap, reg, &data);
1847 data &= (1 << rmask_bits) - 1;
1849 return rockchip_perpin_drv_list[drv_type][data];
1852 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1853 int pin_num, int strength)
1855 struct rockchip_pinctrl *info = bank->drvdata;
1856 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1857 struct regmap *regmap;
1859 u32 data, rmask, rmask_bits, temp;
1861 int drv_type = bank->drv[pin_num / 8].drv_type;
1863 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1864 bank->bank_num, pin_num, strength);
1866 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1869 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1870 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1873 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1874 ret = rockchip_perpin_drv_list[drv_type][i];
1880 dev_err(info->dev, "unsupported driver strength %d\n",
1886 case DRV_TYPE_IO_1V8_3V0_AUTO:
1887 case DRV_TYPE_IO_3V3_ONLY:
1888 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1891 /* regular case, nothing to do */
1895 * drive-strength offset is special, as it is spread
1896 * over 2 registers, the bit data[15] contains bit 0
1897 * of the value while temp[1:0] contains bits 2 and 1
1899 data = (ret & 0x1) << 15;
1900 temp = (ret >> 0x1) & 0x3;
1902 rmask = BIT(15) | BIT(31);
1904 ret = regmap_update_bits(regmap, reg, rmask, data);
1908 rmask = 0x3 | (0x3 << 16);
1909 temp |= (0x3 << 16);
1911 ret = regmap_update_bits(regmap, reg, rmask, temp);
1915 /* setting fully enclosed in the second register */
1920 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1925 case DRV_TYPE_IO_DEFAULT:
1926 case DRV_TYPE_IO_1V8_OR_3V0:
1927 case DRV_TYPE_IO_1V8_ONLY:
1928 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1931 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1936 /* enable the write to the equivalent lower bits */
1937 data = ((1 << rmask_bits) - 1) << (bit + 16);
1938 rmask = data | (data >> 16);
1939 data |= (ret << bit);
1941 ret = regmap_update_bits(regmap, reg, rmask, data);
1946 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1948 PIN_CONFIG_BIAS_DISABLE,
1949 PIN_CONFIG_BIAS_PULL_UP,
1950 PIN_CONFIG_BIAS_PULL_DOWN,
1951 PIN_CONFIG_BIAS_BUS_HOLD
1954 PIN_CONFIG_BIAS_DISABLE,
1955 PIN_CONFIG_BIAS_PULL_DOWN,
1956 PIN_CONFIG_BIAS_DISABLE,
1957 PIN_CONFIG_BIAS_PULL_UP
1961 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1963 struct rockchip_pinctrl *info = bank->drvdata;
1964 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1965 struct regmap *regmap;
1966 int reg, ret, pull_type;
1970 /* rk3066b does support any pulls */
1971 if (ctrl->type == RK3066B)
1972 return PIN_CONFIG_BIAS_DISABLE;
1974 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1976 ret = regmap_read(regmap, reg, &data);
1980 switch (ctrl->type) {
1983 return !(data & BIT(bit))
1984 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1985 : PIN_CONFIG_BIAS_DISABLE;
1992 pull_type = bank->pull_type[pin_num / 8];
1994 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1996 return rockchip_pull_list[pull_type][data];
1998 dev_err(info->dev, "unsupported pinctrl type\n");
2003 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2004 int pin_num, int pull)
2006 struct rockchip_pinctrl *info = bank->drvdata;
2007 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2008 struct regmap *regmap;
2009 int reg, ret, i, pull_type;
2013 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2014 bank->bank_num, pin_num, pull);
2016 /* rk3066b does support any pulls */
2017 if (ctrl->type == RK3066B)
2018 return pull ? -EINVAL : 0;
2020 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2022 switch (ctrl->type) {
2025 data = BIT(bit + 16);
2026 if (pull == PIN_CONFIG_BIAS_DISABLE)
2028 ret = regmap_write(regmap, reg, data);
2036 pull_type = bank->pull_type[pin_num / 8];
2038 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2040 if (rockchip_pull_list[pull_type][i] == pull) {
2047 dev_err(info->dev, "unsupported pull setting %d\n",
2052 /* enable the write to the equivalent lower bits */
2053 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2054 rmask = data | (data >> 16);
2055 data |= (ret << bit);
2057 ret = regmap_update_bits(regmap, reg, rmask, data);
2060 dev_err(info->dev, "unsupported pinctrl type\n");
2067 #define RK3328_SCHMITT_BITS_PER_PIN 1
2068 #define RK3328_SCHMITT_PINS_PER_REG 16
2069 #define RK3328_SCHMITT_BANK_STRIDE 8
2070 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2072 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2074 struct regmap **regmap,
2077 struct rockchip_pinctrl *info = bank->drvdata;
2079 *regmap = info->regmap_base;
2080 *reg = RK3328_SCHMITT_GRF_OFFSET;
2082 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2083 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2084 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2089 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2091 struct rockchip_pinctrl *info = bank->drvdata;
2092 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2093 struct regmap *regmap;
2098 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2102 ret = regmap_read(regmap, reg, &data);
2110 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2111 int pin_num, int enable)
2113 struct rockchip_pinctrl *info = bank->drvdata;
2114 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2115 struct regmap *regmap;
2120 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2121 bank->bank_num, pin_num, enable);
2123 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2127 /* enable the write to the equivalent lower bits */
2128 data = BIT(bit + 16) | (enable << bit);
2129 rmask = BIT(bit + 16) | BIT(bit);
2131 return regmap_update_bits(regmap, reg, rmask, data);
2135 * Pinmux_ops handling
2138 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2140 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2142 return info->nfunctions;
2145 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2148 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2150 return info->functions[selector].name;
2153 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2154 unsigned selector, const char * const **groups,
2155 unsigned * const num_groups)
2157 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2159 *groups = info->functions[selector].groups;
2160 *num_groups = info->functions[selector].ngroups;
2165 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2168 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2169 const unsigned int *pins = info->groups[group].pins;
2170 const struct rockchip_pin_config *data = info->groups[group].data;
2171 struct rockchip_pin_bank *bank;
2174 dev_dbg(info->dev, "enable function %s group %s\n",
2175 info->functions[selector].name, info->groups[group].name);
2178 * for each pin in the pin group selected, program the corresponding
2179 * pin function number in the config register.
2181 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2182 bank = pin_to_bank(info, pins[cnt]);
2183 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2190 /* revert the already done pin settings */
2191 for (cnt--; cnt >= 0; cnt--)
2192 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2200 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2202 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2206 ret = clk_enable(bank->clk);
2208 dev_err(bank->drvdata->dev,
2209 "failed to enable clock for bank %s\n", bank->name);
2212 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2213 clk_disable(bank->clk);
2215 return !(data & BIT(offset));
2219 * The calls to gpio_direction_output() and gpio_direction_input()
2220 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2221 * function called from the gpiolib interface).
2223 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2224 int pin, bool input)
2226 struct rockchip_pin_bank *bank;
2228 unsigned long flags;
2231 bank = gpiochip_get_data(chip);
2233 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2237 clk_enable(bank->clk);
2238 raw_spin_lock_irqsave(&bank->slock, flags);
2240 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2241 /* set bit to 1 for output, 0 for input */
2246 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2248 raw_spin_unlock_irqrestore(&bank->slock, flags);
2249 clk_disable(bank->clk);
2254 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2255 struct pinctrl_gpio_range *range,
2256 unsigned offset, bool input)
2258 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2259 struct gpio_chip *chip;
2263 pin = offset - chip->base;
2264 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2265 offset, range->name, pin, input ? "input" : "output");
2267 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2271 static const struct pinmux_ops rockchip_pmx_ops = {
2272 .get_functions_count = rockchip_pmx_get_funcs_count,
2273 .get_function_name = rockchip_pmx_get_func_name,
2274 .get_function_groups = rockchip_pmx_get_groups,
2275 .set_mux = rockchip_pmx_set,
2276 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2280 * Pinconf_ops handling
2283 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2284 enum pin_config_param pull)
2286 switch (ctrl->type) {
2289 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2290 pull == PIN_CONFIG_BIAS_DISABLE);
2292 return pull ? false : true;
2299 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2305 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2306 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2308 /* set the pin config settings for a specified pin */
2309 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2310 unsigned long *configs, unsigned num_configs)
2312 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2313 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2314 enum pin_config_param param;
2319 for (i = 0; i < num_configs; i++) {
2320 param = pinconf_to_config_param(configs[i]);
2321 arg = pinconf_to_config_argument(configs[i]);
2324 case PIN_CONFIG_BIAS_DISABLE:
2325 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2330 case PIN_CONFIG_BIAS_PULL_UP:
2331 case PIN_CONFIG_BIAS_PULL_DOWN:
2332 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2333 case PIN_CONFIG_BIAS_BUS_HOLD:
2334 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2340 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2345 case PIN_CONFIG_OUTPUT:
2346 rockchip_gpio_set(&bank->gpio_chip,
2347 pin - bank->pin_base, arg);
2348 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2349 pin - bank->pin_base, false);
2353 case PIN_CONFIG_DRIVE_STRENGTH:
2354 /* rk3288 is the first with per-pin drive-strength */
2355 if (!info->ctrl->drv_calc_reg)
2358 rc = rockchip_set_drive_perpin(bank,
2359 pin - bank->pin_base, arg);
2363 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2364 if (!info->ctrl->schmitt_calc_reg)
2367 rc = rockchip_set_schmitt(bank,
2368 pin - bank->pin_base, arg);
2376 } /* for each config */
2381 /* get the pin config settings for a specified pin */
2382 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2383 unsigned long *config)
2385 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2386 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2387 enum pin_config_param param = pinconf_to_config_param(*config);
2392 case PIN_CONFIG_BIAS_DISABLE:
2393 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2398 case PIN_CONFIG_BIAS_PULL_UP:
2399 case PIN_CONFIG_BIAS_PULL_DOWN:
2400 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2401 case PIN_CONFIG_BIAS_BUS_HOLD:
2402 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2405 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2410 case PIN_CONFIG_OUTPUT:
2411 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2412 if (rc != RK_FUNC_GPIO)
2415 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2421 case PIN_CONFIG_DRIVE_STRENGTH:
2422 /* rk3288 is the first with per-pin drive-strength */
2423 if (!info->ctrl->drv_calc_reg)
2426 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2432 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2433 if (!info->ctrl->schmitt_calc_reg)
2436 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2447 *config = pinconf_to_config_packed(param, arg);
2452 static const struct pinconf_ops rockchip_pinconf_ops = {
2453 .pin_config_get = rockchip_pinconf_get,
2454 .pin_config_set = rockchip_pinconf_set,
2458 static const struct of_device_id rockchip_bank_match[] = {
2459 { .compatible = "rockchip,gpio-bank" },
2460 { .compatible = "rockchip,rk3188-gpio-bank0" },
2464 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2465 struct device_node *np)
2467 struct device_node *child;
2469 for_each_child_of_node(np, child) {
2470 if (of_match_node(rockchip_bank_match, child))
2474 info->ngroups += of_get_child_count(child);
2478 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2479 struct rockchip_pin_group *grp,
2480 struct rockchip_pinctrl *info,
2483 struct rockchip_pin_bank *bank;
2490 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2492 /* Initialise group */
2493 grp->name = np->name;
2496 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2497 * do sanity check and calculate pins number
2499 list = of_get_property(np, "rockchip,pins", &size);
2500 /* we do not check return since it's safe node passed down */
2501 size /= sizeof(*list);
2502 if (!size || size % 4) {
2503 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2507 grp->npins = size / 4;
2509 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2511 grp->data = devm_kcalloc(info->dev,
2513 sizeof(struct rockchip_pin_config),
2515 if (!grp->pins || !grp->data)
2518 for (i = 0, j = 0; i < size; i += 4, j++) {
2519 const __be32 *phandle;
2520 struct device_node *np_config;
2522 num = be32_to_cpu(*list++);
2523 bank = bank_num_to_bank(info, num);
2525 return PTR_ERR(bank);
2527 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2528 grp->data[j].func = be32_to_cpu(*list++);
2534 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2535 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2536 &grp->data[j].configs, &grp->data[j].nconfigs);
2544 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2545 struct rockchip_pinctrl *info,
2548 struct device_node *child;
2549 struct rockchip_pmx_func *func;
2550 struct rockchip_pin_group *grp;
2552 static u32 grp_index;
2555 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2557 func = &info->functions[index];
2559 /* Initialise function */
2560 func->name = np->name;
2561 func->ngroups = of_get_child_count(np);
2562 if (func->ngroups <= 0)
2565 func->groups = devm_kcalloc(info->dev,
2566 func->ngroups, sizeof(char *), GFP_KERNEL);
2570 for_each_child_of_node(np, child) {
2571 func->groups[i] = child->name;
2572 grp = &info->groups[grp_index++];
2573 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2583 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2584 struct rockchip_pinctrl *info)
2586 struct device *dev = &pdev->dev;
2587 struct device_node *np = dev->of_node;
2588 struct device_node *child;
2592 rockchip_pinctrl_child_count(info, np);
2594 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2595 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2597 info->functions = devm_kcalloc(dev,
2599 sizeof(struct rockchip_pmx_func),
2601 if (!info->functions)
2604 info->groups = devm_kcalloc(dev,
2606 sizeof(struct rockchip_pin_group),
2613 for_each_child_of_node(np, child) {
2614 if (of_match_node(rockchip_bank_match, child))
2617 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2619 dev_err(&pdev->dev, "failed to parse function\n");
2628 static int rockchip_pinctrl_register(struct platform_device *pdev,
2629 struct rockchip_pinctrl *info)
2631 struct pinctrl_desc *ctrldesc = &info->pctl;
2632 struct pinctrl_pin_desc *pindesc, *pdesc;
2633 struct rockchip_pin_bank *pin_bank;
2637 ctrldesc->name = "rockchip-pinctrl";
2638 ctrldesc->owner = THIS_MODULE;
2639 ctrldesc->pctlops = &rockchip_pctrl_ops;
2640 ctrldesc->pmxops = &rockchip_pmx_ops;
2641 ctrldesc->confops = &rockchip_pinconf_ops;
2643 pindesc = devm_kcalloc(&pdev->dev,
2644 info->ctrl->nr_pins, sizeof(*pindesc),
2649 ctrldesc->pins = pindesc;
2650 ctrldesc->npins = info->ctrl->nr_pins;
2653 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2654 pin_bank = &info->ctrl->pin_banks[bank];
2655 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2657 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2658 pin_bank->name, pin);
2663 ret = rockchip_pinctrl_parse_dt(pdev, info);
2667 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2668 if (IS_ERR(info->pctl_dev)) {
2669 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2670 return PTR_ERR(info->pctl_dev);
2673 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2674 pin_bank = &info->ctrl->pin_banks[bank];
2675 pin_bank->grange.name = pin_bank->name;
2676 pin_bank->grange.id = bank;
2677 pin_bank->grange.pin_base = pin_bank->pin_base;
2678 pin_bank->grange.base = pin_bank->gpio_chip.base;
2679 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2680 pin_bank->grange.gc = &pin_bank->gpio_chip;
2681 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2691 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2693 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2694 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2695 unsigned long flags;
2698 clk_enable(bank->clk);
2699 raw_spin_lock_irqsave(&bank->slock, flags);
2702 data &= ~BIT(offset);
2704 data |= BIT(offset);
2707 raw_spin_unlock_irqrestore(&bank->slock, flags);
2708 clk_disable(bank->clk);
2712 * Returns the level of the pin for input direction and setting of the DR
2713 * register for output gpios.
2715 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2717 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2720 clk_enable(bank->clk);
2721 data = readl(bank->reg_base + GPIO_EXT_PORT);
2722 clk_disable(bank->clk);
2729 * gpiolib gpio_direction_input callback function. The setting of the pin
2730 * mux function as 'gpio input' will be handled by the pinctrl subsystem
2733 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2735 return pinctrl_gpio_direction_input(gc->base + offset);
2739 * gpiolib gpio_direction_output callback function. The setting of the pin
2740 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2743 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2744 unsigned offset, int value)
2746 rockchip_gpio_set(gc, offset, value);
2747 return pinctrl_gpio_direction_output(gc->base + offset);
2750 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2751 unsigned int offset, bool enable)
2753 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2754 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2755 unsigned long flags;
2758 clk_enable(bank->clk);
2759 raw_spin_lock_irqsave(&bank->slock, flags);
2763 data |= BIT(offset);
2765 data &= ~BIT(offset);
2768 raw_spin_unlock_irqrestore(&bank->slock, flags);
2769 clk_disable(bank->clk);
2773 * gpiolib set_config callback function. The setting of the pin
2774 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2777 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2778 unsigned long config)
2780 enum pin_config_param param = pinconf_to_config_param(config);
2783 case PIN_CONFIG_INPUT_DEBOUNCE:
2784 rockchip_gpio_set_debounce(gc, offset, true);
2786 * Rockchip's gpio could only support up to one period
2787 * of the debounce clock(pclk), which is far away from
2788 * satisftying the requirement, as pclk is usually near
2789 * 100MHz shared by all peripherals. So the fact is it
2790 * has crippled debounce capability could only be useful
2791 * to prevent any spurious glitches from waking up the system
2792 * if the gpio is conguired as wakeup interrupt source. Let's
2793 * still return -ENOTSUPP as before, to make sure the caller
2794 * of gpiod_set_debounce won't change its behaviour.
2803 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2804 * and a virtual IRQ, if not already present.
2806 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2808 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2814 clk_enable(bank->clk);
2815 virq = irq_create_mapping(bank->domain, offset);
2816 clk_disable(bank->clk);
2818 return (virq) ? : -ENXIO;
2821 static const struct gpio_chip rockchip_gpiolib_chip = {
2822 .request = gpiochip_generic_request,
2823 .free = gpiochip_generic_free,
2824 .set = rockchip_gpio_set,
2825 .get = rockchip_gpio_get,
2826 .get_direction = rockchip_gpio_get_direction,
2827 .direction_input = rockchip_gpio_direction_input,
2828 .direction_output = rockchip_gpio_direction_output,
2829 .set_config = rockchip_gpio_set_config,
2830 .to_irq = rockchip_gpio_to_irq,
2831 .owner = THIS_MODULE,
2835 * Interrupt handling
2838 static void rockchip_irq_demux(struct irq_desc *desc)
2840 struct irq_chip *chip = irq_desc_get_chip(desc);
2841 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2844 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2846 chained_irq_enter(chip, desc);
2848 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2851 unsigned int irq, virq;
2855 virq = irq_linear_revmap(bank->domain, irq);
2858 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2862 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2865 * Triggering IRQ on both rising and falling edge
2866 * needs manual intervention.
2868 if (bank->toggle_edge_mode & BIT(irq)) {
2869 u32 data, data_old, polarity;
2870 unsigned long flags;
2872 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2874 raw_spin_lock_irqsave(&bank->slock, flags);
2876 polarity = readl_relaxed(bank->reg_base +
2878 if (data & BIT(irq))
2879 polarity &= ~BIT(irq);
2881 polarity |= BIT(irq);
2883 bank->reg_base + GPIO_INT_POLARITY);
2885 raw_spin_unlock_irqrestore(&bank->slock, flags);
2888 data = readl_relaxed(bank->reg_base +
2890 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2893 generic_handle_irq(virq);
2896 chained_irq_exit(chip, desc);
2899 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2901 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2902 struct rockchip_pin_bank *bank = gc->private;
2903 u32 mask = BIT(d->hwirq);
2907 unsigned long flags;
2910 /* make sure the pin is configured as gpio input */
2911 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2915 clk_enable(bank->clk);
2916 raw_spin_lock_irqsave(&bank->slock, flags);
2918 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2920 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2922 raw_spin_unlock_irqrestore(&bank->slock, flags);
2924 if (type & IRQ_TYPE_EDGE_BOTH)
2925 irq_set_handler_locked(d, handle_edge_irq);
2927 irq_set_handler_locked(d, handle_level_irq);
2929 raw_spin_lock_irqsave(&bank->slock, flags);
2932 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2933 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2936 case IRQ_TYPE_EDGE_BOTH:
2937 bank->toggle_edge_mode |= mask;
2941 * Determine gpio state. If 1 next interrupt should be falling
2944 data = readl(bank->reg_base + GPIO_EXT_PORT);
2950 case IRQ_TYPE_EDGE_RISING:
2951 bank->toggle_edge_mode &= ~mask;
2955 case IRQ_TYPE_EDGE_FALLING:
2956 bank->toggle_edge_mode &= ~mask;
2960 case IRQ_TYPE_LEVEL_HIGH:
2961 bank->toggle_edge_mode &= ~mask;
2965 case IRQ_TYPE_LEVEL_LOW:
2966 bank->toggle_edge_mode &= ~mask;
2972 raw_spin_unlock_irqrestore(&bank->slock, flags);
2973 clk_disable(bank->clk);
2977 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2978 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2981 raw_spin_unlock_irqrestore(&bank->slock, flags);
2982 clk_disable(bank->clk);
2987 static void rockchip_irq_suspend(struct irq_data *d)
2989 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2990 struct rockchip_pin_bank *bank = gc->private;
2992 clk_enable(bank->clk);
2993 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2994 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2995 clk_disable(bank->clk);
2998 static void rockchip_irq_resume(struct irq_data *d)
3000 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3001 struct rockchip_pin_bank *bank = gc->private;
3003 clk_enable(bank->clk);
3004 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3005 clk_disable(bank->clk);
3008 static void rockchip_irq_enable(struct irq_data *d)
3010 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3011 struct rockchip_pin_bank *bank = gc->private;
3013 clk_enable(bank->clk);
3014 irq_gc_mask_clr_bit(d);
3017 static void rockchip_irq_disable(struct irq_data *d)
3019 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3020 struct rockchip_pin_bank *bank = gc->private;
3022 irq_gc_mask_set_bit(d);
3023 clk_disable(bank->clk);
3026 static int rockchip_interrupts_register(struct platform_device *pdev,
3027 struct rockchip_pinctrl *info)
3029 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3030 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3031 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3032 struct irq_chip_generic *gc;
3036 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3038 dev_warn(&pdev->dev, "bank %s is not valid\n",
3043 ret = clk_enable(bank->clk);
3045 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3050 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3051 &irq_generic_chip_ops, NULL);
3052 if (!bank->domain) {
3053 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3055 clk_disable(bank->clk);
3059 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3060 "rockchip_gpio_irq", handle_level_irq,
3061 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3063 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3065 irq_domain_remove(bank->domain);
3066 clk_disable(bank->clk);
3071 * Linux assumes that all interrupts start out disabled/masked.
3072 * Our driver only uses the concept of masked and always keeps
3073 * things enabled, so for us that's all masked and all enabled.
3075 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3076 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3078 gc = irq_get_domain_generic_chip(bank->domain, 0);
3079 gc->reg_base = bank->reg_base;
3081 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3082 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3083 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3084 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3085 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3086 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3087 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3088 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3089 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3090 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3091 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3092 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3094 irq_set_chained_handler_and_data(bank->irq,
3095 rockchip_irq_demux, bank);
3097 /* map the gpio irqs here, when the clock is still running */
3098 for (j = 0 ; j < 32 ; j++)
3099 irq_create_mapping(bank->domain, j);
3101 clk_disable(bank->clk);
3107 static int rockchip_gpiolib_register(struct platform_device *pdev,
3108 struct rockchip_pinctrl *info)
3110 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3111 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3112 struct gpio_chip *gc;
3116 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3118 dev_warn(&pdev->dev, "bank %s is not valid\n",
3123 bank->gpio_chip = rockchip_gpiolib_chip;
3125 gc = &bank->gpio_chip;
3126 gc->base = bank->pin_base;
3127 gc->ngpio = bank->nr_pins;
3128 gc->parent = &pdev->dev;
3129 gc->of_node = bank->of_node;
3130 gc->label = bank->name;
3132 ret = gpiochip_add_data(gc, bank);
3134 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3140 rockchip_interrupts_register(pdev, info);
3145 for (--i, --bank; i >= 0; --i, --bank) {
3148 gpiochip_remove(&bank->gpio_chip);
3153 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3154 struct rockchip_pinctrl *info)
3156 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3157 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3160 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3163 gpiochip_remove(&bank->gpio_chip);
3169 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3170 struct rockchip_pinctrl *info)
3172 struct resource res;
3175 if (of_address_to_resource(bank->of_node, 0, &res)) {
3176 dev_err(info->dev, "cannot find IO resource for bank\n");
3180 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3181 if (IS_ERR(bank->reg_base))
3182 return PTR_ERR(bank->reg_base);
3185 * special case, where parts of the pull setting-registers are
3186 * part of the PMU register space
3188 if (of_device_is_compatible(bank->of_node,
3189 "rockchip,rk3188-gpio-bank0")) {
3190 struct device_node *node;
3192 node = of_parse_phandle(bank->of_node->parent,
3195 if (of_address_to_resource(bank->of_node, 1, &res)) {
3196 dev_err(info->dev, "cannot find IO resource for bank\n");
3200 base = devm_ioremap_resource(info->dev, &res);
3202 return PTR_ERR(base);
3203 rockchip_regmap_config.max_register =
3204 resource_size(&res) - 4;
3205 rockchip_regmap_config.name =
3206 "rockchip,rk3188-gpio-bank0-pull";
3207 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3209 &rockchip_regmap_config);
3214 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3216 bank->clk = of_clk_get(bank->of_node, 0);
3217 if (IS_ERR(bank->clk))
3218 return PTR_ERR(bank->clk);
3220 return clk_prepare(bank->clk);
3223 static const struct of_device_id rockchip_pinctrl_dt_match[];
3225 /* retrieve the soc specific data */
3226 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3227 struct rockchip_pinctrl *d,
3228 struct platform_device *pdev)
3230 const struct of_device_id *match;
3231 struct device_node *node = pdev->dev.of_node;
3232 struct device_node *np;
3233 struct rockchip_pin_ctrl *ctrl;
3234 struct rockchip_pin_bank *bank;
3235 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3237 match = of_match_node(rockchip_pinctrl_dt_match, node);
3238 ctrl = (struct rockchip_pin_ctrl *)match->data;
3240 for_each_child_of_node(node, np) {
3241 if (!of_find_property(np, "gpio-controller", NULL))
3244 bank = ctrl->pin_banks;
3245 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3246 if (!strcmp(bank->name, np->name)) {
3249 if (!rockchip_get_bank_data(bank, d))
3257 grf_offs = ctrl->grf_mux_offset;
3258 pmu_offs = ctrl->pmu_mux_offset;
3259 drv_pmu_offs = ctrl->pmu_drv_offset;
3260 drv_grf_offs = ctrl->grf_drv_offset;
3261 bank = ctrl->pin_banks;
3262 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3265 raw_spin_lock_init(&bank->slock);
3267 bank->pin_base = ctrl->nr_pins;
3268 ctrl->nr_pins += bank->nr_pins;
3270 /* calculate iomux and drv offsets */
3271 for (j = 0; j < 4; j++) {
3272 struct rockchip_iomux *iom = &bank->iomux[j];
3273 struct rockchip_drv *drv = &bank->drv[j];
3276 if (bank_pins >= bank->nr_pins)
3279 /* preset iomux offset value, set new start value */
3280 if (iom->offset >= 0) {
3281 if (iom->type & IOMUX_SOURCE_PMU)
3282 pmu_offs = iom->offset;
3284 grf_offs = iom->offset;
3285 } else { /* set current iomux offset */
3286 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3287 pmu_offs : grf_offs;
3290 /* preset drv offset value, set new start value */
3291 if (drv->offset >= 0) {
3292 if (iom->type & IOMUX_SOURCE_PMU)
3293 drv_pmu_offs = drv->offset;
3295 drv_grf_offs = drv->offset;
3296 } else { /* set current drv offset */
3297 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3298 drv_pmu_offs : drv_grf_offs;
3301 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3302 i, j, iom->offset, drv->offset);
3305 * Increase offset according to iomux width.
3306 * 4bit iomux'es are spread over two registers.
3308 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3309 IOMUX_WIDTH_3BIT)) ? 8 : 4;
3310 if (iom->type & IOMUX_SOURCE_PMU)
3316 * Increase offset according to drv width.
3317 * 3bit drive-strenth'es are spread over two registers.
3319 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3320 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3325 if (iom->type & IOMUX_SOURCE_PMU)
3326 drv_pmu_offs += inc;
3328 drv_grf_offs += inc;
3333 /* calculate the per-bank recalced_mask */
3334 for (j = 0; j < ctrl->niomux_recalced; j++) {
3337 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3338 pin = ctrl->iomux_recalced[j].pin;
3339 bank->recalced_mask |= BIT(pin);
3343 /* calculate the per-bank route_mask */
3344 for (j = 0; j < ctrl->niomux_routes; j++) {
3347 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3348 pin = ctrl->iomux_routes[j].pin;
3349 bank->route_mask |= BIT(pin);
3357 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3358 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3360 static u32 rk3288_grf_gpio6c_iomux;
3362 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3364 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3365 int ret = pinctrl_force_sleep(info->pctl_dev);
3371 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3372 * the setting here, and restore it at resume.
3374 if (info->ctrl->type == RK3288) {
3375 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3376 &rk3288_grf_gpio6c_iomux);
3378 pinctrl_force_default(info->pctl_dev);
3386 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3388 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3391 if (info->ctrl->type == RK3288) {
3392 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3393 rk3288_grf_gpio6c_iomux |
3394 GPIO6C6_SEL_WRITE_ENABLE);
3399 return pinctrl_force_default(info->pctl_dev);
3402 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3403 rockchip_pinctrl_resume);
3405 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3407 struct rockchip_pinctrl *info;
3408 struct device *dev = &pdev->dev;
3409 struct rockchip_pin_ctrl *ctrl;
3410 struct device_node *np = pdev->dev.of_node, *node;
3411 struct resource *res;
3415 if (!dev->of_node) {
3416 dev_err(dev, "device tree node not found\n");
3420 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3426 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3428 dev_err(dev, "driver data not available\n");
3433 node = of_parse_phandle(np, "rockchip,grf", 0);
3435 info->regmap_base = syscon_node_to_regmap(node);
3437 if (IS_ERR(info->regmap_base))
3438 return PTR_ERR(info->regmap_base);
3440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3441 base = devm_ioremap_resource(&pdev->dev, res);
3443 return PTR_ERR(base);
3445 rockchip_regmap_config.max_register = resource_size(res) - 4;
3446 rockchip_regmap_config.name = "rockchip,pinctrl";
3447 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3448 &rockchip_regmap_config);
3450 /* to check for the old dt-bindings */
3451 info->reg_size = resource_size(res);
3453 /* Honor the old binding, with pull registers as 2nd resource */
3454 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3455 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3456 base = devm_ioremap_resource(&pdev->dev, res);
3458 return PTR_ERR(base);
3460 rockchip_regmap_config.max_register =
3461 resource_size(res) - 4;
3462 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3463 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3465 &rockchip_regmap_config);
3469 /* try to find the optional reference to the pmu syscon */
3470 node = of_parse_phandle(np, "rockchip,pmu", 0);
3472 info->regmap_pmu = syscon_node_to_regmap(node);
3474 if (IS_ERR(info->regmap_pmu))
3475 return PTR_ERR(info->regmap_pmu);
3478 ret = rockchip_gpiolib_register(pdev, info);
3482 ret = rockchip_pinctrl_register(pdev, info);
3484 rockchip_gpiolib_unregister(pdev, info);
3488 platform_set_drvdata(pdev, info);
3493 static struct rockchip_pin_bank px30_pin_banks[] = {
3494 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3499 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3504 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3509 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3516 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3517 .pin_banks = px30_pin_banks,
3518 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3519 .label = "PX30-GPIO",
3521 .grf_mux_offset = 0x0,
3522 .pmu_mux_offset = 0x0,
3523 .iomux_routes = px30_mux_route_data,
3524 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3525 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3526 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3527 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3530 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3531 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3535 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3536 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3537 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3540 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3541 .pin_banks = rv1108_pin_banks,
3542 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3543 .label = "RV1108-GPIO",
3545 .grf_mux_offset = 0x10,
3546 .pmu_mux_offset = 0x0,
3547 .iomux_recalced = rv1108_mux_recalced_data,
3548 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3549 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3550 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3551 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3554 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3555 PIN_BANK(0, 32, "gpio0"),
3556 PIN_BANK(1, 32, "gpio1"),
3557 PIN_BANK(2, 32, "gpio2"),
3558 PIN_BANK(3, 32, "gpio3"),
3561 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3562 .pin_banks = rk2928_pin_banks,
3563 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3564 .label = "RK2928-GPIO",
3566 .grf_mux_offset = 0xa8,
3567 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3570 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3571 PIN_BANK(0, 32, "gpio0"),
3572 PIN_BANK(1, 32, "gpio1"),
3573 PIN_BANK(2, 32, "gpio2"),
3576 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3577 .pin_banks = rk3036_pin_banks,
3578 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3579 .label = "RK3036-GPIO",
3581 .grf_mux_offset = 0xa8,
3582 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3585 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3586 PIN_BANK(0, 32, "gpio0"),
3587 PIN_BANK(1, 32, "gpio1"),
3588 PIN_BANK(2, 32, "gpio2"),
3589 PIN_BANK(3, 32, "gpio3"),
3590 PIN_BANK(4, 32, "gpio4"),
3591 PIN_BANK(6, 16, "gpio6"),
3594 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3595 .pin_banks = rk3066a_pin_banks,
3596 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3597 .label = "RK3066a-GPIO",
3599 .grf_mux_offset = 0xa8,
3600 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3603 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3604 PIN_BANK(0, 32, "gpio0"),
3605 PIN_BANK(1, 32, "gpio1"),
3606 PIN_BANK(2, 32, "gpio2"),
3607 PIN_BANK(3, 32, "gpio3"),
3610 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3611 .pin_banks = rk3066b_pin_banks,
3612 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3613 .label = "RK3066b-GPIO",
3615 .grf_mux_offset = 0x60,
3618 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3619 PIN_BANK(0, 32, "gpio0"),
3620 PIN_BANK(1, 32, "gpio1"),
3621 PIN_BANK(2, 32, "gpio2"),
3622 PIN_BANK(3, 32, "gpio3"),
3625 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3626 .pin_banks = rk3128_pin_banks,
3627 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3628 .label = "RK3128-GPIO",
3630 .grf_mux_offset = 0xa8,
3631 .iomux_recalced = rk3128_mux_recalced_data,
3632 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3633 .iomux_routes = rk3128_mux_route_data,
3634 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3635 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3638 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3639 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3640 PIN_BANK(1, 32, "gpio1"),
3641 PIN_BANK(2, 32, "gpio2"),
3642 PIN_BANK(3, 32, "gpio3"),
3645 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3646 .pin_banks = rk3188_pin_banks,
3647 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3648 .label = "RK3188-GPIO",
3650 .grf_mux_offset = 0x60,
3651 .iomux_routes = rk3188_mux_route_data,
3652 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3653 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3656 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3657 PIN_BANK(0, 32, "gpio0"),
3658 PIN_BANK(1, 32, "gpio1"),
3659 PIN_BANK(2, 32, "gpio2"),
3660 PIN_BANK(3, 32, "gpio3"),
3663 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3664 .pin_banks = rk3228_pin_banks,
3665 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3666 .label = "RK3228-GPIO",
3668 .grf_mux_offset = 0x0,
3669 .iomux_routes = rk3228_mux_route_data,
3670 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3671 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3672 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3675 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3676 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3681 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3686 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3687 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3688 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3693 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3698 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3699 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3704 PIN_BANK(8, 16, "gpio8"),
3707 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3708 .pin_banks = rk3288_pin_banks,
3709 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3710 .label = "RK3288-GPIO",
3712 .grf_mux_offset = 0x0,
3713 .pmu_mux_offset = 0x84,
3714 .iomux_routes = rk3288_mux_route_data,
3715 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3716 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3717 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3720 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3721 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3722 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3723 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3727 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3734 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3735 .pin_banks = rk3328_pin_banks,
3736 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3737 .label = "RK3328-GPIO",
3739 .grf_mux_offset = 0x0,
3740 .iomux_recalced = rk3328_mux_recalced_data,
3741 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3742 .iomux_routes = rk3328_mux_route_data,
3743 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3744 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3745 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3746 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3749 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3750 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3755 PIN_BANK(1, 32, "gpio1"),
3756 PIN_BANK(2, 32, "gpio2"),
3757 PIN_BANK(3, 32, "gpio3"),
3760 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3761 .pin_banks = rk3368_pin_banks,
3762 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3763 .label = "RK3368-GPIO",
3765 .grf_mux_offset = 0x0,
3766 .pmu_mux_offset = 0x0,
3767 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3768 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3771 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3772 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3777 DRV_TYPE_IO_1V8_ONLY,
3778 DRV_TYPE_IO_1V8_ONLY,
3779 DRV_TYPE_IO_DEFAULT,
3780 DRV_TYPE_IO_DEFAULT,
3785 PULL_TYPE_IO_1V8_ONLY,
3786 PULL_TYPE_IO_1V8_ONLY,
3787 PULL_TYPE_IO_DEFAULT,
3788 PULL_TYPE_IO_DEFAULT
3790 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3794 DRV_TYPE_IO_1V8_OR_3V0,
3795 DRV_TYPE_IO_1V8_OR_3V0,
3796 DRV_TYPE_IO_1V8_OR_3V0,
3797 DRV_TYPE_IO_1V8_OR_3V0,
3803 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3804 DRV_TYPE_IO_1V8_OR_3V0,
3805 DRV_TYPE_IO_1V8_ONLY,
3806 DRV_TYPE_IO_1V8_ONLY,
3807 PULL_TYPE_IO_DEFAULT,
3808 PULL_TYPE_IO_DEFAULT,
3809 PULL_TYPE_IO_1V8_ONLY,
3810 PULL_TYPE_IO_1V8_ONLY
3812 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3813 DRV_TYPE_IO_3V3_ONLY,
3814 DRV_TYPE_IO_3V3_ONLY,
3815 DRV_TYPE_IO_1V8_OR_3V0
3817 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3818 DRV_TYPE_IO_1V8_3V0_AUTO,
3819 DRV_TYPE_IO_1V8_OR_3V0,
3820 DRV_TYPE_IO_1V8_OR_3V0
3824 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3825 .pin_banks = rk3399_pin_banks,
3826 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3827 .label = "RK3399-GPIO",
3829 .grf_mux_offset = 0xe000,
3830 .pmu_mux_offset = 0x0,
3831 .grf_drv_offset = 0xe100,
3832 .pmu_drv_offset = 0x80,
3833 .iomux_routes = rk3399_mux_route_data,
3834 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3835 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3836 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3839 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3840 { .compatible = "rockchip,px30-pinctrl",
3841 .data = &px30_pin_ctrl },
3842 { .compatible = "rockchip,rv1108-pinctrl",
3843 .data = &rv1108_pin_ctrl },
3844 { .compatible = "rockchip,rk2928-pinctrl",
3845 .data = &rk2928_pin_ctrl },
3846 { .compatible = "rockchip,rk3036-pinctrl",
3847 .data = &rk3036_pin_ctrl },
3848 { .compatible = "rockchip,rk3066a-pinctrl",
3849 .data = &rk3066a_pin_ctrl },
3850 { .compatible = "rockchip,rk3066b-pinctrl",
3851 .data = &rk3066b_pin_ctrl },
3852 { .compatible = "rockchip,rk3128-pinctrl",
3853 .data = (void *)&rk3128_pin_ctrl },
3854 { .compatible = "rockchip,rk3188-pinctrl",
3855 .data = &rk3188_pin_ctrl },
3856 { .compatible = "rockchip,rk3228-pinctrl",
3857 .data = &rk3228_pin_ctrl },
3858 { .compatible = "rockchip,rk3288-pinctrl",
3859 .data = &rk3288_pin_ctrl },
3860 { .compatible = "rockchip,rk3328-pinctrl",
3861 .data = &rk3328_pin_ctrl },
3862 { .compatible = "rockchip,rk3368-pinctrl",
3863 .data = &rk3368_pin_ctrl },
3864 { .compatible = "rockchip,rk3399-pinctrl",
3865 .data = &rk3399_pin_ctrl },
3869 static struct platform_driver rockchip_pinctrl_driver = {
3870 .probe = rockchip_pinctrl_probe,
3872 .name = "rockchip-pinctrl",
3873 .pm = &rockchip_pinctrl_dev_pm_ops,
3874 .of_match_table = rockchip_pinctrl_dt_match,
3878 static int __init rockchip_pinctrl_drv_register(void)
3880 return platform_driver_register(&rockchip_pinctrl_driver);
3882 postcore_initcall(rockchip_pinctrl_drv_register);