1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl driver for Rockchip SoCs
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
21 #include <linux/bitops.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/clk.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
39 /* GPIO control registers */
40 #define GPIO_SWPORT_DR 0x00
41 #define GPIO_SWPORT_DDR 0x04
42 #define GPIO_INTEN 0x30
43 #define GPIO_INTMASK 0x34
44 #define GPIO_INTTYPE_LEVEL 0x38
45 #define GPIO_INT_POLARITY 0x3c
46 #define GPIO_INT_STATUS 0x40
47 #define GPIO_INT_RAWSTATUS 0x44
48 #define GPIO_DEBOUNCE 0x48
49 #define GPIO_PORTS_EOI 0x4c
50 #define GPIO_EXT_PORT 0x50
51 #define GPIO_LS_SYNC 0x60
53 enum rockchip_pinctrl_type {
69 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
70 * register 31:16 area.
72 #define WRITE_MASK_VAL(h, l, v) \
73 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
76 * Encode variants of iomux registers into a type variable
78 #define IOMUX_GPIO_ONLY BIT(0)
79 #define IOMUX_WIDTH_4BIT BIT(1)
80 #define IOMUX_SOURCE_PMU BIT(2)
81 #define IOMUX_UNROUTED BIT(3)
82 #define IOMUX_WIDTH_3BIT BIT(4)
83 #define IOMUX_WIDTH_2BIT BIT(5)
86 * struct rockchip_iomux
87 * @type: iomux variant using IOMUX_* constants
88 * @offset: if initialized to -1 it will be autocalculated, by specifying
89 * an initial offset value the relevant source offset can be reset
90 * to a new value for autocalculating the following iomux registers.
92 struct rockchip_iomux {
98 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
100 enum rockchip_pin_drv_type {
101 DRV_TYPE_IO_DEFAULT = 0,
102 DRV_TYPE_IO_1V8_OR_3V0,
103 DRV_TYPE_IO_1V8_ONLY,
104 DRV_TYPE_IO_1V8_3V0_AUTO,
105 DRV_TYPE_IO_3V3_ONLY,
110 * enum type index corresponding to rockchip_pull_list arrays index.
112 enum rockchip_pin_pull_type {
113 PULL_TYPE_IO_DEFAULT = 0,
114 PULL_TYPE_IO_1V8_ONLY,
119 * struct rockchip_drv
120 * @drv_type: drive strength variant using rockchip_perpin_drv_type
121 * @offset: if initialized to -1 it will be autocalculated, by specifying
122 * an initial offset value the relevant source offset can be reset
123 * to a new value for autocalculating the following drive strength
124 * registers. if used chips own cal_drv func instead to calculate
125 * registers offset, the variant could be ignored.
127 struct rockchip_drv {
128 enum rockchip_pin_drv_type drv_type;
133 * struct rockchip_pin_bank
134 * @reg_base: register base of the gpio bank
135 * @regmap_pull: optional separate register for additional pull settings
136 * @clk: clock of the gpio bank
137 * @irq: interrupt of the gpio bank
138 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
139 * @pin_base: first pin number
140 * @nr_pins: number of pins in this bank
141 * @name: name of the bank
142 * @bank_num: number of the bank, to account for holes
143 * @iomux: array describing the 4 iomux sources of the bank
144 * @drv: array describing the 4 drive strength sources of the bank
145 * @pull_type: array describing the 4 pull type sources of the bank
146 * @valid: is all necessary information present
147 * @of_node: dt node of this bank
148 * @drvdata: common pinctrl basedata
149 * @domain: irqdomain of the gpio bank
150 * @gpio_chip: gpiolib chip
151 * @grange: gpio range
152 * @slock: spinlock for the gpio bank
153 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
154 * @recalced_mask: bit mask to indicate a need to recalulate the mask
155 * @route_mask: bits describing the routing pins of per bank
157 struct rockchip_pin_bank {
158 void __iomem *reg_base;
159 struct regmap *regmap_pull;
167 struct rockchip_iomux iomux[4];
168 struct rockchip_drv drv[4];
169 enum rockchip_pin_pull_type pull_type[4];
171 struct device_node *of_node;
172 struct rockchip_pinctrl *drvdata;
173 struct irq_domain *domain;
174 struct gpio_chip gpio_chip;
175 struct pinctrl_gpio_range grange;
176 raw_spinlock_t slock;
177 u32 toggle_edge_mode;
182 #define PIN_BANK(id, pins, label) \
195 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
201 { .type = iom0, .offset = -1 }, \
202 { .type = iom1, .offset = -1 }, \
203 { .type = iom2, .offset = -1 }, \
204 { .type = iom3, .offset = -1 }, \
208 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
220 { .drv_type = type0, .offset = -1 }, \
221 { .drv_type = type1, .offset = -1 }, \
222 { .drv_type = type2, .offset = -1 }, \
223 { .drv_type = type3, .offset = -1 }, \
227 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
228 drv2, drv3, pull0, pull1, \
241 { .drv_type = drv0, .offset = -1 }, \
242 { .drv_type = drv1, .offset = -1 }, \
243 { .drv_type = drv2, .offset = -1 }, \
244 { .drv_type = drv3, .offset = -1 }, \
246 .pull_type[0] = pull0, \
247 .pull_type[1] = pull1, \
248 .pull_type[2] = pull2, \
249 .pull_type[3] = pull3, \
252 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
253 iom2, iom3, drv0, drv1, drv2, \
254 drv3, offset0, offset1, \
261 { .type = iom0, .offset = -1 }, \
262 { .type = iom1, .offset = -1 }, \
263 { .type = iom2, .offset = -1 }, \
264 { .type = iom3, .offset = -1 }, \
267 { .drv_type = drv0, .offset = offset0 }, \
268 { .drv_type = drv1, .offset = offset1 }, \
269 { .drv_type = drv2, .offset = offset2 }, \
270 { .drv_type = drv3, .offset = offset3 }, \
274 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
275 label, iom0, iom1, iom2, \
276 iom3, drv0, drv1, drv2, \
277 drv3, offset0, offset1, \
278 offset2, offset3, pull0, \
279 pull1, pull2, pull3) \
285 { .type = iom0, .offset = -1 }, \
286 { .type = iom1, .offset = -1 }, \
287 { .type = iom2, .offset = -1 }, \
288 { .type = iom3, .offset = -1 }, \
291 { .drv_type = drv0, .offset = offset0 }, \
292 { .drv_type = drv1, .offset = offset1 }, \
293 { .drv_type = drv2, .offset = offset2 }, \
294 { .drv_type = drv3, .offset = offset3 }, \
296 .pull_type[0] = pull0, \
297 .pull_type[1] = pull1, \
298 .pull_type[2] = pull2, \
299 .pull_type[3] = pull3, \
302 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
307 .route_offset = REG, \
309 .route_location = FLAG, \
312 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
313 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
315 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
316 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
318 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
319 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
322 * struct rockchip_mux_recalced_data: represent a pin iomux data.
325 * @bit: index at register.
326 * @reg: register offset.
329 struct rockchip_mux_recalced_data {
337 enum rockchip_mux_route_location {
338 ROCKCHIP_ROUTE_SAME = 0,
344 * struct rockchip_mux_recalced_data: represent a pin iomux data.
345 * @bank_num: bank number.
346 * @pin: index at register or used to calc index.
347 * @func: the min pin.
348 * @route_location: the mux route location (same, pmu, grf).
349 * @route_offset: the max pin.
350 * @route_val: the register offset.
352 struct rockchip_mux_route_data {
356 enum rockchip_mux_route_location route_location;
361 struct rockchip_pin_ctrl {
362 struct rockchip_pin_bank *pin_banks;
366 enum rockchip_pinctrl_type type;
371 struct rockchip_mux_recalced_data *iomux_recalced;
373 struct rockchip_mux_route_data *iomux_routes;
376 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
377 int pin_num, struct regmap **regmap,
379 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
380 int pin_num, struct regmap **regmap,
382 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
383 int pin_num, struct regmap **regmap,
387 struct rockchip_pin_config {
389 unsigned long *configs;
390 unsigned int nconfigs;
394 * struct rockchip_pin_group: represent group of pins of a pinmux function.
395 * @name: name of the pin group, used to lookup the group.
396 * @pins: the pins included in this group.
397 * @npins: number of pins included in this group.
398 * @data: local pin configuration
400 struct rockchip_pin_group {
404 struct rockchip_pin_config *data;
408 * struct rockchip_pmx_func: represent a pin function.
409 * @name: name of the pin function, used to lookup the function.
410 * @groups: one or more names of pin groups that provide this function.
411 * @ngroups: number of groups included in @groups.
413 struct rockchip_pmx_func {
419 struct rockchip_pinctrl {
420 struct regmap *regmap_base;
422 struct regmap *regmap_pull;
423 struct regmap *regmap_pmu;
425 struct rockchip_pin_ctrl *ctrl;
426 struct pinctrl_desc pctl;
427 struct pinctrl_dev *pctl_dev;
428 struct rockchip_pin_group *groups;
429 unsigned int ngroups;
430 struct rockchip_pmx_func *functions;
431 unsigned int nfunctions;
434 static struct regmap_config rockchip_regmap_config = {
440 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
441 const struct rockchip_pinctrl *info,
446 for (i = 0; i < info->ngroups; i++) {
447 if (!strcmp(info->groups[i].name, name))
448 return &info->groups[i];
455 * given a pin number that is local to a pin controller, find out the pin bank
456 * and the register base of the pin bank.
458 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
461 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
463 while (pin >= (b->pin_base + b->nr_pins))
469 static struct rockchip_pin_bank *bank_num_to_bank(
470 struct rockchip_pinctrl *info,
473 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
476 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
477 if (b->bank_num == num)
481 return ERR_PTR(-EINVAL);
485 * Pinctrl_ops handling
488 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
492 return info->ngroups;
495 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
498 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
500 return info->groups[selector].name;
503 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
504 unsigned selector, const unsigned **pins,
507 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
509 if (selector >= info->ngroups)
512 *pins = info->groups[selector].pins;
513 *npins = info->groups[selector].npins;
518 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
519 struct device_node *np,
520 struct pinctrl_map **map, unsigned *num_maps)
522 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
523 const struct rockchip_pin_group *grp;
524 struct pinctrl_map *new_map;
525 struct device_node *parent;
530 * first find the group of this node and check if we need to create
531 * config maps for pins
533 grp = pinctrl_name_to_group(info, np->name);
535 dev_err(info->dev, "unable to find group for node %pOFn\n",
540 map_num += grp->npins;
542 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
550 parent = of_get_parent(np);
555 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
556 new_map[0].data.mux.function = parent->name;
557 new_map[0].data.mux.group = np->name;
560 /* create config map */
562 for (i = 0; i < grp->npins; i++) {
563 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
564 new_map[i].data.configs.group_or_pin =
565 pin_get_name(pctldev, grp->pins[i]);
566 new_map[i].data.configs.configs = grp->data[i].configs;
567 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
570 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
571 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
576 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
577 struct pinctrl_map *map, unsigned num_maps)
582 static const struct pinctrl_ops rockchip_pctrl_ops = {
583 .get_groups_count = rockchip_get_groups_count,
584 .get_group_name = rockchip_get_group_name,
585 .get_group_pins = rockchip_get_group_pins,
586 .dt_node_to_map = rockchip_dt_node_to_map,
587 .dt_free_map = rockchip_dt_free_map,
594 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
658 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
692 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
801 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
823 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
824 int *reg, u8 *bit, int *mask)
826 struct rockchip_pinctrl *info = bank->drvdata;
827 struct rockchip_pin_ctrl *ctrl = info->ctrl;
828 struct rockchip_mux_recalced_data *data;
831 for (i = 0; i < ctrl->niomux_recalced; i++) {
832 data = &ctrl->iomux_recalced[i];
833 if (data->num == bank->bank_num &&
838 if (i >= ctrl->niomux_recalced)
846 static struct rockchip_mux_route_data px30_mux_route_data[] = {
847 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
848 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
849 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
850 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
851 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
852 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
853 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
854 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
857 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
858 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
859 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
860 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
861 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
862 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
863 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
864 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
867 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
868 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
869 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
872 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
873 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
874 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
875 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
876 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
877 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
878 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
879 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
880 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
881 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
882 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
883 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
884 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
885 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
886 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
887 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
888 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
889 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
890 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
893 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
894 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
895 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
898 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
899 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
900 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
901 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
902 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
903 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
904 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
905 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
906 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
907 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
908 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
909 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
910 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
911 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
912 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
913 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
914 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
915 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
916 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
917 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
918 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
919 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
920 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
921 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
922 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
923 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
924 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
927 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
928 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
929 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
930 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
931 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
932 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
933 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
934 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
935 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
936 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
937 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
938 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
939 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
942 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
943 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
944 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
945 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
946 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
947 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
950 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
951 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
952 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
953 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
954 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
955 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
956 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
957 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
958 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
959 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
960 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
961 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
962 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
963 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
964 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
965 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
966 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
967 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
968 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
969 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
970 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
971 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
972 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
973 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
974 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
975 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
976 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
977 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
978 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
979 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
980 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
981 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
982 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
983 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
984 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
985 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
986 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
987 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
988 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
989 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
990 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
991 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
992 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
993 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
994 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
995 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
996 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
997 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
998 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
999 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1000 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1001 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1002 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1003 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1004 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1005 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1006 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1007 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1008 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1009 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1010 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1011 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1012 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1013 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1014 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1015 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1016 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1017 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1018 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1019 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1020 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1021 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1022 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1023 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1024 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1025 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1026 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1027 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1028 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1029 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1030 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1031 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1032 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1033 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1034 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1035 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1036 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1037 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1038 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1039 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1040 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1041 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1042 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1043 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1046 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1047 int mux, u32 *loc, u32 *reg, u32 *value)
1049 struct rockchip_pinctrl *info = bank->drvdata;
1050 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1051 struct rockchip_mux_route_data *data;
1054 for (i = 0; i < ctrl->niomux_routes; i++) {
1055 data = &ctrl->iomux_routes[i];
1056 if ((data->bank_num == bank->bank_num) &&
1057 (data->pin == pin) && (data->func == mux))
1061 if (i >= ctrl->niomux_routes)
1064 *loc = data->route_location;
1065 *reg = data->route_offset;
1066 *value = data->route_val;
1071 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1073 struct rockchip_pinctrl *info = bank->drvdata;
1074 int iomux_num = (pin / 8);
1075 struct regmap *regmap;
1077 int reg, ret, mask, mux_type;
1083 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1084 dev_err(info->dev, "pin %d is unrouted\n", pin);
1088 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1089 return RK_FUNC_GPIO;
1091 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1092 ? info->regmap_pmu : info->regmap_base;
1094 /* get basic quadrupel of mux registers and the correct reg inside */
1095 mux_type = bank->iomux[iomux_num].type;
1096 reg = bank->iomux[iomux_num].offset;
1097 if (mux_type & IOMUX_WIDTH_4BIT) {
1100 bit = (pin % 4) * 4;
1102 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1105 bit = (pin % 8 % 5) * 3;
1108 bit = (pin % 8) * 2;
1112 if (bank->recalced_mask & BIT(pin))
1113 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1115 ret = regmap_read(regmap, reg, &val);
1119 return ((val >> bit) & mask);
1122 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1125 struct rockchip_pinctrl *info = bank->drvdata;
1126 int iomux_num = (pin / 8);
1131 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1132 dev_err(info->dev, "pin %d is unrouted\n", pin);
1136 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1137 if (mux != RK_FUNC_GPIO) {
1139 "pin %d only supports a gpio mux\n", pin);
1148 * Set a new mux function for a pin.
1150 * The register is divided into the upper and lower 16 bit. When changing
1151 * a value, the previous register value is not read and changed. Instead
1152 * it seems the changed bits are marked in the upper 16 bit, while the
1153 * changed value gets set in the same offset in the lower 16 bit.
1154 * All pin settings seem to be 2 bit wide in both the upper and lower
1156 * @bank: pin bank to change
1157 * @pin: pin to change
1158 * @mux: new mux function to set
1160 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1162 struct rockchip_pinctrl *info = bank->drvdata;
1163 int iomux_num = (pin / 8);
1164 struct regmap *regmap;
1165 int reg, ret, mask, mux_type;
1167 u32 data, rmask, route_location, route_reg, route_val;
1169 ret = rockchip_verify_mux(bank, pin, mux);
1173 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1176 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1177 bank->bank_num, pin, mux);
1179 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1180 ? info->regmap_pmu : info->regmap_base;
1182 /* get basic quadrupel of mux registers and the correct reg inside */
1183 mux_type = bank->iomux[iomux_num].type;
1184 reg = bank->iomux[iomux_num].offset;
1185 if (mux_type & IOMUX_WIDTH_4BIT) {
1188 bit = (pin % 4) * 4;
1190 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1193 bit = (pin % 8 % 5) * 3;
1196 bit = (pin % 8) * 2;
1200 if (bank->recalced_mask & BIT(pin))
1201 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1203 if (bank->route_mask & BIT(pin)) {
1204 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1205 &route_reg, &route_val)) {
1206 struct regmap *route_regmap = regmap;
1208 /* handle special locations */
1209 switch (route_location) {
1210 case ROCKCHIP_ROUTE_PMU:
1211 route_regmap = info->regmap_pmu;
1213 case ROCKCHIP_ROUTE_GRF:
1214 route_regmap = info->regmap_base;
1218 ret = regmap_write(route_regmap, route_reg, route_val);
1224 data = (mask << (bit + 16));
1225 rmask = data | (data >> 16);
1226 data |= (mux & mask) << bit;
1227 ret = regmap_update_bits(regmap, reg, rmask, data);
1232 #define PX30_PULL_PMU_OFFSET 0x10
1233 #define PX30_PULL_GRF_OFFSET 0x60
1234 #define PX30_PULL_BITS_PER_PIN 2
1235 #define PX30_PULL_PINS_PER_REG 8
1236 #define PX30_PULL_BANK_STRIDE 16
1238 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1239 int pin_num, struct regmap **regmap,
1242 struct rockchip_pinctrl *info = bank->drvdata;
1244 /* The first 32 pins of the first bank are located in PMU */
1245 if (bank->bank_num == 0) {
1246 *regmap = info->regmap_pmu;
1247 *reg = PX30_PULL_PMU_OFFSET;
1249 *regmap = info->regmap_base;
1250 *reg = PX30_PULL_GRF_OFFSET;
1252 /* correct the offset, as we're starting with the 2nd bank */
1254 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1257 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1258 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1259 *bit *= PX30_PULL_BITS_PER_PIN;
1262 #define PX30_DRV_PMU_OFFSET 0x20
1263 #define PX30_DRV_GRF_OFFSET 0xf0
1264 #define PX30_DRV_BITS_PER_PIN 2
1265 #define PX30_DRV_PINS_PER_REG 8
1266 #define PX30_DRV_BANK_STRIDE 16
1268 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1269 int pin_num, struct regmap **regmap,
1272 struct rockchip_pinctrl *info = bank->drvdata;
1274 /* The first 32 pins of the first bank are located in PMU */
1275 if (bank->bank_num == 0) {
1276 *regmap = info->regmap_pmu;
1277 *reg = PX30_DRV_PMU_OFFSET;
1279 *regmap = info->regmap_base;
1280 *reg = PX30_DRV_GRF_OFFSET;
1282 /* correct the offset, as we're starting with the 2nd bank */
1284 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1287 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1288 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1289 *bit *= PX30_DRV_BITS_PER_PIN;
1292 #define PX30_SCHMITT_PMU_OFFSET 0x38
1293 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1294 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1295 #define PX30_SCHMITT_BANK_STRIDE 16
1296 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1298 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1300 struct regmap **regmap,
1303 struct rockchip_pinctrl *info = bank->drvdata;
1306 if (bank->bank_num == 0) {
1307 *regmap = info->regmap_pmu;
1308 *reg = PX30_SCHMITT_PMU_OFFSET;
1309 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1311 *regmap = info->regmap_base;
1312 *reg = PX30_SCHMITT_GRF_OFFSET;
1313 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1314 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1317 *reg += ((pin_num / pins_per_reg) * 4);
1318 *bit = pin_num % pins_per_reg;
1323 #define RV1108_PULL_PMU_OFFSET 0x10
1324 #define RV1108_PULL_OFFSET 0x110
1325 #define RV1108_PULL_PINS_PER_REG 8
1326 #define RV1108_PULL_BITS_PER_PIN 2
1327 #define RV1108_PULL_BANK_STRIDE 16
1329 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1330 int pin_num, struct regmap **regmap,
1333 struct rockchip_pinctrl *info = bank->drvdata;
1335 /* The first 24 pins of the first bank are located in PMU */
1336 if (bank->bank_num == 0) {
1337 *regmap = info->regmap_pmu;
1338 *reg = RV1108_PULL_PMU_OFFSET;
1340 *reg = RV1108_PULL_OFFSET;
1341 *regmap = info->regmap_base;
1342 /* correct the offset, as we're starting with the 2nd bank */
1344 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1347 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1348 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1349 *bit *= RV1108_PULL_BITS_PER_PIN;
1352 #define RV1108_DRV_PMU_OFFSET 0x20
1353 #define RV1108_DRV_GRF_OFFSET 0x210
1354 #define RV1108_DRV_BITS_PER_PIN 2
1355 #define RV1108_DRV_PINS_PER_REG 8
1356 #define RV1108_DRV_BANK_STRIDE 16
1358 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1359 int pin_num, struct regmap **regmap,
1362 struct rockchip_pinctrl *info = bank->drvdata;
1364 /* The first 24 pins of the first bank are located in PMU */
1365 if (bank->bank_num == 0) {
1366 *regmap = info->regmap_pmu;
1367 *reg = RV1108_DRV_PMU_OFFSET;
1369 *regmap = info->regmap_base;
1370 *reg = RV1108_DRV_GRF_OFFSET;
1372 /* correct the offset, as we're starting with the 2nd bank */
1374 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1377 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1378 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1379 *bit *= RV1108_DRV_BITS_PER_PIN;
1382 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1383 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1384 #define RV1108_SCHMITT_BANK_STRIDE 8
1385 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1386 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1388 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1390 struct regmap **regmap,
1393 struct rockchip_pinctrl *info = bank->drvdata;
1396 if (bank->bank_num == 0) {
1397 *regmap = info->regmap_pmu;
1398 *reg = RV1108_SCHMITT_PMU_OFFSET;
1399 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1401 *regmap = info->regmap_base;
1402 *reg = RV1108_SCHMITT_GRF_OFFSET;
1403 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1404 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1406 *reg += ((pin_num / pins_per_reg) * 4);
1407 *bit = pin_num % pins_per_reg;
1412 #define RK3308_SCHMITT_PINS_PER_REG 8
1413 #define RK3308_SCHMITT_BANK_STRIDE 16
1414 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1416 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1417 int pin_num, struct regmap **regmap,
1420 struct rockchip_pinctrl *info = bank->drvdata;
1422 *regmap = info->regmap_base;
1423 *reg = RK3308_SCHMITT_GRF_OFFSET;
1425 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1426 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1427 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1432 #define RK2928_PULL_OFFSET 0x118
1433 #define RK2928_PULL_PINS_PER_REG 16
1434 #define RK2928_PULL_BANK_STRIDE 8
1436 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1437 int pin_num, struct regmap **regmap,
1440 struct rockchip_pinctrl *info = bank->drvdata;
1442 *regmap = info->regmap_base;
1443 *reg = RK2928_PULL_OFFSET;
1444 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1445 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1447 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1450 #define RK3128_PULL_OFFSET 0x118
1452 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1453 int pin_num, struct regmap **regmap,
1456 struct rockchip_pinctrl *info = bank->drvdata;
1458 *regmap = info->regmap_base;
1459 *reg = RK3128_PULL_OFFSET;
1460 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1461 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1463 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1466 #define RK3188_PULL_OFFSET 0x164
1467 #define RK3188_PULL_BITS_PER_PIN 2
1468 #define RK3188_PULL_PINS_PER_REG 8
1469 #define RK3188_PULL_BANK_STRIDE 16
1470 #define RK3188_PULL_PMU_OFFSET 0x64
1472 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1473 int pin_num, struct regmap **regmap,
1476 struct rockchip_pinctrl *info = bank->drvdata;
1478 /* The first 12 pins of the first bank are located elsewhere */
1479 if (bank->bank_num == 0 && pin_num < 12) {
1480 *regmap = info->regmap_pmu ? info->regmap_pmu
1481 : bank->regmap_pull;
1482 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1483 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1484 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1485 *bit *= RK3188_PULL_BITS_PER_PIN;
1487 *regmap = info->regmap_pull ? info->regmap_pull
1488 : info->regmap_base;
1489 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1491 /* correct the offset, as it is the 2nd pull register */
1493 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1494 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1497 * The bits in these registers have an inverse ordering
1498 * with the lowest pin being in bits 15:14 and the highest
1501 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1502 *bit *= RK3188_PULL_BITS_PER_PIN;
1506 #define RK3288_PULL_OFFSET 0x140
1507 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1508 int pin_num, struct regmap **regmap,
1511 struct rockchip_pinctrl *info = bank->drvdata;
1513 /* The first 24 pins of the first bank are located in PMU */
1514 if (bank->bank_num == 0) {
1515 *regmap = info->regmap_pmu;
1516 *reg = RK3188_PULL_PMU_OFFSET;
1518 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1519 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1520 *bit *= RK3188_PULL_BITS_PER_PIN;
1522 *regmap = info->regmap_base;
1523 *reg = RK3288_PULL_OFFSET;
1525 /* correct the offset, as we're starting with the 2nd bank */
1527 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1528 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1530 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1531 *bit *= RK3188_PULL_BITS_PER_PIN;
1535 #define RK3288_DRV_PMU_OFFSET 0x70
1536 #define RK3288_DRV_GRF_OFFSET 0x1c0
1537 #define RK3288_DRV_BITS_PER_PIN 2
1538 #define RK3288_DRV_PINS_PER_REG 8
1539 #define RK3288_DRV_BANK_STRIDE 16
1541 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1542 int pin_num, struct regmap **regmap,
1545 struct rockchip_pinctrl *info = bank->drvdata;
1547 /* The first 24 pins of the first bank are located in PMU */
1548 if (bank->bank_num == 0) {
1549 *regmap = info->regmap_pmu;
1550 *reg = RK3288_DRV_PMU_OFFSET;
1552 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1553 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1554 *bit *= RK3288_DRV_BITS_PER_PIN;
1556 *regmap = info->regmap_base;
1557 *reg = RK3288_DRV_GRF_OFFSET;
1559 /* correct the offset, as we're starting with the 2nd bank */
1561 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1562 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1564 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1565 *bit *= RK3288_DRV_BITS_PER_PIN;
1569 #define RK3228_PULL_OFFSET 0x100
1571 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1572 int pin_num, struct regmap **regmap,
1575 struct rockchip_pinctrl *info = bank->drvdata;
1577 *regmap = info->regmap_base;
1578 *reg = RK3228_PULL_OFFSET;
1579 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1580 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1582 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1583 *bit *= RK3188_PULL_BITS_PER_PIN;
1586 #define RK3228_DRV_GRF_OFFSET 0x200
1588 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1589 int pin_num, struct regmap **regmap,
1592 struct rockchip_pinctrl *info = bank->drvdata;
1594 *regmap = info->regmap_base;
1595 *reg = RK3228_DRV_GRF_OFFSET;
1596 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1597 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1599 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1600 *bit *= RK3288_DRV_BITS_PER_PIN;
1603 #define RK3308_PULL_OFFSET 0xa0
1605 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1606 int pin_num, struct regmap **regmap,
1609 struct rockchip_pinctrl *info = bank->drvdata;
1611 *regmap = info->regmap_base;
1612 *reg = RK3308_PULL_OFFSET;
1613 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1614 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1616 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1617 *bit *= RK3188_PULL_BITS_PER_PIN;
1620 #define RK3308_DRV_GRF_OFFSET 0x100
1622 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1623 int pin_num, struct regmap **regmap,
1626 struct rockchip_pinctrl *info = bank->drvdata;
1628 *regmap = info->regmap_base;
1629 *reg = RK3308_DRV_GRF_OFFSET;
1630 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1631 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1633 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1634 *bit *= RK3288_DRV_BITS_PER_PIN;
1637 #define RK3368_PULL_GRF_OFFSET 0x100
1638 #define RK3368_PULL_PMU_OFFSET 0x10
1640 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1641 int pin_num, struct regmap **regmap,
1644 struct rockchip_pinctrl *info = bank->drvdata;
1646 /* The first 32 pins of the first bank are located in PMU */
1647 if (bank->bank_num == 0) {
1648 *regmap = info->regmap_pmu;
1649 *reg = RK3368_PULL_PMU_OFFSET;
1651 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1652 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1653 *bit *= RK3188_PULL_BITS_PER_PIN;
1655 *regmap = info->regmap_base;
1656 *reg = RK3368_PULL_GRF_OFFSET;
1658 /* correct the offset, as we're starting with the 2nd bank */
1660 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1661 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1663 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1664 *bit *= RK3188_PULL_BITS_PER_PIN;
1668 #define RK3368_DRV_PMU_OFFSET 0x20
1669 #define RK3368_DRV_GRF_OFFSET 0x200
1671 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1672 int pin_num, struct regmap **regmap,
1675 struct rockchip_pinctrl *info = bank->drvdata;
1677 /* The first 32 pins of the first bank are located in PMU */
1678 if (bank->bank_num == 0) {
1679 *regmap = info->regmap_pmu;
1680 *reg = RK3368_DRV_PMU_OFFSET;
1682 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1683 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1684 *bit *= RK3288_DRV_BITS_PER_PIN;
1686 *regmap = info->regmap_base;
1687 *reg = RK3368_DRV_GRF_OFFSET;
1689 /* correct the offset, as we're starting with the 2nd bank */
1691 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1692 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1694 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1695 *bit *= RK3288_DRV_BITS_PER_PIN;
1699 #define RK3399_PULL_GRF_OFFSET 0xe040
1700 #define RK3399_PULL_PMU_OFFSET 0x40
1701 #define RK3399_DRV_3BITS_PER_PIN 3
1703 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1704 int pin_num, struct regmap **regmap,
1707 struct rockchip_pinctrl *info = bank->drvdata;
1709 /* The bank0:16 and bank1:32 pins are located in PMU */
1710 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1711 *regmap = info->regmap_pmu;
1712 *reg = RK3399_PULL_PMU_OFFSET;
1714 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1716 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1717 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1718 *bit *= RK3188_PULL_BITS_PER_PIN;
1720 *regmap = info->regmap_base;
1721 *reg = RK3399_PULL_GRF_OFFSET;
1723 /* correct the offset, as we're starting with the 3rd bank */
1725 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1726 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1728 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1729 *bit *= RK3188_PULL_BITS_PER_PIN;
1733 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1734 int pin_num, struct regmap **regmap,
1737 struct rockchip_pinctrl *info = bank->drvdata;
1738 int drv_num = (pin_num / 8);
1740 /* The bank0:16 and bank1:32 pins are located in PMU */
1741 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1742 *regmap = info->regmap_pmu;
1744 *regmap = info->regmap_base;
1746 *reg = bank->drv[drv_num].offset;
1747 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1748 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1749 *bit = (pin_num % 8) * 3;
1751 *bit = (pin_num % 8) * 2;
1754 #define RK3568_PULL_PMU_OFFSET 0x20
1755 #define RK3568_PULL_GRF_OFFSET 0x80
1756 #define RK3568_PULL_BITS_PER_PIN 2
1757 #define RK3568_PULL_PINS_PER_REG 8
1758 #define RK3568_PULL_BANK_STRIDE 0x10
1760 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1761 int pin_num, struct regmap **regmap,
1764 struct rockchip_pinctrl *info = bank->drvdata;
1766 if (bank->bank_num == 0) {
1767 *regmap = info->regmap_pmu;
1768 *reg = RK3568_PULL_PMU_OFFSET;
1769 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1770 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1772 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1773 *bit *= RK3568_PULL_BITS_PER_PIN;
1775 *regmap = info->regmap_base;
1776 *reg = RK3568_PULL_GRF_OFFSET;
1777 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1778 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1780 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1781 *bit *= RK3568_PULL_BITS_PER_PIN;
1785 #define RK3568_DRV_PMU_OFFSET 0x70
1786 #define RK3568_DRV_GRF_OFFSET 0x200
1787 #define RK3568_DRV_BITS_PER_PIN 8
1788 #define RK3568_DRV_PINS_PER_REG 2
1789 #define RK3568_DRV_BANK_STRIDE 0x40
1791 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1792 int pin_num, struct regmap **regmap,
1795 struct rockchip_pinctrl *info = bank->drvdata;
1797 /* The first 32 pins of the first bank are located in PMU */
1798 if (bank->bank_num == 0) {
1799 *regmap = info->regmap_pmu;
1800 *reg = RK3568_DRV_PMU_OFFSET;
1801 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1803 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1804 *bit *= RK3568_DRV_BITS_PER_PIN;
1806 *regmap = info->regmap_base;
1807 *reg = RK3568_DRV_GRF_OFFSET;
1808 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1809 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1811 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1812 *bit *= RK3568_DRV_BITS_PER_PIN;
1816 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1817 { 2, 4, 8, 12, -1, -1, -1, -1 },
1818 { 3, 6, 9, 12, -1, -1, -1, -1 },
1819 { 5, 10, 15, 20, -1, -1, -1, -1 },
1820 { 4, 6, 8, 10, 12, 14, 16, 18 },
1821 { 4, 7, 10, 13, 16, 19, 22, 26 }
1824 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1827 struct rockchip_pinctrl *info = bank->drvdata;
1828 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1829 struct regmap *regmap;
1831 u32 data, temp, rmask_bits;
1833 int drv_type = bank->drv[pin_num / 8].drv_type;
1835 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1838 case DRV_TYPE_IO_1V8_3V0_AUTO:
1839 case DRV_TYPE_IO_3V3_ONLY:
1840 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1843 /* regular case, nothing to do */
1847 * drive-strength offset is special, as it is
1848 * spread over 2 registers
1850 ret = regmap_read(regmap, reg, &data);
1854 ret = regmap_read(regmap, reg + 0x4, &temp);
1859 * the bit data[15] contains bit 0 of the value
1860 * while temp[1:0] contains bits 2 and 1
1867 return rockchip_perpin_drv_list[drv_type][data];
1869 /* setting fully enclosed in the second register */
1874 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1880 case DRV_TYPE_IO_DEFAULT:
1881 case DRV_TYPE_IO_1V8_OR_3V0:
1882 case DRV_TYPE_IO_1V8_ONLY:
1883 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1886 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1891 ret = regmap_read(regmap, reg, &data);
1896 data &= (1 << rmask_bits) - 1;
1898 return rockchip_perpin_drv_list[drv_type][data];
1901 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1902 int pin_num, int strength)
1904 struct rockchip_pinctrl *info = bank->drvdata;
1905 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1906 struct regmap *regmap;
1908 u32 data, rmask, rmask_bits, temp;
1910 int drv_type = bank->drv[pin_num / 8].drv_type;
1912 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1913 bank->bank_num, pin_num, strength);
1915 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1916 if (ctrl->type == RK3568) {
1917 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1918 ret = (1 << (strength + 1)) - 1;
1923 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1924 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1927 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1928 ret = rockchip_perpin_drv_list[drv_type][i];
1934 dev_err(info->dev, "unsupported driver strength %d\n",
1940 case DRV_TYPE_IO_1V8_3V0_AUTO:
1941 case DRV_TYPE_IO_3V3_ONLY:
1942 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1945 /* regular case, nothing to do */
1949 * drive-strength offset is special, as it is spread
1950 * over 2 registers, the bit data[15] contains bit 0
1951 * of the value while temp[1:0] contains bits 2 and 1
1953 data = (ret & 0x1) << 15;
1954 temp = (ret >> 0x1) & 0x3;
1956 rmask = BIT(15) | BIT(31);
1958 ret = regmap_update_bits(regmap, reg, rmask, data);
1962 rmask = 0x3 | (0x3 << 16);
1963 temp |= (0x3 << 16);
1965 ret = regmap_update_bits(regmap, reg, rmask, temp);
1969 /* setting fully enclosed in the second register */
1974 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1979 case DRV_TYPE_IO_DEFAULT:
1980 case DRV_TYPE_IO_1V8_OR_3V0:
1981 case DRV_TYPE_IO_1V8_ONLY:
1982 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1985 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1991 /* enable the write to the equivalent lower bits */
1992 data = ((1 << rmask_bits) - 1) << (bit + 16);
1993 rmask = data | (data >> 16);
1994 data |= (ret << bit);
1996 ret = regmap_update_bits(regmap, reg, rmask, data);
2001 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2003 PIN_CONFIG_BIAS_DISABLE,
2004 PIN_CONFIG_BIAS_PULL_UP,
2005 PIN_CONFIG_BIAS_PULL_DOWN,
2006 PIN_CONFIG_BIAS_BUS_HOLD
2009 PIN_CONFIG_BIAS_DISABLE,
2010 PIN_CONFIG_BIAS_PULL_DOWN,
2011 PIN_CONFIG_BIAS_DISABLE,
2012 PIN_CONFIG_BIAS_PULL_UP
2016 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2018 struct rockchip_pinctrl *info = bank->drvdata;
2019 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2020 struct regmap *regmap;
2021 int reg, ret, pull_type;
2025 /* rk3066b does support any pulls */
2026 if (ctrl->type == RK3066B)
2027 return PIN_CONFIG_BIAS_DISABLE;
2029 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2031 ret = regmap_read(regmap, reg, &data);
2035 switch (ctrl->type) {
2038 return !(data & BIT(bit))
2039 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2040 : PIN_CONFIG_BIAS_DISABLE;
2049 pull_type = bank->pull_type[pin_num / 8];
2051 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2053 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2054 * where that pull up value becomes 3.
2056 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2061 return rockchip_pull_list[pull_type][data];
2063 dev_err(info->dev, "unsupported pinctrl type\n");
2068 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2069 int pin_num, int pull)
2071 struct rockchip_pinctrl *info = bank->drvdata;
2072 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2073 struct regmap *regmap;
2074 int reg, ret, i, pull_type;
2078 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2079 bank->bank_num, pin_num, pull);
2081 /* rk3066b does support any pulls */
2082 if (ctrl->type == RK3066B)
2083 return pull ? -EINVAL : 0;
2085 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2087 switch (ctrl->type) {
2090 data = BIT(bit + 16);
2091 if (pull == PIN_CONFIG_BIAS_DISABLE)
2093 ret = regmap_write(regmap, reg, data);
2103 pull_type = bank->pull_type[pin_num / 8];
2105 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2107 if (rockchip_pull_list[pull_type][i] == pull) {
2113 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2114 * where that pull up value becomes 3.
2116 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2122 dev_err(info->dev, "unsupported pull setting %d\n",
2127 /* enable the write to the equivalent lower bits */
2128 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2129 rmask = data | (data >> 16);
2130 data |= (ret << bit);
2132 ret = regmap_update_bits(regmap, reg, rmask, data);
2135 dev_err(info->dev, "unsupported pinctrl type\n");
2142 #define RK3328_SCHMITT_BITS_PER_PIN 1
2143 #define RK3328_SCHMITT_PINS_PER_REG 16
2144 #define RK3328_SCHMITT_BANK_STRIDE 8
2145 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2147 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2149 struct regmap **regmap,
2152 struct rockchip_pinctrl *info = bank->drvdata;
2154 *regmap = info->regmap_base;
2155 *reg = RK3328_SCHMITT_GRF_OFFSET;
2157 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2158 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2159 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2164 #define RK3568_SCHMITT_BITS_PER_PIN 2
2165 #define RK3568_SCHMITT_PINS_PER_REG 8
2166 #define RK3568_SCHMITT_BANK_STRIDE 0x10
2167 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
2168 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2170 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2172 struct regmap **regmap,
2175 struct rockchip_pinctrl *info = bank->drvdata;
2177 if (bank->bank_num == 0) {
2178 *regmap = info->regmap_pmu;
2179 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2181 *regmap = info->regmap_base;
2182 *reg = RK3568_SCHMITT_GRF_OFFSET;
2183 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2186 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
2187 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2188 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
2193 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2195 struct rockchip_pinctrl *info = bank->drvdata;
2196 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2197 struct regmap *regmap;
2202 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2206 ret = regmap_read(regmap, reg, &data);
2211 switch (ctrl->type) {
2213 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2221 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2222 int pin_num, int enable)
2224 struct rockchip_pinctrl *info = bank->drvdata;
2225 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2226 struct regmap *regmap;
2231 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2232 bank->bank_num, pin_num, enable);
2234 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2238 /* enable the write to the equivalent lower bits */
2239 switch (ctrl->type) {
2241 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2242 rmask = data | (data >> 16);
2243 data |= ((enable ? 0x2 : 0x1) << bit);
2246 data = BIT(bit + 16) | (enable << bit);
2247 rmask = BIT(bit + 16) | BIT(bit);
2251 return regmap_update_bits(regmap, reg, rmask, data);
2255 * Pinmux_ops handling
2258 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2260 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2262 return info->nfunctions;
2265 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2268 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2270 return info->functions[selector].name;
2273 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2274 unsigned selector, const char * const **groups,
2275 unsigned * const num_groups)
2277 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2279 *groups = info->functions[selector].groups;
2280 *num_groups = info->functions[selector].ngroups;
2285 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2288 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2289 const unsigned int *pins = info->groups[group].pins;
2290 const struct rockchip_pin_config *data = info->groups[group].data;
2291 struct rockchip_pin_bank *bank;
2294 dev_dbg(info->dev, "enable function %s group %s\n",
2295 info->functions[selector].name, info->groups[group].name);
2298 * for each pin in the pin group selected, program the corresponding
2299 * pin function number in the config register.
2301 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2302 bank = pin_to_bank(info, pins[cnt]);
2303 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2310 /* revert the already done pin settings */
2311 for (cnt--; cnt >= 0; cnt--)
2312 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2320 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2322 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2326 ret = clk_enable(bank->clk);
2328 dev_err(bank->drvdata->dev,
2329 "failed to enable clock for bank %s\n", bank->name);
2332 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2333 clk_disable(bank->clk);
2335 if (data & BIT(offset))
2336 return GPIO_LINE_DIRECTION_OUT;
2338 return GPIO_LINE_DIRECTION_IN;
2342 * The calls to gpio_direction_output() and gpio_direction_input()
2343 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2344 * function called from the gpiolib interface).
2346 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2347 int pin, bool input)
2349 struct rockchip_pin_bank *bank;
2351 unsigned long flags;
2354 bank = gpiochip_get_data(chip);
2356 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2360 clk_enable(bank->clk);
2361 raw_spin_lock_irqsave(&bank->slock, flags);
2363 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2364 /* set bit to 1 for output, 0 for input */
2369 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2371 raw_spin_unlock_irqrestore(&bank->slock, flags);
2372 clk_disable(bank->clk);
2377 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2378 struct pinctrl_gpio_range *range,
2379 unsigned offset, bool input)
2381 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2382 struct gpio_chip *chip;
2386 pin = offset - chip->base;
2387 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2388 offset, range->name, pin, input ? "input" : "output");
2390 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2394 static const struct pinmux_ops rockchip_pmx_ops = {
2395 .get_functions_count = rockchip_pmx_get_funcs_count,
2396 .get_function_name = rockchip_pmx_get_func_name,
2397 .get_function_groups = rockchip_pmx_get_groups,
2398 .set_mux = rockchip_pmx_set,
2399 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2403 * Pinconf_ops handling
2406 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2407 enum pin_config_param pull)
2409 switch (ctrl->type) {
2412 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2413 pull == PIN_CONFIG_BIAS_DISABLE);
2415 return pull ? false : true;
2424 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2430 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2431 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2433 /* set the pin config settings for a specified pin */
2434 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2435 unsigned long *configs, unsigned num_configs)
2437 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2438 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2439 enum pin_config_param param;
2444 for (i = 0; i < num_configs; i++) {
2445 param = pinconf_to_config_param(configs[i]);
2446 arg = pinconf_to_config_argument(configs[i]);
2449 case PIN_CONFIG_BIAS_DISABLE:
2450 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2455 case PIN_CONFIG_BIAS_PULL_UP:
2456 case PIN_CONFIG_BIAS_PULL_DOWN:
2457 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2458 case PIN_CONFIG_BIAS_BUS_HOLD:
2459 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2465 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2470 case PIN_CONFIG_OUTPUT:
2471 rockchip_gpio_set(&bank->gpio_chip,
2472 pin - bank->pin_base, arg);
2473 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2474 pin - bank->pin_base, false);
2478 case PIN_CONFIG_DRIVE_STRENGTH:
2479 /* rk3288 is the first with per-pin drive-strength */
2480 if (!info->ctrl->drv_calc_reg)
2483 rc = rockchip_set_drive_perpin(bank,
2484 pin - bank->pin_base, arg);
2488 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2489 if (!info->ctrl->schmitt_calc_reg)
2492 rc = rockchip_set_schmitt(bank,
2493 pin - bank->pin_base, arg);
2501 } /* for each config */
2506 /* get the pin config settings for a specified pin */
2507 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2508 unsigned long *config)
2510 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2511 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2512 enum pin_config_param param = pinconf_to_config_param(*config);
2517 case PIN_CONFIG_BIAS_DISABLE:
2518 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2523 case PIN_CONFIG_BIAS_PULL_UP:
2524 case PIN_CONFIG_BIAS_PULL_DOWN:
2525 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2526 case PIN_CONFIG_BIAS_BUS_HOLD:
2527 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2530 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2535 case PIN_CONFIG_OUTPUT:
2536 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2537 if (rc != RK_FUNC_GPIO)
2540 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2546 case PIN_CONFIG_DRIVE_STRENGTH:
2547 /* rk3288 is the first with per-pin drive-strength */
2548 if (!info->ctrl->drv_calc_reg)
2551 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2557 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2558 if (!info->ctrl->schmitt_calc_reg)
2561 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2572 *config = pinconf_to_config_packed(param, arg);
2577 static const struct pinconf_ops rockchip_pinconf_ops = {
2578 .pin_config_get = rockchip_pinconf_get,
2579 .pin_config_set = rockchip_pinconf_set,
2583 static const struct of_device_id rockchip_bank_match[] = {
2584 { .compatible = "rockchip,gpio-bank" },
2585 { .compatible = "rockchip,rk3188-gpio-bank0" },
2589 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2590 struct device_node *np)
2592 struct device_node *child;
2594 for_each_child_of_node(np, child) {
2595 if (of_match_node(rockchip_bank_match, child))
2599 info->ngroups += of_get_child_count(child);
2603 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2604 struct rockchip_pin_group *grp,
2605 struct rockchip_pinctrl *info,
2608 struct rockchip_pin_bank *bank;
2615 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2617 /* Initialise group */
2618 grp->name = np->name;
2621 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2622 * do sanity check and calculate pins number
2624 list = of_get_property(np, "rockchip,pins", &size);
2625 /* we do not check return since it's safe node passed down */
2626 size /= sizeof(*list);
2627 if (!size || size % 4) {
2628 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2632 grp->npins = size / 4;
2634 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2636 grp->data = devm_kcalloc(info->dev,
2638 sizeof(struct rockchip_pin_config),
2640 if (!grp->pins || !grp->data)
2643 for (i = 0, j = 0; i < size; i += 4, j++) {
2644 const __be32 *phandle;
2645 struct device_node *np_config;
2647 num = be32_to_cpu(*list++);
2648 bank = bank_num_to_bank(info, num);
2650 return PTR_ERR(bank);
2652 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2653 grp->data[j].func = be32_to_cpu(*list++);
2659 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2660 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2661 &grp->data[j].configs, &grp->data[j].nconfigs);
2662 of_node_put(np_config);
2670 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2671 struct rockchip_pinctrl *info,
2674 struct device_node *child;
2675 struct rockchip_pmx_func *func;
2676 struct rockchip_pin_group *grp;
2678 static u32 grp_index;
2681 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2683 func = &info->functions[index];
2685 /* Initialise function */
2686 func->name = np->name;
2687 func->ngroups = of_get_child_count(np);
2688 if (func->ngroups <= 0)
2691 func->groups = devm_kcalloc(info->dev,
2692 func->ngroups, sizeof(char *), GFP_KERNEL);
2696 for_each_child_of_node(np, child) {
2697 func->groups[i] = child->name;
2698 grp = &info->groups[grp_index++];
2699 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2709 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2710 struct rockchip_pinctrl *info)
2712 struct device *dev = &pdev->dev;
2713 struct device_node *np = dev->of_node;
2714 struct device_node *child;
2718 rockchip_pinctrl_child_count(info, np);
2720 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2721 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2723 info->functions = devm_kcalloc(dev,
2725 sizeof(struct rockchip_pmx_func),
2727 if (!info->functions)
2730 info->groups = devm_kcalloc(dev,
2732 sizeof(struct rockchip_pin_group),
2739 for_each_child_of_node(np, child) {
2740 if (of_match_node(rockchip_bank_match, child))
2743 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2745 dev_err(&pdev->dev, "failed to parse function\n");
2754 static int rockchip_pinctrl_register(struct platform_device *pdev,
2755 struct rockchip_pinctrl *info)
2757 struct pinctrl_desc *ctrldesc = &info->pctl;
2758 struct pinctrl_pin_desc *pindesc, *pdesc;
2759 struct rockchip_pin_bank *pin_bank;
2763 ctrldesc->name = "rockchip-pinctrl";
2764 ctrldesc->owner = THIS_MODULE;
2765 ctrldesc->pctlops = &rockchip_pctrl_ops;
2766 ctrldesc->pmxops = &rockchip_pmx_ops;
2767 ctrldesc->confops = &rockchip_pinconf_ops;
2769 pindesc = devm_kcalloc(&pdev->dev,
2770 info->ctrl->nr_pins, sizeof(*pindesc),
2775 ctrldesc->pins = pindesc;
2776 ctrldesc->npins = info->ctrl->nr_pins;
2779 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2780 pin_bank = &info->ctrl->pin_banks[bank];
2781 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2783 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2784 pin_bank->name, pin);
2789 ret = rockchip_pinctrl_parse_dt(pdev, info);
2793 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2794 if (IS_ERR(info->pctl_dev)) {
2795 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2796 return PTR_ERR(info->pctl_dev);
2799 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2800 pin_bank = &info->ctrl->pin_banks[bank];
2801 pin_bank->grange.name = pin_bank->name;
2802 pin_bank->grange.id = bank;
2803 pin_bank->grange.pin_base = pin_bank->pin_base;
2804 pin_bank->grange.base = pin_bank->gpio_chip.base;
2805 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2806 pin_bank->grange.gc = &pin_bank->gpio_chip;
2807 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2817 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2819 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2820 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2821 unsigned long flags;
2824 clk_enable(bank->clk);
2825 raw_spin_lock_irqsave(&bank->slock, flags);
2828 data &= ~BIT(offset);
2830 data |= BIT(offset);
2833 raw_spin_unlock_irqrestore(&bank->slock, flags);
2834 clk_disable(bank->clk);
2838 * Returns the level of the pin for input direction and setting of the DR
2839 * register for output gpios.
2841 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2843 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2846 clk_enable(bank->clk);
2847 data = readl(bank->reg_base + GPIO_EXT_PORT);
2848 clk_disable(bank->clk);
2855 * gpiolib gpio_direction_input callback function. The setting of the pin
2856 * mux function as 'gpio input' will be handled by the pinctrl subsystem
2859 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2861 return pinctrl_gpio_direction_input(gc->base + offset);
2865 * gpiolib gpio_direction_output callback function. The setting of the pin
2866 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2869 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2870 unsigned offset, int value)
2872 rockchip_gpio_set(gc, offset, value);
2873 return pinctrl_gpio_direction_output(gc->base + offset);
2876 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2877 unsigned int offset, bool enable)
2879 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2880 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2881 unsigned long flags;
2884 clk_enable(bank->clk);
2885 raw_spin_lock_irqsave(&bank->slock, flags);
2889 data |= BIT(offset);
2891 data &= ~BIT(offset);
2894 raw_spin_unlock_irqrestore(&bank->slock, flags);
2895 clk_disable(bank->clk);
2899 * gpiolib set_config callback function. The setting of the pin
2900 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2903 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2904 unsigned long config)
2906 enum pin_config_param param = pinconf_to_config_param(config);
2909 case PIN_CONFIG_INPUT_DEBOUNCE:
2910 rockchip_gpio_set_debounce(gc, offset, true);
2912 * Rockchip's gpio could only support up to one period
2913 * of the debounce clock(pclk), which is far away from
2914 * satisftying the requirement, as pclk is usually near
2915 * 100MHz shared by all peripherals. So the fact is it
2916 * has crippled debounce capability could only be useful
2917 * to prevent any spurious glitches from waking up the system
2918 * if the gpio is conguired as wakeup interrupt source. Let's
2919 * still return -ENOTSUPP as before, to make sure the caller
2920 * of gpiod_set_debounce won't change its behaviour.
2929 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2930 * and a virtual IRQ, if not already present.
2932 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2934 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2940 clk_enable(bank->clk);
2941 virq = irq_create_mapping(bank->domain, offset);
2942 clk_disable(bank->clk);
2944 return (virq) ? : -ENXIO;
2947 static const struct gpio_chip rockchip_gpiolib_chip = {
2948 .request = gpiochip_generic_request,
2949 .free = gpiochip_generic_free,
2950 .set = rockchip_gpio_set,
2951 .get = rockchip_gpio_get,
2952 .get_direction = rockchip_gpio_get_direction,
2953 .direction_input = rockchip_gpio_direction_input,
2954 .direction_output = rockchip_gpio_direction_output,
2955 .set_config = rockchip_gpio_set_config,
2956 .to_irq = rockchip_gpio_to_irq,
2957 .owner = THIS_MODULE,
2961 * Interrupt handling
2964 static void rockchip_irq_demux(struct irq_desc *desc)
2966 struct irq_chip *chip = irq_desc_get_chip(desc);
2967 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2970 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2972 chained_irq_enter(chip, desc);
2974 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2977 unsigned int irq, virq;
2981 virq = irq_find_mapping(bank->domain, irq);
2984 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2988 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2991 * Triggering IRQ on both rising and falling edge
2992 * needs manual intervention.
2994 if (bank->toggle_edge_mode & BIT(irq)) {
2995 u32 data, data_old, polarity;
2996 unsigned long flags;
2998 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
3000 raw_spin_lock_irqsave(&bank->slock, flags);
3002 polarity = readl_relaxed(bank->reg_base +
3004 if (data & BIT(irq))
3005 polarity &= ~BIT(irq);
3007 polarity |= BIT(irq);
3009 bank->reg_base + GPIO_INT_POLARITY);
3011 raw_spin_unlock_irqrestore(&bank->slock, flags);
3014 data = readl_relaxed(bank->reg_base +
3016 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
3019 generic_handle_irq(virq);
3022 chained_irq_exit(chip, desc);
3025 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
3027 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3028 struct rockchip_pin_bank *bank = gc->private;
3029 u32 mask = BIT(d->hwirq);
3033 unsigned long flags;
3036 /* make sure the pin is configured as gpio input */
3037 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3041 clk_enable(bank->clk);
3042 raw_spin_lock_irqsave(&bank->slock, flags);
3044 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3046 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3048 raw_spin_unlock_irqrestore(&bank->slock, flags);
3050 if (type & IRQ_TYPE_EDGE_BOTH)
3051 irq_set_handler_locked(d, handle_edge_irq);
3053 irq_set_handler_locked(d, handle_level_irq);
3055 raw_spin_lock_irqsave(&bank->slock, flags);
3058 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
3059 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
3062 case IRQ_TYPE_EDGE_BOTH:
3063 bank->toggle_edge_mode |= mask;
3067 * Determine gpio state. If 1 next interrupt should be falling
3070 data = readl(bank->reg_base + GPIO_EXT_PORT);
3076 case IRQ_TYPE_EDGE_RISING:
3077 bank->toggle_edge_mode &= ~mask;
3081 case IRQ_TYPE_EDGE_FALLING:
3082 bank->toggle_edge_mode &= ~mask;
3086 case IRQ_TYPE_LEVEL_HIGH:
3087 bank->toggle_edge_mode &= ~mask;
3091 case IRQ_TYPE_LEVEL_LOW:
3092 bank->toggle_edge_mode &= ~mask;
3098 raw_spin_unlock_irqrestore(&bank->slock, flags);
3099 clk_disable(bank->clk);
3103 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
3104 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
3107 raw_spin_unlock_irqrestore(&bank->slock, flags);
3108 clk_disable(bank->clk);
3113 static void rockchip_irq_suspend(struct irq_data *d)
3115 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3116 struct rockchip_pin_bank *bank = gc->private;
3118 clk_enable(bank->clk);
3119 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3120 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
3121 clk_disable(bank->clk);
3124 static void rockchip_irq_resume(struct irq_data *d)
3126 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3127 struct rockchip_pin_bank *bank = gc->private;
3129 clk_enable(bank->clk);
3130 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3131 clk_disable(bank->clk);
3134 static void rockchip_irq_enable(struct irq_data *d)
3136 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3137 struct rockchip_pin_bank *bank = gc->private;
3139 clk_enable(bank->clk);
3140 irq_gc_mask_clr_bit(d);
3143 static void rockchip_irq_disable(struct irq_data *d)
3145 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3146 struct rockchip_pin_bank *bank = gc->private;
3148 irq_gc_mask_set_bit(d);
3149 clk_disable(bank->clk);
3152 static int rockchip_interrupts_register(struct platform_device *pdev,
3153 struct rockchip_pinctrl *info)
3155 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3156 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3157 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3158 struct irq_chip_generic *gc;
3162 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3164 dev_warn(&pdev->dev, "bank %s is not valid\n",
3169 ret = clk_enable(bank->clk);
3171 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3176 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3177 &irq_generic_chip_ops, NULL);
3178 if (!bank->domain) {
3179 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3181 clk_disable(bank->clk);
3185 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3186 "rockchip_gpio_irq", handle_level_irq,
3189 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3191 irq_domain_remove(bank->domain);
3192 clk_disable(bank->clk);
3196 gc = irq_get_domain_generic_chip(bank->domain, 0);
3197 gc->reg_base = bank->reg_base;
3199 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3200 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3201 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3202 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3203 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3204 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3205 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3206 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3207 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3208 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3209 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3210 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3213 * Linux assumes that all interrupts start out disabled/masked.
3214 * Our driver only uses the concept of masked and always keeps
3215 * things enabled, so for us that's all masked and all enabled.
3217 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3218 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3219 gc->mask_cache = 0xffffffff;
3221 irq_set_chained_handler_and_data(bank->irq,
3222 rockchip_irq_demux, bank);
3223 clk_disable(bank->clk);
3229 static int rockchip_gpiolib_register(struct platform_device *pdev,
3230 struct rockchip_pinctrl *info)
3232 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3233 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3234 struct gpio_chip *gc;
3238 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3240 dev_warn(&pdev->dev, "bank %s is not valid\n",
3245 bank->gpio_chip = rockchip_gpiolib_chip;
3247 gc = &bank->gpio_chip;
3248 gc->base = bank->pin_base;
3249 gc->ngpio = bank->nr_pins;
3250 gc->parent = &pdev->dev;
3251 gc->of_node = bank->of_node;
3252 gc->label = bank->name;
3254 ret = gpiochip_add_data(gc, bank);
3256 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3262 rockchip_interrupts_register(pdev, info);
3267 for (--i, --bank; i >= 0; --i, --bank) {
3270 gpiochip_remove(&bank->gpio_chip);
3275 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3276 struct rockchip_pinctrl *info)
3278 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3279 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3282 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3285 gpiochip_remove(&bank->gpio_chip);
3291 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3292 struct rockchip_pinctrl *info)
3294 struct resource res;
3297 if (of_address_to_resource(bank->of_node, 0, &res)) {
3298 dev_err(info->dev, "cannot find IO resource for bank\n");
3302 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3303 if (IS_ERR(bank->reg_base))
3304 return PTR_ERR(bank->reg_base);
3307 * special case, where parts of the pull setting-registers are
3308 * part of the PMU register space
3310 if (of_device_is_compatible(bank->of_node,
3311 "rockchip,rk3188-gpio-bank0")) {
3312 struct device_node *node;
3314 node = of_parse_phandle(bank->of_node->parent,
3317 if (of_address_to_resource(bank->of_node, 1, &res)) {
3318 dev_err(info->dev, "cannot find IO resource for bank\n");
3322 base = devm_ioremap_resource(info->dev, &res);
3324 return PTR_ERR(base);
3325 rockchip_regmap_config.max_register =
3326 resource_size(&res) - 4;
3327 rockchip_regmap_config.name =
3328 "rockchip,rk3188-gpio-bank0-pull";
3329 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3331 &rockchip_regmap_config);
3336 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3338 bank->clk = of_clk_get(bank->of_node, 0);
3339 if (IS_ERR(bank->clk))
3340 return PTR_ERR(bank->clk);
3342 return clk_prepare(bank->clk);
3345 static const struct of_device_id rockchip_pinctrl_dt_match[];
3347 /* retrieve the soc specific data */
3348 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3349 struct rockchip_pinctrl *d,
3350 struct platform_device *pdev)
3352 const struct of_device_id *match;
3353 struct device_node *node = pdev->dev.of_node;
3354 struct device_node *np;
3355 struct rockchip_pin_ctrl *ctrl;
3356 struct rockchip_pin_bank *bank;
3357 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3359 match = of_match_node(rockchip_pinctrl_dt_match, node);
3360 ctrl = (struct rockchip_pin_ctrl *)match->data;
3362 for_each_child_of_node(node, np) {
3363 if (!of_find_property(np, "gpio-controller", NULL))
3366 bank = ctrl->pin_banks;
3367 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3368 if (!strcmp(bank->name, np->name)) {
3371 if (!rockchip_get_bank_data(bank, d))
3379 grf_offs = ctrl->grf_mux_offset;
3380 pmu_offs = ctrl->pmu_mux_offset;
3381 drv_pmu_offs = ctrl->pmu_drv_offset;
3382 drv_grf_offs = ctrl->grf_drv_offset;
3383 bank = ctrl->pin_banks;
3384 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3387 raw_spin_lock_init(&bank->slock);
3389 bank->pin_base = ctrl->nr_pins;
3390 ctrl->nr_pins += bank->nr_pins;
3392 /* calculate iomux and drv offsets */
3393 for (j = 0; j < 4; j++) {
3394 struct rockchip_iomux *iom = &bank->iomux[j];
3395 struct rockchip_drv *drv = &bank->drv[j];
3398 if (bank_pins >= bank->nr_pins)
3401 /* preset iomux offset value, set new start value */
3402 if (iom->offset >= 0) {
3403 if (iom->type & IOMUX_SOURCE_PMU)
3404 pmu_offs = iom->offset;
3406 grf_offs = iom->offset;
3407 } else { /* set current iomux offset */
3408 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3409 pmu_offs : grf_offs;
3412 /* preset drv offset value, set new start value */
3413 if (drv->offset >= 0) {
3414 if (iom->type & IOMUX_SOURCE_PMU)
3415 drv_pmu_offs = drv->offset;
3417 drv_grf_offs = drv->offset;
3418 } else { /* set current drv offset */
3419 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3420 drv_pmu_offs : drv_grf_offs;
3423 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3424 i, j, iom->offset, drv->offset);
3427 * Increase offset according to iomux width.
3428 * 4bit iomux'es are spread over two registers.
3430 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3432 IOMUX_WIDTH_2BIT)) ? 8 : 4;
3433 if (iom->type & IOMUX_SOURCE_PMU)
3439 * Increase offset according to drv width.
3440 * 3bit drive-strenth'es are spread over two registers.
3442 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3443 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3448 if (iom->type & IOMUX_SOURCE_PMU)
3449 drv_pmu_offs += inc;
3451 drv_grf_offs += inc;
3456 /* calculate the per-bank recalced_mask */
3457 for (j = 0; j < ctrl->niomux_recalced; j++) {
3460 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3461 pin = ctrl->iomux_recalced[j].pin;
3462 bank->recalced_mask |= BIT(pin);
3466 /* calculate the per-bank route_mask */
3467 for (j = 0; j < ctrl->niomux_routes; j++) {
3470 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3471 pin = ctrl->iomux_routes[j].pin;
3472 bank->route_mask |= BIT(pin);
3480 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3481 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3483 static u32 rk3288_grf_gpio6c_iomux;
3485 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3487 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3488 int ret = pinctrl_force_sleep(info->pctl_dev);
3494 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3495 * the setting here, and restore it at resume.
3497 if (info->ctrl->type == RK3288) {
3498 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3499 &rk3288_grf_gpio6c_iomux);
3501 pinctrl_force_default(info->pctl_dev);
3509 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3511 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3514 if (info->ctrl->type == RK3288) {
3515 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3516 rk3288_grf_gpio6c_iomux |
3517 GPIO6C6_SEL_WRITE_ENABLE);
3522 return pinctrl_force_default(info->pctl_dev);
3525 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3526 rockchip_pinctrl_resume);
3528 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3530 struct rockchip_pinctrl *info;
3531 struct device *dev = &pdev->dev;
3532 struct rockchip_pin_ctrl *ctrl;
3533 struct device_node *np = pdev->dev.of_node, *node;
3534 struct resource *res;
3538 if (!dev->of_node) {
3539 dev_err(dev, "device tree node not found\n");
3543 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3549 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3551 dev_err(dev, "driver data not available\n");
3556 node = of_parse_phandle(np, "rockchip,grf", 0);
3558 info->regmap_base = syscon_node_to_regmap(node);
3560 if (IS_ERR(info->regmap_base))
3561 return PTR_ERR(info->regmap_base);
3563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3564 base = devm_ioremap_resource(&pdev->dev, res);
3566 return PTR_ERR(base);
3568 rockchip_regmap_config.max_register = resource_size(res) - 4;
3569 rockchip_regmap_config.name = "rockchip,pinctrl";
3570 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3571 &rockchip_regmap_config);
3573 /* to check for the old dt-bindings */
3574 info->reg_size = resource_size(res);
3576 /* Honor the old binding, with pull registers as 2nd resource */
3577 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3578 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3579 base = devm_ioremap_resource(&pdev->dev, res);
3581 return PTR_ERR(base);
3583 rockchip_regmap_config.max_register =
3584 resource_size(res) - 4;
3585 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3586 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3588 &rockchip_regmap_config);
3592 /* try to find the optional reference to the pmu syscon */
3593 node = of_parse_phandle(np, "rockchip,pmu", 0);
3595 info->regmap_pmu = syscon_node_to_regmap(node);
3597 if (IS_ERR(info->regmap_pmu))
3598 return PTR_ERR(info->regmap_pmu);
3601 ret = rockchip_gpiolib_register(pdev, info);
3605 ret = rockchip_pinctrl_register(pdev, info);
3607 rockchip_gpiolib_unregister(pdev, info);
3611 platform_set_drvdata(pdev, info);
3616 static struct rockchip_pin_bank px30_pin_banks[] = {
3617 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3622 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3627 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3632 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3639 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3640 .pin_banks = px30_pin_banks,
3641 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3642 .label = "PX30-GPIO",
3644 .grf_mux_offset = 0x0,
3645 .pmu_mux_offset = 0x0,
3646 .iomux_routes = px30_mux_route_data,
3647 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3648 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3649 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3650 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3653 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3654 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3658 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3659 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3660 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3663 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3664 .pin_banks = rv1108_pin_banks,
3665 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3666 .label = "RV1108-GPIO",
3668 .grf_mux_offset = 0x10,
3669 .pmu_mux_offset = 0x0,
3670 .iomux_recalced = rv1108_mux_recalced_data,
3671 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3672 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3673 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3674 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3677 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3678 PIN_BANK(0, 32, "gpio0"),
3679 PIN_BANK(1, 32, "gpio1"),
3680 PIN_BANK(2, 32, "gpio2"),
3681 PIN_BANK(3, 32, "gpio3"),
3684 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3685 .pin_banks = rk2928_pin_banks,
3686 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3687 .label = "RK2928-GPIO",
3689 .grf_mux_offset = 0xa8,
3690 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3693 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3694 PIN_BANK(0, 32, "gpio0"),
3695 PIN_BANK(1, 32, "gpio1"),
3696 PIN_BANK(2, 32, "gpio2"),
3699 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3700 .pin_banks = rk3036_pin_banks,
3701 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3702 .label = "RK3036-GPIO",
3704 .grf_mux_offset = 0xa8,
3705 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3708 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3709 PIN_BANK(0, 32, "gpio0"),
3710 PIN_BANK(1, 32, "gpio1"),
3711 PIN_BANK(2, 32, "gpio2"),
3712 PIN_BANK(3, 32, "gpio3"),
3713 PIN_BANK(4, 32, "gpio4"),
3714 PIN_BANK(6, 16, "gpio6"),
3717 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3718 .pin_banks = rk3066a_pin_banks,
3719 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3720 .label = "RK3066a-GPIO",
3722 .grf_mux_offset = 0xa8,
3723 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3726 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3727 PIN_BANK(0, 32, "gpio0"),
3728 PIN_BANK(1, 32, "gpio1"),
3729 PIN_BANK(2, 32, "gpio2"),
3730 PIN_BANK(3, 32, "gpio3"),
3733 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3734 .pin_banks = rk3066b_pin_banks,
3735 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3736 .label = "RK3066b-GPIO",
3738 .grf_mux_offset = 0x60,
3741 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3742 PIN_BANK(0, 32, "gpio0"),
3743 PIN_BANK(1, 32, "gpio1"),
3744 PIN_BANK(2, 32, "gpio2"),
3745 PIN_BANK(3, 32, "gpio3"),
3748 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3749 .pin_banks = rk3128_pin_banks,
3750 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3751 .label = "RK3128-GPIO",
3753 .grf_mux_offset = 0xa8,
3754 .iomux_recalced = rk3128_mux_recalced_data,
3755 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3756 .iomux_routes = rk3128_mux_route_data,
3757 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3758 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3761 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3762 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3763 PIN_BANK(1, 32, "gpio1"),
3764 PIN_BANK(2, 32, "gpio2"),
3765 PIN_BANK(3, 32, "gpio3"),
3768 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3769 .pin_banks = rk3188_pin_banks,
3770 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3771 .label = "RK3188-GPIO",
3773 .grf_mux_offset = 0x60,
3774 .iomux_routes = rk3188_mux_route_data,
3775 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3776 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3779 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3780 PIN_BANK(0, 32, "gpio0"),
3781 PIN_BANK(1, 32, "gpio1"),
3782 PIN_BANK(2, 32, "gpio2"),
3783 PIN_BANK(3, 32, "gpio3"),
3786 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3787 .pin_banks = rk3228_pin_banks,
3788 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3789 .label = "RK3228-GPIO",
3791 .grf_mux_offset = 0x0,
3792 .iomux_routes = rk3228_mux_route_data,
3793 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3794 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3795 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3798 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3799 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3804 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3809 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3810 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3811 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3816 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3821 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3822 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3827 PIN_BANK(8, 16, "gpio8"),
3830 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3831 .pin_banks = rk3288_pin_banks,
3832 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3833 .label = "RK3288-GPIO",
3835 .grf_mux_offset = 0x0,
3836 .pmu_mux_offset = 0x84,
3837 .iomux_routes = rk3288_mux_route_data,
3838 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3839 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3840 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3843 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3844 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3848 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3852 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3856 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3860 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3866 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3867 .pin_banks = rk3308_pin_banks,
3868 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3869 .label = "RK3308-GPIO",
3871 .grf_mux_offset = 0x0,
3872 .iomux_recalced = rk3308_mux_recalced_data,
3873 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3874 .iomux_routes = rk3308_mux_route_data,
3875 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3876 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3877 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3878 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3881 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3882 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3883 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3884 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3888 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3895 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3896 .pin_banks = rk3328_pin_banks,
3897 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3898 .label = "RK3328-GPIO",
3900 .grf_mux_offset = 0x0,
3901 .iomux_recalced = rk3328_mux_recalced_data,
3902 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3903 .iomux_routes = rk3328_mux_route_data,
3904 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3905 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3906 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3907 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3910 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3911 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3916 PIN_BANK(1, 32, "gpio1"),
3917 PIN_BANK(2, 32, "gpio2"),
3918 PIN_BANK(3, 32, "gpio3"),
3921 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3922 .pin_banks = rk3368_pin_banks,
3923 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3924 .label = "RK3368-GPIO",
3926 .grf_mux_offset = 0x0,
3927 .pmu_mux_offset = 0x0,
3928 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3929 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3932 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3933 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3938 DRV_TYPE_IO_1V8_ONLY,
3939 DRV_TYPE_IO_1V8_ONLY,
3940 DRV_TYPE_IO_DEFAULT,
3941 DRV_TYPE_IO_DEFAULT,
3946 PULL_TYPE_IO_1V8_ONLY,
3947 PULL_TYPE_IO_1V8_ONLY,
3948 PULL_TYPE_IO_DEFAULT,
3949 PULL_TYPE_IO_DEFAULT
3951 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3955 DRV_TYPE_IO_1V8_OR_3V0,
3956 DRV_TYPE_IO_1V8_OR_3V0,
3957 DRV_TYPE_IO_1V8_OR_3V0,
3958 DRV_TYPE_IO_1V8_OR_3V0,
3964 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3965 DRV_TYPE_IO_1V8_OR_3V0,
3966 DRV_TYPE_IO_1V8_ONLY,
3967 DRV_TYPE_IO_1V8_ONLY,
3968 PULL_TYPE_IO_DEFAULT,
3969 PULL_TYPE_IO_DEFAULT,
3970 PULL_TYPE_IO_1V8_ONLY,
3971 PULL_TYPE_IO_1V8_ONLY
3973 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3974 DRV_TYPE_IO_3V3_ONLY,
3975 DRV_TYPE_IO_3V3_ONLY,
3976 DRV_TYPE_IO_1V8_OR_3V0
3978 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3979 DRV_TYPE_IO_1V8_3V0_AUTO,
3980 DRV_TYPE_IO_1V8_OR_3V0,
3981 DRV_TYPE_IO_1V8_OR_3V0
3985 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3986 .pin_banks = rk3399_pin_banks,
3987 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3988 .label = "RK3399-GPIO",
3990 .grf_mux_offset = 0xe000,
3991 .pmu_mux_offset = 0x0,
3992 .grf_drv_offset = 0xe100,
3993 .pmu_drv_offset = 0x80,
3994 .iomux_routes = rk3399_mux_route_data,
3995 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3996 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3997 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4000 static struct rockchip_pin_bank rk3568_pin_banks[] = {
4001 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4002 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4003 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4004 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
4005 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4009 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4013 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4017 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4023 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
4024 .pin_banks = rk3568_pin_banks,
4025 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
4026 .label = "RK3568-GPIO",
4028 .grf_mux_offset = 0x0,
4029 .pmu_mux_offset = 0x0,
4030 .grf_drv_offset = 0x0200,
4031 .pmu_drv_offset = 0x0070,
4032 .iomux_routes = rk3568_mux_route_data,
4033 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
4034 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
4035 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
4036 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4039 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4040 { .compatible = "rockchip,px30-pinctrl",
4041 .data = &px30_pin_ctrl },
4042 { .compatible = "rockchip,rv1108-pinctrl",
4043 .data = &rv1108_pin_ctrl },
4044 { .compatible = "rockchip,rk2928-pinctrl",
4045 .data = &rk2928_pin_ctrl },
4046 { .compatible = "rockchip,rk3036-pinctrl",
4047 .data = &rk3036_pin_ctrl },
4048 { .compatible = "rockchip,rk3066a-pinctrl",
4049 .data = &rk3066a_pin_ctrl },
4050 { .compatible = "rockchip,rk3066b-pinctrl",
4051 .data = &rk3066b_pin_ctrl },
4052 { .compatible = "rockchip,rk3128-pinctrl",
4053 .data = (void *)&rk3128_pin_ctrl },
4054 { .compatible = "rockchip,rk3188-pinctrl",
4055 .data = &rk3188_pin_ctrl },
4056 { .compatible = "rockchip,rk3228-pinctrl",
4057 .data = &rk3228_pin_ctrl },
4058 { .compatible = "rockchip,rk3288-pinctrl",
4059 .data = &rk3288_pin_ctrl },
4060 { .compatible = "rockchip,rk3308-pinctrl",
4061 .data = &rk3308_pin_ctrl },
4062 { .compatible = "rockchip,rk3328-pinctrl",
4063 .data = &rk3328_pin_ctrl },
4064 { .compatible = "rockchip,rk3368-pinctrl",
4065 .data = &rk3368_pin_ctrl },
4066 { .compatible = "rockchip,rk3399-pinctrl",
4067 .data = &rk3399_pin_ctrl },
4068 { .compatible = "rockchip,rk3568-pinctrl",
4069 .data = &rk3568_pin_ctrl },
4073 static struct platform_driver rockchip_pinctrl_driver = {
4074 .probe = rockchip_pinctrl_probe,
4076 .name = "rockchip-pinctrl",
4077 .pm = &rockchip_pinctrl_dev_pm_ops,
4078 .of_match_table = rockchip_pinctrl_dt_match,
4082 static int __init rockchip_pinctrl_drv_register(void)
4084 return platform_driver_register(&rockchip_pinctrl_driver);
4086 postcore_initcall(rockchip_pinctrl_drv_register);