drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <heiko@sntech.de>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              https://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/io.h>
  21 #include <linux/bitops.h>
  22 #include <linux/gpio/driver.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pinctrl/machine.h>
  26 #include <linux/pinctrl/pinconf.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/clk.h>
  32 #include <linux/regmap.h>
  33 #include <linux/mfd/syscon.h>
  34 #include <dt-bindings/pinctrl/rockchip.h>
  35
  36 #include "core.h"
  37 #include "pinconf.h"
  38
  39 /* GPIO control registers */
  40 #define GPIO_SWPORT_DR          0x00
  41 #define GPIO_SWPORT_DDR         0x04
  42 #define GPIO_INTEN              0x30
  43 #define GPIO_INTMASK            0x34
  44 #define GPIO_INTTYPE_LEVEL      0x38
  45 #define GPIO_INT_POLARITY       0x3c
  46 #define GPIO_INT_STATUS         0x40
  47 #define GPIO_INT_RAWSTATUS      0x44
  48 #define GPIO_DEBOUNCE           0x48
  49 #define GPIO_PORTS_EOI          0x4c
  50 #define GPIO_EXT_PORT           0x50
  51 #define GPIO_LS_SYNC            0x60
  52
  53 enum rockchip_pinctrl_type {
  54         PX30,
  55         RV1108,
  56         RK2928,
  57         RK3066B,
  58         RK3128,
  59         RK3188,
  60         RK3288,
  61         RK3308,
  62         RK3368,
  63         RK3399,
  64 };
  65
  66 /*
  67  * Encode variants of iomux registers into a type variable
  68  */
  69 #define IOMUX_GPIO_ONLY         BIT(0)
  70 #define IOMUX_WIDTH_4BIT        BIT(1)
  71 #define IOMUX_SOURCE_PMU        BIT(2)
  72 #define IOMUX_UNROUTED          BIT(3)
  73 #define IOMUX_WIDTH_3BIT        BIT(4)
  74 #define IOMUX_WIDTH_2BIT        BIT(5)
  75
  76 /**
  77  * struct rockchip_iomux
  78  * @type: iomux variant using IOMUX_* constants
  79  * @offset: if initialized to -1 it will be autocalculated, by specifying
  80  *          an initial offset value the relevant source offset can be reset
  81  *          to a new value for autocalculating the following iomux registers.
  82  */
  83 struct rockchip_iomux {
  84         int                             type;
  85         int                             offset;
  86 };
  87
  88 /*
  89  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  90  */
  91 enum rockchip_pin_drv_type {
  92         DRV_TYPE_IO_DEFAULT = 0,
  93         DRV_TYPE_IO_1V8_OR_3V0,
  94         DRV_TYPE_IO_1V8_ONLY,
  95         DRV_TYPE_IO_1V8_3V0_AUTO,
  96         DRV_TYPE_IO_3V3_ONLY,
  97         DRV_TYPE_MAX
  98 };
  99
 100 /*
 101  * enum type index corresponding to rockchip_pull_list arrays index.
 102  */
 103 enum rockchip_pin_pull_type {
 104         PULL_TYPE_IO_DEFAULT = 0,
 105         PULL_TYPE_IO_1V8_ONLY,
 106         PULL_TYPE_MAX
 107 };
 108
 109 /**
 110  * struct rockchip_drv
 111  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 112  * @offset: if initialized to -1 it will be autocalculated, by specifying
 113  *          an initial offset value the relevant source offset can be reset
 114  *          to a new value for autocalculating the following drive strength
 115  *          registers. if used chips own cal_drv func instead to calculate
 116  *          registers offset, the variant could be ignored.
 117  */
 118 struct rockchip_drv {
 119         enum rockchip_pin_drv_type      drv_type;
 120         int                             offset;
 121 };
 122
 123 /**
 124  * struct rockchip_pin_bank
 125  * @reg_base: register base of the gpio bank
 126  * @regmap_pull: optional separate register for additional pull settings
 127  * @clk: clock of the gpio bank
 128  * @irq: interrupt of the gpio bank
 129  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 130  * @pin_base: first pin number
 131  * @nr_pins: number of pins in this bank
 132  * @name: name of the bank
 133  * @bank_num: number of the bank, to account for holes
 134  * @iomux: array describing the 4 iomux sources of the bank
 135  * @drv: array describing the 4 drive strength sources of the bank
 136  * @pull_type: array describing the 4 pull type sources of the bank
 137  * @valid: is all necessary information present
 138  * @of_node: dt node of this bank
 139  * @drvdata: common pinctrl basedata
 140  * @domain: irqdomain of the gpio bank
 141  * @gpio_chip: gpiolib chip
 142  * @grange: gpio range
 143  * @slock: spinlock for the gpio bank
 144  * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
 145  * @recalced_mask: bit mask to indicate a need to recalulate the mask
 146  * @route_mask: bits describing the routing pins of per bank
 147  */
 148 struct rockchip_pin_bank {
 149         void __iomem                    *reg_base;
 150         struct regmap                   *regmap_pull;
 151         struct clk                      *clk;
 152         int                             irq;
 153         u32                             saved_masks;
 154         u32                             pin_base;
 155         u8                              nr_pins;
 156         char                            *name;
 157         u8                              bank_num;
 158         struct rockchip_iomux           iomux[4];
 159         struct rockchip_drv             drv[4];
 160         enum rockchip_pin_pull_type     pull_type[4];
 161         bool                            valid;
 162         struct device_node              *of_node;
 163         struct rockchip_pinctrl         *drvdata;
 164         struct irq_domain               *domain;
 165         struct gpio_chip                gpio_chip;
 166         struct pinctrl_gpio_range       grange;
 167         raw_spinlock_t                  slock;
 168         u32                             toggle_edge_mode;
 169         u32                             recalced_mask;
 170         u32                             route_mask;
 171 };
 172
 173 #define PIN_BANK(id, pins, label)                       \
 174         {                                               \
 175                 .bank_num       = id,                   \
 176                 .nr_pins        = pins,                 \
 177                 .name           = label,                \
 178                 .iomux          = {                     \
 179                         { .offset = -1 },               \
 180                         { .offset = -1 },               \
 181                         { .offset = -1 },               \
 182                         { .offset = -1 },               \
 183                 },                                      \
 184         }
 185
 186 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 187         {                                                               \
 188                 .bank_num       = id,                                   \
 189                 .nr_pins        = pins,                                 \
 190                 .name           = label,                                \
 191                 .iomux          = {                                     \
 192                         { .type = iom0, .offset = -1 },                 \
 193                         { .type = iom1, .offset = -1 },                 \
 194                         { .type = iom2, .offset = -1 },                 \
 195                         { .type = iom3, .offset = -1 },                 \
 196                 },                                                      \
 197         }
 198
 199 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 200         {                                                               \
 201                 .bank_num       = id,                                   \
 202                 .nr_pins        = pins,                                 \
 203                 .name           = label,                                \
 204                 .iomux          = {                                     \
 205                         { .offset = -1 },                               \
 206                         { .offset = -1 },                               \
 207                         { .offset = -1 },                               \
 208                         { .offset = -1 },                               \
 209                 },                                                      \
 210                 .drv            = {                                     \
 211                         { .drv_type = type0, .offset = -1 },            \
 212                         { .drv_type = type1, .offset = -1 },            \
 213                         { .drv_type = type2, .offset = -1 },            \
 214                         { .drv_type = type3, .offset = -1 },            \
 215                 },                                                      \
 216         }
 217
 218 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 219                                       drv2, drv3, pull0, pull1,         \
 220                                       pull2, pull3)                     \
 221         {                                                               \
 222                 .bank_num       = id,                                   \
 223                 .nr_pins        = pins,                                 \
 224                 .name           = label,                                \
 225                 .iomux          = {                                     \
 226                         { .offset = -1 },                               \
 227                         { .offset = -1 },                               \
 228                         { .offset = -1 },                               \
 229                         { .offset = -1 },                               \
 230                 },                                                      \
 231                 .drv            = {                                     \
 232                         { .drv_type = drv0, .offset = -1 },             \
 233                         { .drv_type = drv1, .offset = -1 },             \
 234                         { .drv_type = drv2, .offset = -1 },             \
 235                         { .drv_type = drv3, .offset = -1 },             \
 236                 },                                                      \
 237                 .pull_type[0] = pull0,                                  \
 238                 .pull_type[1] = pull1,                                  \
 239                 .pull_type[2] = pull2,                                  \
 240                 .pull_type[3] = pull3,                                  \
 241         }
 242
 243 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 244                                         iom2, iom3, drv0, drv1, drv2,   \
 245                                         drv3, offset0, offset1,         \
 246                                         offset2, offset3)               \
 247         {                                                               \
 248                 .bank_num       = id,                                   \
 249                 .nr_pins        = pins,                                 \
 250                 .name           = label,                                \
 251                 .iomux          = {                                     \
 252                         { .type = iom0, .offset = -1 },                 \
 253                         { .type = iom1, .offset = -1 },                 \
 254                         { .type = iom2, .offset = -1 },                 \
 255                         { .type = iom3, .offset = -1 },                 \
 256                 },                                                      \
 257                 .drv            = {                                     \
 258                         { .drv_type = drv0, .offset = offset0 },        \
 259                         { .drv_type = drv1, .offset = offset1 },        \
 260                         { .drv_type = drv2, .offset = offset2 },        \
 261                         { .drv_type = drv3, .offset = offset3 },        \
 262                 },                                                      \
 263         }
 264
 265 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 266                                               label, iom0, iom1, iom2,  \
 267                                               iom3, drv0, drv1, drv2,   \
 268                                               drv3, offset0, offset1,   \
 269                                               offset2, offset3, pull0,  \
 270                                               pull1, pull2, pull3)      \
 271         {                                                               \
 272                 .bank_num       = id,                                   \
 273                 .nr_pins        = pins,                                 \
 274                 .name           = label,                                \
 275                 .iomux          = {                                     \
 276                         { .type = iom0, .offset = -1 },                 \
 277                         { .type = iom1, .offset = -1 },                 \
 278                         { .type = iom2, .offset = -1 },                 \
 279                         { .type = iom3, .offset = -1 },                 \
 280                 },                                                      \
 281                 .drv            = {                                     \
 282                         { .drv_type = drv0, .offset = offset0 },        \
 283                         { .drv_type = drv1, .offset = offset1 },        \
 284                         { .drv_type = drv2, .offset = offset2 },        \
 285                         { .drv_type = drv3, .offset = offset3 },        \
 286                 },                                                      \
 287                 .pull_type[0] = pull0,                                  \
 288                 .pull_type[1] = pull1,                                  \
 289                 .pull_type[2] = pull2,                                  \
 290                 .pull_type[3] = pull3,                                  \
 291         }
 292
 293 /**
 294  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 295  * @num: bank number.
 296  * @pin: pin number.
 297  * @bit: index at register.
 298  * @reg: register offset.
 299  * @mask: mask bit
 300  */
 301 struct rockchip_mux_recalced_data {
 302         u8 num;
 303         u8 pin;
 304         u32 reg;
 305         u8 bit;
 306         u8 mask;
 307 };
 308
 309 enum rockchip_mux_route_location {
 310         ROCKCHIP_ROUTE_SAME = 0,
 311         ROCKCHIP_ROUTE_PMU,
 312         ROCKCHIP_ROUTE_GRF,
 313 };
 314
 315 /**
 316  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 317  * @bank_num: bank number.
 318  * @pin: index at register or used to calc index.
 319  * @func: the min pin.
 320  * @route_location: the mux route location (same, pmu, grf).
 321  * @route_offset: the max pin.
 322  * @route_val: the register offset.
 323  */
 324 struct rockchip_mux_route_data {
 325         u8 bank_num;
 326         u8 pin;
 327         u8 func;
 328         enum rockchip_mux_route_location route_location;
 329         u32 route_offset;
 330         u32 route_val;
 331 };
 332
 333 struct rockchip_pin_ctrl {
 334         struct rockchip_pin_bank        *pin_banks;
 335         u32                             nr_banks;
 336         u32                             nr_pins;
 337         char                            *label;
 338         enum rockchip_pinctrl_type      type;
 339         int                             grf_mux_offset;
 340         int                             pmu_mux_offset;
 341         int                             grf_drv_offset;
 342         int                             pmu_drv_offset;
 343         struct rockchip_mux_recalced_data *iomux_recalced;
 344         u32                             niomux_recalced;
 345         struct rockchip_mux_route_data *iomux_routes;
 346         u32                             niomux_routes;
 347
 348         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 349                                     int pin_num, struct regmap **regmap,
 350                                     int *reg, u8 *bit);
 351         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 352                                     int pin_num, struct regmap **regmap,
 353                                     int *reg, u8 *bit);
 354         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 355                                     int pin_num, struct regmap **regmap,
 356                                     int *reg, u8 *bit);
 357 };
 358
 359 struct rockchip_pin_config {
 360         unsigned int            func;
 361         unsigned long           *configs;
 362         unsigned int            nconfigs;
 363 };
 364
 365 /**
 366  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 367  * @name: name of the pin group, used to lookup the group.
 368  * @pins: the pins included in this group.
 369  * @npins: number of pins included in this group.
 370  * @data: local pin configuration
 371  */
 372 struct rockchip_pin_group {
 373         const char                      *name;
 374         unsigned int                    npins;
 375         unsigned int                    *pins;
 376         struct rockchip_pin_config      *data;
 377 };
 378
 379 /**
 380  * struct rockchip_pmx_func: represent a pin function.
 381  * @name: name of the pin function, used to lookup the function.
 382  * @groups: one or more names of pin groups that provide this function.
 383  * @ngroups: number of groups included in @groups.
 384  */
 385 struct rockchip_pmx_func {
 386         const char              *name;
 387         const char              **groups;
 388         u8                      ngroups;
 389 };
 390
 391 struct rockchip_pinctrl {
 392         struct regmap                   *regmap_base;
 393         int                             reg_size;
 394         struct regmap                   *regmap_pull;
 395         struct regmap                   *regmap_pmu;
 396         struct device                   *dev;
 397         struct rockchip_pin_ctrl        *ctrl;
 398         struct pinctrl_desc             pctl;
 399         struct pinctrl_dev              *pctl_dev;
 400         struct rockchip_pin_group       *groups;
 401         unsigned int                    ngroups;
 402         struct rockchip_pmx_func        *functions;
 403         unsigned int                    nfunctions;
 404 };
 405
 406 static struct regmap_config rockchip_regmap_config = {
 407         .reg_bits = 32,
 408         .val_bits = 32,
 409         .reg_stride = 4,
 410 };
 411
 412 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 413                                         const struct rockchip_pinctrl *info,
 414                                         const char *name)
 415 {
 416         int i;
 417
 418         for (i = 0; i < info->ngroups; i++) {
 419                 if (!strcmp(info->groups[i].name, name))
 420                         return &info->groups[i];
 421         }
 422
 423         return NULL;
 424 }
 425
 426 /*
 427  * given a pin number that is local to a pin controller, find out the pin bank
 428  * and the register base of the pin bank.
 429  */
 430 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 431                                                                 unsigned pin)
 432 {
 433         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 434
 435         while (pin >= (b->pin_base + b->nr_pins))
 436                 b++;
 437
 438         return b;
 439 }
 440
 441 static struct rockchip_pin_bank *bank_num_to_bank(
 442                                         struct rockchip_pinctrl *info,
 443                                         unsigned num)
 444 {
 445         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 446         int i;
 447
 448         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 449                 if (b->bank_num == num)
 450                         return b;
 451         }
 452
 453         return ERR_PTR(-EINVAL);
 454 }
 455
 456 /*
 457  * Pinctrl_ops handling
 458  */
 459
 460 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 461 {
 462         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 463
 464         return info->ngroups;
 465 }
 466
 467 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 468                                                         unsigned selector)
 469 {
 470         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 471
 472         return info->groups[selector].name;
 473 }
 474
 475 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 476                                       unsigned selector, const unsigned **pins,
 477                                       unsigned *npins)
 478 {
 479         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 480
 481         if (selector >= info->ngroups)
 482                 return -EINVAL;
 483
 484         *pins = info->groups[selector].pins;
 485         *npins = info->groups[selector].npins;
 486
 487         return 0;
 488 }
 489
 490 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 491                                  struct device_node *np,
 492                                  struct pinctrl_map **map, unsigned *num_maps)
 493 {
 494         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 495         const struct rockchip_pin_group *grp;
 496         struct pinctrl_map *new_map;
 497         struct device_node *parent;
 498         int map_num = 1;
 499         int i;
 500
 501         /*
 502          * first find the group of this node and check if we need to create
 503          * config maps for pins
 504          */
 505         grp = pinctrl_name_to_group(info, np->name);
 506         if (!grp) {
 507                 dev_err(info->dev, "unable to find group for node %pOFn\n",
 508                         np);
 509                 return -EINVAL;
 510         }
 511
 512         map_num += grp->npins;
 513
 514         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 515         if (!new_map)
 516                 return -ENOMEM;
 517
 518         *map = new_map;
 519         *num_maps = map_num;
 520
 521         /* create mux map */
 522         parent = of_get_parent(np);
 523         if (!parent) {
 524                 kfree(new_map);
 525                 return -EINVAL;
 526         }
 527         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 528         new_map[0].data.mux.function = parent->name;
 529         new_map[0].data.mux.group = np->name;
 530         of_node_put(parent);
 531
 532         /* create config map */
 533         new_map++;
 534         for (i = 0; i < grp->npins; i++) {
 535                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 536                 new_map[i].data.configs.group_or_pin =
 537                                 pin_get_name(pctldev, grp->pins[i]);
 538                 new_map[i].data.configs.configs = grp->data[i].configs;
 539                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 540         }
 541
 542         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 543                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 544
 545         return 0;
 546 }
 547
 548 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 549                                     struct pinctrl_map *map, unsigned num_maps)
 550 {
 551         kfree(map);
 552 }
 553
 554 static const struct pinctrl_ops rockchip_pctrl_ops = {
 555         .get_groups_count       = rockchip_get_groups_count,
 556         .get_group_name         = rockchip_get_group_name,
 557         .get_group_pins         = rockchip_get_group_pins,
 558         .dt_node_to_map         = rockchip_dt_node_to_map,
 559         .dt_free_map            = rockchip_dt_free_map,
 560 };
 561
 562 /*
 563  * Hardware access
 564  */
 565
 566 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 567         {
 568                 .num = 1,
 569                 .pin = 0,
 570                 .reg = 0x418,
 571                 .bit = 0,
 572                 .mask = 0x3
 573         }, {
 574                 .num = 1,
 575                 .pin = 1,
 576                 .reg = 0x418,
 577                 .bit = 2,
 578                 .mask = 0x3
 579         }, {
 580                 .num = 1,
 581                 .pin = 2,
 582                 .reg = 0x418,
 583                 .bit = 4,
 584                 .mask = 0x3
 585         }, {
 586                 .num = 1,
 587                 .pin = 3,
 588                 .reg = 0x418,
 589                 .bit = 6,
 590                 .mask = 0x3
 591         }, {
 592                 .num = 1,
 593                 .pin = 4,
 594                 .reg = 0x418,
 595                 .bit = 8,
 596                 .mask = 0x3
 597         }, {
 598                 .num = 1,
 599                 .pin = 5,
 600                 .reg = 0x418,
 601                 .bit = 10,
 602                 .mask = 0x3
 603         }, {
 604                 .num = 1,
 605                 .pin = 6,
 606                 .reg = 0x418,
 607                 .bit = 12,
 608                 .mask = 0x3
 609         }, {
 610                 .num = 1,
 611                 .pin = 7,
 612                 .reg = 0x418,
 613                 .bit = 14,
 614                 .mask = 0x3
 615         }, {
 616                 .num = 1,
 617                 .pin = 8,
 618                 .reg = 0x41c,
 619                 .bit = 0,
 620                 .mask = 0x3
 621         }, {
 622                 .num = 1,
 623                 .pin = 9,
 624                 .reg = 0x41c,
 625                 .bit = 2,
 626                 .mask = 0x3
 627         },
 628 };
 629
 630 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 631         {
 632                 .num = 2,
 633                 .pin = 20,
 634                 .reg = 0xe8,
 635                 .bit = 0,
 636                 .mask = 0x7
 637         }, {
 638                 .num = 2,
 639                 .pin = 21,
 640                 .reg = 0xe8,
 641                 .bit = 4,
 642                 .mask = 0x7
 643         }, {
 644                 .num = 2,
 645                 .pin = 22,
 646                 .reg = 0xe8,
 647                 .bit = 8,
 648                 .mask = 0x7
 649         }, {
 650                 .num = 2,
 651                 .pin = 23,
 652                 .reg = 0xe8,
 653                 .bit = 12,
 654                 .mask = 0x7
 655         }, {
 656                 .num = 2,
 657                 .pin = 24,
 658                 .reg = 0xd4,
 659                 .bit = 12,
 660                 .mask = 0x7
 661         },
 662 };
 663
 664 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 665         {
 666                 /* gpio1b6_sel */
 667                 .num = 1,
 668                 .pin = 14,
 669                 .reg = 0x28,
 670                 .bit = 12,
 671                 .mask = 0xf
 672         }, {
 673                 /* gpio1b7_sel */
 674                 .num = 1,
 675                 .pin = 15,
 676                 .reg = 0x2c,
 677                 .bit = 0,
 678                 .mask = 0x3
 679         }, {
 680                 /* gpio1c2_sel */
 681                 .num = 1,
 682                 .pin = 18,
 683                 .reg = 0x30,
 684                 .bit = 4,
 685                 .mask = 0xf
 686         }, {
 687                 /* gpio1c3_sel */
 688                 .num = 1,
 689                 .pin = 19,
 690                 .reg = 0x30,
 691                 .bit = 8,
 692                 .mask = 0xf
 693         }, {
 694                 /* gpio1c4_sel */
 695                 .num = 1,
 696                 .pin = 20,
 697                 .reg = 0x30,
 698                 .bit = 12,
 699                 .mask = 0xf
 700         }, {
 701                 /* gpio1c5_sel */
 702                 .num = 1,
 703                 .pin = 21,
 704                 .reg = 0x34,
 705                 .bit = 0,
 706                 .mask = 0xf
 707         }, {
 708                 /* gpio1c6_sel */
 709                 .num = 1,
 710                 .pin = 22,
 711                 .reg = 0x34,
 712                 .bit = 4,
 713                 .mask = 0xf
 714         }, {
 715                 /* gpio1c7_sel */
 716                 .num = 1,
 717                 .pin = 23,
 718                 .reg = 0x34,
 719                 .bit = 8,
 720                 .mask = 0xf
 721         }, {
 722                 /* gpio3b4_sel */
 723                 .num = 3,
 724                 .pin = 12,
 725                 .reg = 0x68,
 726                 .bit = 8,
 727                 .mask = 0xf
 728         }, {
 729                 /* gpio3b5_sel */
 730                 .num = 3,
 731                 .pin = 13,
 732                 .reg = 0x68,
 733                 .bit = 12,
 734                 .mask = 0xf
 735         }, {
 736                 /* gpio2a2_sel */
 737                 .num = 2,
 738                 .pin = 2,
 739                 .reg = 0x40,
 740                 .bit = 4,
 741                 .mask = 0x3
 742         }, {
 743                 /* gpio2a3_sel */
 744                 .num = 2,
 745                 .pin = 3,
 746                 .reg = 0x40,
 747                 .bit = 6,
 748                 .mask = 0x3
 749         }, {
 750                 /* gpio2c0_sel */
 751                 .num = 2,
 752                 .pin = 16,
 753                 .reg = 0x50,
 754                 .bit = 0,
 755                 .mask = 0x3
 756         }, {
 757                 /* gpio3b2_sel */
 758                 .num = 3,
 759                 .pin = 10,
 760                 .reg = 0x68,
 761                 .bit = 4,
 762                 .mask = 0x3
 763         }, {
 764                 /* gpio3b3_sel */
 765                 .num = 3,
 766                 .pin = 11,
 767                 .reg = 0x68,
 768                 .bit = 6,
 769                 .mask = 0x3
 770         },
 771 };
 772
 773 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 774         {
 775                 .num = 2,
 776                 .pin = 12,
 777                 .reg = 0x24,
 778                 .bit = 8,
 779                 .mask = 0x3
 780         }, {
 781                 .num = 2,
 782                 .pin = 15,
 783                 .reg = 0x28,
 784                 .bit = 0,
 785                 .mask = 0x7
 786         }, {
 787                 .num = 2,
 788                 .pin = 23,
 789                 .reg = 0x30,
 790                 .bit = 14,
 791                 .mask = 0x3
 792         },
 793 };
 794
 795 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 796                                       int *reg, u8 *bit, int *mask)
 797 {
 798         struct rockchip_pinctrl *info = bank->drvdata;
 799         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 800         struct rockchip_mux_recalced_data *data;
 801         int i;
 802
 803         for (i = 0; i < ctrl->niomux_recalced; i++) {
 804                 data = &ctrl->iomux_recalced[i];
 805                 if (data->num == bank->bank_num &&
 806                     data->pin == pin)
 807                         break;
 808         }
 809
 810         if (i >= ctrl->niomux_recalced)
 811                 return;
 812
 813         *reg = data->reg;
 814         *mask = data->mask;
 815         *bit = data->bit;
 816 }
 817
 818 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 819         {
 820                 /* cif-d2m0 */
 821                 .bank_num = 2,
 822                 .pin = 0,
 823                 .func = 1,
 824                 .route_offset = 0x184,
 825                 .route_val = BIT(16 + 7),
 826         }, {
 827                 /* cif-d2m1 */
 828                 .bank_num = 3,
 829                 .pin = 3,
 830                 .func = 3,
 831                 .route_offset = 0x184,
 832                 .route_val = BIT(16 + 7) | BIT(7),
 833         }, {
 834                 /* pdm-m0 */
 835                 .bank_num = 3,
 836                 .pin = 22,
 837                 .func = 2,
 838                 .route_offset = 0x184,
 839                 .route_val = BIT(16 + 8),
 840         }, {
 841                 /* pdm-m1 */
 842                 .bank_num = 2,
 843                 .pin = 22,
 844                 .func = 1,
 845                 .route_offset = 0x184,
 846                 .route_val = BIT(16 + 8) | BIT(8),
 847         }, {
 848                 /* uart2-rxm0 */
 849                 .bank_num = 1,
 850                 .pin = 27,
 851                 .func = 2,
 852                 .route_offset = 0x184,
 853                 .route_val = BIT(16 + 10),
 854         }, {
 855                 /* uart2-rxm1 */
 856                 .bank_num = 2,
 857                 .pin = 14,
 858                 .func = 2,
 859                 .route_offset = 0x184,
 860                 .route_val = BIT(16 + 10) | BIT(10),
 861         }, {
 862                 /* uart3-rxm0 */
 863                 .bank_num = 0,
 864                 .pin = 17,
 865                 .func = 2,
 866                 .route_offset = 0x184,
 867                 .route_val = BIT(16 + 9),
 868         }, {
 869                 /* uart3-rxm1 */
 870                 .bank_num = 1,
 871                 .pin = 15,
 872                 .func = 2,
 873                 .route_offset = 0x184,
 874                 .route_val = BIT(16 + 9) | BIT(9),
 875         },
 876 };
 877
 878 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 879         {
 880                 /* spi-0 */
 881                 .bank_num = 1,
 882                 .pin = 10,
 883                 .func = 1,
 884                 .route_offset = 0x144,
 885                 .route_val = BIT(16 + 3) | BIT(16 + 4),
 886         }, {
 887                 /* spi-1 */
 888                 .bank_num = 1,
 889                 .pin = 27,
 890                 .func = 3,
 891                 .route_offset = 0x144,
 892                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
 893         }, {
 894                 /* spi-2 */
 895                 .bank_num = 0,
 896                 .pin = 13,
 897                 .func = 2,
 898                 .route_offset = 0x144,
 899                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
 900         }, {
 901                 /* i2s-0 */
 902                 .bank_num = 1,
 903                 .pin = 5,
 904                 .func = 1,
 905                 .route_offset = 0x144,
 906                 .route_val = BIT(16 + 5),
 907         }, {
 908                 /* i2s-1 */
 909                 .bank_num = 0,
 910                 .pin = 14,
 911                 .func = 1,
 912                 .route_offset = 0x144,
 913                 .route_val = BIT(16 + 5) | BIT(5),
 914         }, {
 915                 /* emmc-0 */
 916                 .bank_num = 1,
 917                 .pin = 22,
 918                 .func = 2,
 919                 .route_offset = 0x144,
 920                 .route_val = BIT(16 + 6),
 921         }, {
 922                 /* emmc-1 */
 923                 .bank_num = 2,
 924                 .pin = 4,
 925                 .func = 2,
 926                 .route_offset = 0x144,
 927                 .route_val = BIT(16 + 6) | BIT(6),
 928         },
 929 };
 930
 931 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 932         {
 933                 /* non-iomuxed emmc/flash pins on flash-dqs */
 934                 .bank_num = 0,
 935                 .pin = 24,
 936                 .func = 1,
 937                 .route_location = ROCKCHIP_ROUTE_GRF,
 938                 .route_offset = 0xa0,
 939                 .route_val = BIT(16 + 11),
 940         }, {
 941                 /* non-iomuxed emmc/flash pins on emmc-clk */
 942                 .bank_num = 0,
 943                 .pin = 24,
 944                 .func = 2,
 945                 .route_location = ROCKCHIP_ROUTE_GRF,
 946                 .route_offset = 0xa0,
 947                 .route_val = BIT(16 + 11) | BIT(11),
 948         },
 949 };
 950
 951 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 952         {
 953                 /* pwm0-0 */
 954                 .bank_num = 0,
 955                 .pin = 26,
 956                 .func = 1,
 957                 .route_offset = 0x50,
 958                 .route_val = BIT(16),
 959         }, {
 960                 /* pwm0-1 */
 961                 .bank_num = 3,
 962                 .pin = 21,
 963                 .func = 1,
 964                 .route_offset = 0x50,
 965                 .route_val = BIT(16) | BIT(0),
 966         }, {
 967                 /* pwm1-0 */
 968                 .bank_num = 0,
 969                 .pin = 27,
 970                 .func = 1,
 971                 .route_offset = 0x50,
 972                 .route_val = BIT(16 + 1),
 973         }, {
 974                 /* pwm1-1 */
 975                 .bank_num = 0,
 976                 .pin = 30,
 977                 .func = 2,
 978                 .route_offset = 0x50,
 979                 .route_val = BIT(16 + 1) | BIT(1),
 980         }, {
 981                 /* pwm2-0 */
 982                 .bank_num = 0,
 983                 .pin = 28,
 984                 .func = 1,
 985                 .route_offset = 0x50,
 986                 .route_val = BIT(16 + 2),
 987         }, {
 988                 /* pwm2-1 */
 989                 .bank_num = 1,
 990                 .pin = 12,
 991                 .func = 2,
 992                 .route_offset = 0x50,
 993                 .route_val = BIT(16 + 2) | BIT(2),
 994         }, {
 995                 /* pwm3-0 */
 996                 .bank_num = 3,
 997                 .pin = 26,
 998                 .func = 1,
 999                 .route_offset = 0x50,
1000                 .route_val = BIT(16 + 3),
1001         }, {
1002                 /* pwm3-1 */
1003                 .bank_num = 1,
1004                 .pin = 11,
1005                 .func = 2,
1006                 .route_offset = 0x50,
1007                 .route_val = BIT(16 + 3) | BIT(3),
1008         }, {
1009                 /* sdio-0_d0 */
1010                 .bank_num = 1,
1011                 .pin = 1,
1012                 .func = 1,
1013                 .route_offset = 0x50,
1014                 .route_val = BIT(16 + 4),
1015         }, {
1016                 /* sdio-1_d0 */
1017                 .bank_num = 3,
1018                 .pin = 2,
1019                 .func = 1,
1020                 .route_offset = 0x50,
1021                 .route_val = BIT(16 + 4) | BIT(4),
1022         }, {
1023                 /* spi-0_rx */
1024                 .bank_num = 0,
1025                 .pin = 13,
1026                 .func = 2,
1027                 .route_offset = 0x50,
1028                 .route_val = BIT(16 + 5),
1029         }, {
1030                 /* spi-1_rx */
1031                 .bank_num = 2,
1032                 .pin = 0,
1033                 .func = 2,
1034                 .route_offset = 0x50,
1035                 .route_val = BIT(16 + 5) | BIT(5),
1036         }, {
1037                 /* emmc-0_cmd */
1038                 .bank_num = 1,
1039                 .pin = 22,
1040                 .func = 2,
1041                 .route_offset = 0x50,
1042                 .route_val = BIT(16 + 7),
1043         }, {
1044                 /* emmc-1_cmd */
1045                 .bank_num = 2,
1046                 .pin = 4,
1047                 .func = 2,
1048                 .route_offset = 0x50,
1049                 .route_val = BIT(16 + 7) | BIT(7),
1050         }, {
1051                 /* uart2-0_rx */
1052                 .bank_num = 1,
1053                 .pin = 19,
1054                 .func = 2,
1055                 .route_offset = 0x50,
1056                 .route_val = BIT(16 + 8),
1057         }, {
1058                 /* uart2-1_rx */
1059                 .bank_num = 1,
1060                 .pin = 10,
1061                 .func = 2,
1062                 .route_offset = 0x50,
1063                 .route_val = BIT(16 + 8) | BIT(8),
1064         }, {
1065                 /* uart1-0_rx */
1066                 .bank_num = 1,
1067                 .pin = 10,
1068                 .func = 1,
1069                 .route_offset = 0x50,
1070                 .route_val = BIT(16 + 11),
1071         }, {
1072                 /* uart1-1_rx */
1073                 .bank_num = 3,
1074                 .pin = 13,
1075                 .func = 1,
1076                 .route_offset = 0x50,
1077                 .route_val = BIT(16 + 11) | BIT(11),
1078         },
1079 };
1080
1081 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
1082         {
1083                 /* edphdmi_cecinoutt1 */
1084                 .bank_num = 7,
1085                 .pin = 16,
1086                 .func = 2,
1087                 .route_offset = 0x264,
1088                 .route_val = BIT(16 + 12) | BIT(12),
1089         }, {
1090                 /* edphdmi_cecinout */
1091                 .bank_num = 7,
1092                 .pin = 23,
1093                 .func = 4,
1094                 .route_offset = 0x264,
1095                 .route_val = BIT(16 + 12),
1096         },
1097 };
1098
1099 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1100         {
1101                 /* rtc_clk */
1102                 .bank_num = 0,
1103                 .pin = 19,
1104                 .func = 1,
1105                 .route_offset = 0x314,
1106                 .route_val = BIT(16 + 0) | BIT(0),
1107         }, {
1108                 /* uart2_rxm0 */
1109                 .bank_num = 1,
1110                 .pin = 22,
1111                 .func = 2,
1112                 .route_offset = 0x314,
1113                 .route_val = BIT(16 + 2) | BIT(16 + 3),
1114         }, {
1115                 /* uart2_rxm1 */
1116                 .bank_num = 4,
1117                 .pin = 26,
1118                 .func = 2,
1119                 .route_offset = 0x314,
1120                 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1121         }, {
1122                 /* i2c3_sdam0 */
1123                 .bank_num = 0,
1124                 .pin = 15,
1125                 .func = 2,
1126                 .route_offset = 0x608,
1127                 .route_val = BIT(16 + 8) | BIT(16 + 9),
1128         }, {
1129                 /* i2c3_sdam1 */
1130                 .bank_num = 3,
1131                 .pin = 12,
1132                 .func = 2,
1133                 .route_offset = 0x608,
1134                 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
1135         }, {
1136                 /* i2c3_sdam2 */
1137                 .bank_num = 2,
1138                 .pin = 0,
1139                 .func = 3,
1140                 .route_offset = 0x608,
1141                 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
1142         }, {
1143                 /* i2s-8ch-1-sclktxm0 */
1144                 .bank_num = 1,
1145                 .pin = 3,
1146                 .func = 2,
1147                 .route_offset = 0x308,
1148                 .route_val = BIT(16 + 3),
1149         }, {
1150                 /* i2s-8ch-1-sclkrxm0 */
1151                 .bank_num = 1,
1152                 .pin = 4,
1153                 .func = 2,
1154                 .route_offset = 0x308,
1155                 .route_val = BIT(16 + 3),
1156         }, {
1157                 /* i2s-8ch-1-sclktxm1 */
1158                 .bank_num = 1,
1159                 .pin = 13,
1160                 .func = 2,
1161                 .route_offset = 0x308,
1162                 .route_val = BIT(16 + 3) | BIT(3),
1163         }, {
1164                 /* i2s-8ch-1-sclkrxm1 */
1165                 .bank_num = 1,
1166                 .pin = 14,
1167                 .func = 2,
1168                 .route_offset = 0x308,
1169                 .route_val = BIT(16 + 3) | BIT(3),
1170         }, {
1171                 /* pdm-clkm0 */
1172                 .bank_num = 1,
1173                 .pin = 4,
1174                 .func = 3,
1175                 .route_offset = 0x308,
1176                 .route_val =  BIT(16 + 12) | BIT(16 + 13),
1177         }, {
1178                 /* pdm-clkm1 */
1179                 .bank_num = 1,
1180                 .pin = 14,
1181                 .func = 4,
1182                 .route_offset = 0x308,
1183                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1184         }, {
1185                 /* pdm-clkm2 */
1186                 .bank_num = 2,
1187                 .pin = 6,
1188                 .func = 2,
1189                 .route_offset = 0x308,
1190                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1191         }, {
1192                 /* pdm-clkm-m2 */
1193                 .bank_num = 2,
1194                 .pin = 4,
1195                 .func = 3,
1196                 .route_offset = 0x600,
1197                 .route_val = BIT(16 + 2) | BIT(2),
1198         }, {
1199                 /* spi1_miso */
1200                 .bank_num = 3,
1201                 .pin = 10,
1202                 .func = 3,
1203                 .route_offset = 0x314,
1204                 .route_val = BIT(16 + 9),
1205         }, {
1206                 /* spi1_miso_m1 */
1207                 .bank_num = 2,
1208                 .pin = 4,
1209                 .func = 2,
1210                 .route_offset = 0x314,
1211                 .route_val = BIT(16 + 9) | BIT(9),
1212         }, {
1213                 /* owire_m0 */
1214                 .bank_num = 0,
1215                 .pin = 11,
1216                 .func = 3,
1217                 .route_offset = 0x314,
1218                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1219         }, {
1220                 /* owire_m1 */
1221                 .bank_num = 1,
1222                 .pin = 22,
1223                 .func = 7,
1224                 .route_offset = 0x314,
1225                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1226         }, {
1227                 /* owire_m2 */
1228                 .bank_num = 2,
1229                 .pin = 2,
1230                 .func = 5,
1231                 .route_offset = 0x314,
1232                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1233         }, {
1234                 /* can_rxd_m0 */
1235                 .bank_num = 0,
1236                 .pin = 11,
1237                 .func = 2,
1238                 .route_offset = 0x314,
1239                 .route_val = BIT(16 + 12) | BIT(16 + 13),
1240         }, {
1241                 /* can_rxd_m1 */
1242                 .bank_num = 1,
1243                 .pin = 22,
1244                 .func = 5,
1245                 .route_offset = 0x314,
1246                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1247         }, {
1248                 /* can_rxd_m2 */
1249                 .bank_num = 2,
1250                 .pin = 2,
1251                 .func = 4,
1252                 .route_offset = 0x314,
1253                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1254         }, {
1255                 /* mac_rxd0_m0 */
1256                 .bank_num = 1,
1257                 .pin = 20,
1258                 .func = 3,
1259                 .route_offset = 0x314,
1260                 .route_val = BIT(16 + 14),
1261         }, {
1262                 /* mac_rxd0_m1 */
1263                 .bank_num = 4,
1264                 .pin = 2,
1265                 .func = 2,
1266                 .route_offset = 0x314,
1267                 .route_val = BIT(16 + 14) | BIT(14),
1268         }, {
1269                 /* uart3_rx */
1270                 .bank_num = 3,
1271                 .pin = 12,
1272                 .func = 4,
1273                 .route_offset = 0x314,
1274                 .route_val = BIT(16 + 15),
1275         }, {
1276                 /* uart3_rx_m1 */
1277                 .bank_num = 0,
1278                 .pin = 17,
1279                 .func = 3,
1280                 .route_offset = 0x314,
1281                 .route_val = BIT(16 + 15) | BIT(15),
1282         },
1283 };
1284
1285 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1286         {
1287                 /* uart2dbg_rxm0 */
1288                 .bank_num = 1,
1289                 .pin = 1,
1290                 .func = 2,
1291                 .route_offset = 0x50,
1292                 .route_val = BIT(16) | BIT(16 + 1),
1293         }, {
1294                 /* uart2dbg_rxm1 */
1295                 .bank_num = 2,
1296                 .pin = 1,
1297                 .func = 1,
1298                 .route_offset = 0x50,
1299                 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1300         }, {
1301                 /* gmac-m1_rxd0 */
1302                 .bank_num = 1,
1303                 .pin = 11,
1304                 .func = 2,
1305                 .route_offset = 0x50,
1306                 .route_val = BIT(16 + 2) | BIT(2),
1307         }, {
1308                 /* gmac-m1-optimized_rxd3 */
1309                 .bank_num = 1,
1310                 .pin = 14,
1311                 .func = 2,
1312                 .route_offset = 0x50,
1313                 .route_val = BIT(16 + 10) | BIT(10),
1314         }, {
1315                 /* pdm_sdi0m0 */
1316                 .bank_num = 2,
1317                 .pin = 19,
1318                 .func = 2,
1319                 .route_offset = 0x50,
1320                 .route_val = BIT(16 + 3),
1321         }, {
1322                 /* pdm_sdi0m1 */
1323                 .bank_num = 1,
1324                 .pin = 23,
1325                 .func = 3,
1326                 .route_offset = 0x50,
1327                 .route_val =  BIT(16 + 3) | BIT(3),
1328         }, {
1329                 /* spi_rxdm2 */
1330                 .bank_num = 3,
1331                 .pin = 2,
1332                 .func = 4,
1333                 .route_offset = 0x50,
1334                 .route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1335         }, {
1336                 /* i2s2_sdim0 */
1337                 .bank_num = 1,
1338                 .pin = 24,
1339                 .func = 1,
1340                 .route_offset = 0x50,
1341                 .route_val = BIT(16 + 6),
1342         }, {
1343                 /* i2s2_sdim1 */
1344                 .bank_num = 3,
1345                 .pin = 2,
1346                 .func = 6,
1347                 .route_offset = 0x50,
1348                 .route_val =  BIT(16 + 6) | BIT(6),
1349         }, {
1350                 /* card_iom1 */
1351                 .bank_num = 2,
1352                 .pin = 22,
1353                 .func = 3,
1354                 .route_offset = 0x50,
1355                 .route_val =  BIT(16 + 7) | BIT(7),
1356         }, {
1357                 /* tsp_d5m1 */
1358                 .bank_num = 2,
1359                 .pin = 16,
1360                 .func = 3,
1361                 .route_offset = 0x50,
1362                 .route_val =  BIT(16 + 8) | BIT(8),
1363         }, {
1364                 /* cif_data5m1 */
1365                 .bank_num = 2,
1366                 .pin = 16,
1367                 .func = 4,
1368                 .route_offset = 0x50,
1369                 .route_val =  BIT(16 + 9) | BIT(9),
1370         },
1371 };
1372
1373 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1374         {
1375                 /* uart2dbga_rx */
1376                 .bank_num = 4,
1377                 .pin = 8,
1378                 .func = 2,
1379                 .route_offset = 0xe21c,
1380                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1381         }, {
1382                 /* uart2dbgb_rx */
1383                 .bank_num = 4,
1384                 .pin = 16,
1385                 .func = 2,
1386                 .route_offset = 0xe21c,
1387                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1388         }, {
1389                 /* uart2dbgc_rx */
1390                 .bank_num = 4,
1391                 .pin = 19,
1392                 .func = 1,
1393                 .route_offset = 0xe21c,
1394                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1395         }, {
1396                 /* pcie_clkreqn */
1397                 .bank_num = 2,
1398                 .pin = 26,
1399                 .func = 2,
1400                 .route_offset = 0xe21c,
1401                 .route_val = BIT(16 + 14),
1402         }, {
1403                 /* pcie_clkreqnb */
1404                 .bank_num = 4,
1405                 .pin = 24,
1406                 .func = 1,
1407                 .route_offset = 0xe21c,
1408                 .route_val = BIT(16 + 14) | BIT(14),
1409         },
1410 };
1411
1412 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1413                                    int mux, u32 *loc, u32 *reg, u32 *value)
1414 {
1415         struct rockchip_pinctrl *info = bank->drvdata;
1416         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1417         struct rockchip_mux_route_data *data;
1418         int i;
1419
1420         for (i = 0; i < ctrl->niomux_routes; i++) {
1421                 data = &ctrl->iomux_routes[i];
1422                 if ((data->bank_num == bank->bank_num) &&
1423                     (data->pin == pin) && (data->func == mux))
1424                         break;
1425         }
1426
1427         if (i >= ctrl->niomux_routes)
1428                 return false;
1429
1430         *loc = data->route_location;
1431         *reg = data->route_offset;
1432         *value = data->route_val;
1433
1434         return true;
1435 }
1436
1437 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1438 {
1439         struct rockchip_pinctrl *info = bank->drvdata;
1440         int iomux_num = (pin / 8);
1441         struct regmap *regmap;
1442         unsigned int val;
1443         int reg, ret, mask, mux_type;
1444         u8 bit;
1445
1446         if (iomux_num > 3)
1447                 return -EINVAL;
1448
1449         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1450                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1451                 return -EINVAL;
1452         }
1453
1454         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1455                 return RK_FUNC_GPIO;
1456
1457         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1458                                 ? info->regmap_pmu : info->regmap_base;
1459
1460         /* get basic quadrupel of mux registers and the correct reg inside */
1461         mux_type = bank->iomux[iomux_num].type;
1462         reg = bank->iomux[iomux_num].offset;
1463         if (mux_type & IOMUX_WIDTH_4BIT) {
1464                 if ((pin % 8) >= 4)
1465                         reg += 0x4;
1466                 bit = (pin % 4) * 4;
1467                 mask = 0xf;
1468         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1469                 if ((pin % 8) >= 5)
1470                         reg += 0x4;
1471                 bit = (pin % 8 % 5) * 3;
1472                 mask = 0x7;
1473         } else {
1474                 bit = (pin % 8) * 2;
1475                 mask = 0x3;
1476         }
1477
1478         if (bank->recalced_mask & BIT(pin))
1479                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1480
1481         ret = regmap_read(regmap, reg, &val);
1482         if (ret)
1483                 return ret;
1484
1485         return ((val >> bit) & mask);
1486 }
1487
1488 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1489                                int pin, int mux)
1490 {
1491         struct rockchip_pinctrl *info = bank->drvdata;
1492         int iomux_num = (pin / 8);
1493
1494         if (iomux_num > 3)
1495                 return -EINVAL;
1496
1497         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1498                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1499                 return -EINVAL;
1500         }
1501
1502         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1503                 if (mux != RK_FUNC_GPIO) {
1504                         dev_err(info->dev,
1505                                 "pin %d only supports a gpio mux\n", pin);
1506                         return -ENOTSUPP;
1507                 }
1508         }
1509
1510         return 0;
1511 }
1512
1513 /*
1514  * Set a new mux function for a pin.
1515  *
1516  * The register is divided into the upper and lower 16 bit. When changing
1517  * a value, the previous register value is not read and changed. Instead
1518  * it seems the changed bits are marked in the upper 16 bit, while the
1519  * changed value gets set in the same offset in the lower 16 bit.
1520  * All pin settings seem to be 2 bit wide in both the upper and lower
1521  * parts.
1522  * @bank: pin bank to change
1523  * @pin: pin to change
1524  * @mux: new mux function to set
1525  */
1526 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1527 {
1528         struct rockchip_pinctrl *info = bank->drvdata;
1529         int iomux_num = (pin / 8);
1530         struct regmap *regmap;
1531         int reg, ret, mask, mux_type;
1532         u8 bit;
1533         u32 data, rmask, route_location, route_reg, route_val;
1534
1535         ret = rockchip_verify_mux(bank, pin, mux);
1536         if (ret < 0)
1537                 return ret;
1538
1539         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1540                 return 0;
1541
1542         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1543                                                 bank->bank_num, pin, mux);
1544
1545         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1546                                 ? info->regmap_pmu : info->regmap_base;
1547
1548         /* get basic quadrupel of mux registers and the correct reg inside */
1549         mux_type = bank->iomux[iomux_num].type;
1550         reg = bank->iomux[iomux_num].offset;
1551         if (mux_type & IOMUX_WIDTH_4BIT) {
1552                 if ((pin % 8) >= 4)
1553                         reg += 0x4;
1554                 bit = (pin % 4) * 4;
1555                 mask = 0xf;
1556         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1557                 if ((pin % 8) >= 5)
1558                         reg += 0x4;
1559                 bit = (pin % 8 % 5) * 3;
1560                 mask = 0x7;
1561         } else {
1562                 bit = (pin % 8) * 2;
1563                 mask = 0x3;
1564         }
1565
1566         if (bank->recalced_mask & BIT(pin))
1567                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1568
1569         if (bank->route_mask & BIT(pin)) {
1570                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1571                                            &route_reg, &route_val)) {
1572                         struct regmap *route_regmap = regmap;
1573
1574                         /* handle special locations */
1575                         switch (route_location) {
1576                         case ROCKCHIP_ROUTE_PMU:
1577                                 route_regmap = info->regmap_pmu;
1578                                 break;
1579                         case ROCKCHIP_ROUTE_GRF:
1580                                 route_regmap = info->regmap_base;
1581                                 break;
1582                         }
1583
1584                         ret = regmap_write(route_regmap, route_reg, route_val);
1585                         if (ret)
1586                                 return ret;
1587                 }
1588         }
1589
1590         data = (mask << (bit + 16));
1591         rmask = data | (data >> 16);
1592         data |= (mux & mask) << bit;
1593         ret = regmap_update_bits(regmap, reg, rmask, data);
1594
1595         return ret;
1596 }
1597
1598 #define PX30_PULL_PMU_OFFSET            0x10
1599 #define PX30_PULL_GRF_OFFSET            0x60
1600 #define PX30_PULL_BITS_PER_PIN          2
1601 #define PX30_PULL_PINS_PER_REG          8
1602 #define PX30_PULL_BANK_STRIDE           16
1603
1604 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1605                                        int pin_num, struct regmap **regmap,
1606                                        int *reg, u8 *bit)
1607 {
1608         struct rockchip_pinctrl *info = bank->drvdata;
1609
1610         /* The first 32 pins of the first bank are located in PMU */
1611         if (bank->bank_num == 0) {
1612                 *regmap = info->regmap_pmu;
1613                 *reg = PX30_PULL_PMU_OFFSET;
1614         } else {
1615                 *regmap = info->regmap_base;
1616                 *reg = PX30_PULL_GRF_OFFSET;
1617
1618                 /* correct the offset, as we're starting with the 2nd bank */
1619                 *reg -= 0x10;
1620                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1621         }
1622
1623         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1624         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1625         *bit *= PX30_PULL_BITS_PER_PIN;
1626 }
1627
1628 #define PX30_DRV_PMU_OFFSET             0x20
1629 #define PX30_DRV_GRF_OFFSET             0xf0
1630 #define PX30_DRV_BITS_PER_PIN           2
1631 #define PX30_DRV_PINS_PER_REG           8
1632 #define PX30_DRV_BANK_STRIDE            16
1633
1634 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1635                                       int pin_num, struct regmap **regmap,
1636                                       int *reg, u8 *bit)
1637 {
1638         struct rockchip_pinctrl *info = bank->drvdata;
1639
1640         /* The first 32 pins of the first bank are located in PMU */
1641         if (bank->bank_num == 0) {
1642                 *regmap = info->regmap_pmu;
1643                 *reg = PX30_DRV_PMU_OFFSET;
1644         } else {
1645                 *regmap = info->regmap_base;
1646                 *reg = PX30_DRV_GRF_OFFSET;
1647
1648                 /* correct the offset, as we're starting with the 2nd bank */
1649                 *reg -= 0x10;
1650                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1651         }
1652
1653         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1654         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1655         *bit *= PX30_DRV_BITS_PER_PIN;
1656 }
1657
1658 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1659 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1660 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1661 #define PX30_SCHMITT_BANK_STRIDE                16
1662 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1663
1664 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1665                                          int pin_num,
1666                                          struct regmap **regmap,
1667                                          int *reg, u8 *bit)
1668 {
1669         struct rockchip_pinctrl *info = bank->drvdata;
1670         int pins_per_reg;
1671
1672         if (bank->bank_num == 0) {
1673                 *regmap = info->regmap_pmu;
1674                 *reg = PX30_SCHMITT_PMU_OFFSET;
1675                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1676         } else {
1677                 *regmap = info->regmap_base;
1678                 *reg = PX30_SCHMITT_GRF_OFFSET;
1679                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1680                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1681         }
1682
1683         *reg += ((pin_num / pins_per_reg) * 4);
1684         *bit = pin_num % pins_per_reg;
1685
1686         return 0;
1687 }
1688
1689 #define RV1108_PULL_PMU_OFFSET          0x10
1690 #define RV1108_PULL_OFFSET              0x110
1691 #define RV1108_PULL_PINS_PER_REG        8
1692 #define RV1108_PULL_BITS_PER_PIN        2
1693 #define RV1108_PULL_BANK_STRIDE         16
1694
1695 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1696                                          int pin_num, struct regmap **regmap,
1697                                          int *reg, u8 *bit)
1698 {
1699         struct rockchip_pinctrl *info = bank->drvdata;
1700
1701         /* The first 24 pins of the first bank are located in PMU */
1702         if (bank->bank_num == 0) {
1703                 *regmap = info->regmap_pmu;
1704                 *reg = RV1108_PULL_PMU_OFFSET;
1705         } else {
1706                 *reg = RV1108_PULL_OFFSET;
1707                 *regmap = info->regmap_base;
1708                 /* correct the offset, as we're starting with the 2nd bank */
1709                 *reg -= 0x10;
1710                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1711         }
1712
1713         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1714         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1715         *bit *= RV1108_PULL_BITS_PER_PIN;
1716 }
1717
1718 #define RV1108_DRV_PMU_OFFSET           0x20
1719 #define RV1108_DRV_GRF_OFFSET           0x210
1720 #define RV1108_DRV_BITS_PER_PIN         2
1721 #define RV1108_DRV_PINS_PER_REG         8
1722 #define RV1108_DRV_BANK_STRIDE          16
1723
1724 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1725                                         int pin_num, struct regmap **regmap,
1726                                         int *reg, u8 *bit)
1727 {
1728         struct rockchip_pinctrl *info = bank->drvdata;
1729
1730         /* The first 24 pins of the first bank are located in PMU */
1731         if (bank->bank_num == 0) {
1732                 *regmap = info->regmap_pmu;
1733                 *reg = RV1108_DRV_PMU_OFFSET;
1734         } else {
1735                 *regmap = info->regmap_base;
1736                 *reg = RV1108_DRV_GRF_OFFSET;
1737
1738                 /* correct the offset, as we're starting with the 2nd bank */
1739                 *reg -= 0x10;
1740                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1741         }
1742
1743         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1744         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1745         *bit *= RV1108_DRV_BITS_PER_PIN;
1746 }
1747
1748 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1749 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1750 #define RV1108_SCHMITT_BANK_STRIDE              8
1751 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1752 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1753
1754 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1755                                            int pin_num,
1756                                            struct regmap **regmap,
1757                                            int *reg, u8 *bit)
1758 {
1759         struct rockchip_pinctrl *info = bank->drvdata;
1760         int pins_per_reg;
1761
1762         if (bank->bank_num == 0) {
1763                 *regmap = info->regmap_pmu;
1764                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1765                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1766         } else {
1767                 *regmap = info->regmap_base;
1768                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1769                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1770                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1771         }
1772         *reg += ((pin_num / pins_per_reg) * 4);
1773         *bit = pin_num % pins_per_reg;
1774
1775         return 0;
1776 }
1777
1778 #define RK3308_SCHMITT_PINS_PER_REG             8
1779 #define RK3308_SCHMITT_BANK_STRIDE              16
1780 #define RK3308_SCHMITT_GRF_OFFSET               0x1a0
1781
1782 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1783                                     int pin_num, struct regmap **regmap,
1784                                     int *reg, u8 *bit)
1785 {
1786         struct rockchip_pinctrl *info = bank->drvdata;
1787
1788         *regmap = info->regmap_base;
1789         *reg = RK3308_SCHMITT_GRF_OFFSET;
1790
1791         *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1792         *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1793         *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1794
1795         return 0;
1796 }
1797
1798 #define RK2928_PULL_OFFSET              0x118
1799 #define RK2928_PULL_PINS_PER_REG        16
1800 #define RK2928_PULL_BANK_STRIDE         8
1801
1802 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1803                                     int pin_num, struct regmap **regmap,
1804                                     int *reg, u8 *bit)
1805 {
1806         struct rockchip_pinctrl *info = bank->drvdata;
1807
1808         *regmap = info->regmap_base;
1809         *reg = RK2928_PULL_OFFSET;
1810         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1811         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1812
1813         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1814 };
1815
1816 #define RK3128_PULL_OFFSET      0x118
1817
1818 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1819                                          int pin_num, struct regmap **regmap,
1820                                          int *reg, u8 *bit)
1821 {
1822         struct rockchip_pinctrl *info = bank->drvdata;
1823
1824         *regmap = info->regmap_base;
1825         *reg = RK3128_PULL_OFFSET;
1826         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1827         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1828
1829         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1830 }
1831
1832 #define RK3188_PULL_OFFSET              0x164
1833 #define RK3188_PULL_BITS_PER_PIN        2
1834 #define RK3188_PULL_PINS_PER_REG        8
1835 #define RK3188_PULL_BANK_STRIDE         16
1836 #define RK3188_PULL_PMU_OFFSET          0x64
1837
1838 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1839                                     int pin_num, struct regmap **regmap,
1840                                     int *reg, u8 *bit)
1841 {
1842         struct rockchip_pinctrl *info = bank->drvdata;
1843
1844         /* The first 12 pins of the first bank are located elsewhere */
1845         if (bank->bank_num == 0 && pin_num < 12) {
1846                 *regmap = info->regmap_pmu ? info->regmap_pmu
1847                                            : bank->regmap_pull;
1848                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1849                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1850                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1851                 *bit *= RK3188_PULL_BITS_PER_PIN;
1852         } else {
1853                 *regmap = info->regmap_pull ? info->regmap_pull
1854                                             : info->regmap_base;
1855                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1856
1857                 /* correct the offset, as it is the 2nd pull register */
1858                 *reg -= 4;
1859                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1860                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1861
1862                 /*
1863                  * The bits in these registers have an inverse ordering
1864                  * with the lowest pin being in bits 15:14 and the highest
1865                  * pin in bits 1:0
1866                  */
1867                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1868                 *bit *= RK3188_PULL_BITS_PER_PIN;
1869         }
1870 }
1871
1872 #define RK3288_PULL_OFFSET              0x140
1873 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1874                                     int pin_num, struct regmap **regmap,
1875                                     int *reg, u8 *bit)
1876 {
1877         struct rockchip_pinctrl *info = bank->drvdata;
1878
1879         /* The first 24 pins of the first bank are located in PMU */
1880         if (bank->bank_num == 0) {
1881                 *regmap = info->regmap_pmu;
1882                 *reg = RK3188_PULL_PMU_OFFSET;
1883
1884                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1885                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1886                 *bit *= RK3188_PULL_BITS_PER_PIN;
1887         } else {
1888                 *regmap = info->regmap_base;
1889                 *reg = RK3288_PULL_OFFSET;
1890
1891                 /* correct the offset, as we're starting with the 2nd bank */
1892                 *reg -= 0x10;
1893                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1894                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1895
1896                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1897                 *bit *= RK3188_PULL_BITS_PER_PIN;
1898         }
1899 }
1900
1901 #define RK3288_DRV_PMU_OFFSET           0x70
1902 #define RK3288_DRV_GRF_OFFSET           0x1c0
1903 #define RK3288_DRV_BITS_PER_PIN         2
1904 #define RK3288_DRV_PINS_PER_REG         8
1905 #define RK3288_DRV_BANK_STRIDE          16
1906
1907 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1908                                     int pin_num, struct regmap **regmap,
1909                                     int *reg, u8 *bit)
1910 {
1911         struct rockchip_pinctrl *info = bank->drvdata;
1912
1913         /* The first 24 pins of the first bank are located in PMU */
1914         if (bank->bank_num == 0) {
1915                 *regmap = info->regmap_pmu;
1916                 *reg = RK3288_DRV_PMU_OFFSET;
1917
1918                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1919                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1920                 *bit *= RK3288_DRV_BITS_PER_PIN;
1921         } else {
1922                 *regmap = info->regmap_base;
1923                 *reg = RK3288_DRV_GRF_OFFSET;
1924
1925                 /* correct the offset, as we're starting with the 2nd bank */
1926                 *reg -= 0x10;
1927                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1928                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1929
1930                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1931                 *bit *= RK3288_DRV_BITS_PER_PIN;
1932         }
1933 }
1934
1935 #define RK3228_PULL_OFFSET              0x100
1936
1937 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1938                                     int pin_num, struct regmap **regmap,
1939                                     int *reg, u8 *bit)
1940 {
1941         struct rockchip_pinctrl *info = bank->drvdata;
1942
1943         *regmap = info->regmap_base;
1944         *reg = RK3228_PULL_OFFSET;
1945         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1946         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1947
1948         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1949         *bit *= RK3188_PULL_BITS_PER_PIN;
1950 }
1951
1952 #define RK3228_DRV_GRF_OFFSET           0x200
1953
1954 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1955                                     int pin_num, struct regmap **regmap,
1956                                     int *reg, u8 *bit)
1957 {
1958         struct rockchip_pinctrl *info = bank->drvdata;
1959
1960         *regmap = info->regmap_base;
1961         *reg = RK3228_DRV_GRF_OFFSET;
1962         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1963         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1964
1965         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1966         *bit *= RK3288_DRV_BITS_PER_PIN;
1967 }
1968
1969 #define RK3308_PULL_OFFSET              0xa0
1970
1971 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1972                                     int pin_num, struct regmap **regmap,
1973                                     int *reg, u8 *bit)
1974 {
1975         struct rockchip_pinctrl *info = bank->drvdata;
1976
1977         *regmap = info->regmap_base;
1978         *reg = RK3308_PULL_OFFSET;
1979         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1980         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1981
1982         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1983         *bit *= RK3188_PULL_BITS_PER_PIN;
1984 }
1985
1986 #define RK3308_DRV_GRF_OFFSET           0x100
1987
1988 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1989                                     int pin_num, struct regmap **regmap,
1990                                     int *reg, u8 *bit)
1991 {
1992         struct rockchip_pinctrl *info = bank->drvdata;
1993
1994         *regmap = info->regmap_base;
1995         *reg = RK3308_DRV_GRF_OFFSET;
1996         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1997         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1998
1999         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2000         *bit *= RK3288_DRV_BITS_PER_PIN;
2001 }
2002
2003 #define RK3368_PULL_GRF_OFFSET          0x100
2004 #define RK3368_PULL_PMU_OFFSET          0x10
2005
2006 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2007                                     int pin_num, struct regmap **regmap,
2008                                     int *reg, u8 *bit)
2009 {
2010         struct rockchip_pinctrl *info = bank->drvdata;
2011
2012         /* The first 32 pins of the first bank are located in PMU */
2013         if (bank->bank_num == 0) {
2014                 *regmap = info->regmap_pmu;
2015                 *reg = RK3368_PULL_PMU_OFFSET;
2016
2017                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2018                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2019                 *bit *= RK3188_PULL_BITS_PER_PIN;
2020         } else {
2021                 *regmap = info->regmap_base;
2022                 *reg = RK3368_PULL_GRF_OFFSET;
2023
2024                 /* correct the offset, as we're starting with the 2nd bank */
2025                 *reg -= 0x10;
2026                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2027                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2028
2029                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2030                 *bit *= RK3188_PULL_BITS_PER_PIN;
2031         }
2032 }
2033
2034 #define RK3368_DRV_PMU_OFFSET           0x20
2035 #define RK3368_DRV_GRF_OFFSET           0x200
2036
2037 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2038                                     int pin_num, struct regmap **regmap,
2039                                     int *reg, u8 *bit)
2040 {
2041         struct rockchip_pinctrl *info = bank->drvdata;
2042
2043         /* The first 32 pins of the first bank are located in PMU */
2044         if (bank->bank_num == 0) {
2045                 *regmap = info->regmap_pmu;
2046                 *reg = RK3368_DRV_PMU_OFFSET;
2047
2048                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2049                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2050                 *bit *= RK3288_DRV_BITS_PER_PIN;
2051         } else {
2052                 *regmap = info->regmap_base;
2053                 *reg = RK3368_DRV_GRF_OFFSET;
2054
2055                 /* correct the offset, as we're starting with the 2nd bank */
2056                 *reg -= 0x10;
2057                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2058                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2059
2060                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2061                 *bit *= RK3288_DRV_BITS_PER_PIN;
2062         }
2063 }
2064
2065 #define RK3399_PULL_GRF_OFFSET          0xe040
2066 #define RK3399_PULL_PMU_OFFSET          0x40
2067 #define RK3399_DRV_3BITS_PER_PIN        3
2068
2069 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2070                                          int pin_num, struct regmap **regmap,
2071                                          int *reg, u8 *bit)
2072 {
2073         struct rockchip_pinctrl *info = bank->drvdata;
2074
2075         /* The bank0:16 and bank1:32 pins are located in PMU */
2076         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2077                 *regmap = info->regmap_pmu;
2078                 *reg = RK3399_PULL_PMU_OFFSET;
2079
2080                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2081
2082                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2083                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2084                 *bit *= RK3188_PULL_BITS_PER_PIN;
2085         } else {
2086                 *regmap = info->regmap_base;
2087                 *reg = RK3399_PULL_GRF_OFFSET;
2088
2089                 /* correct the offset, as we're starting with the 3rd bank */
2090                 *reg -= 0x20;
2091                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2092                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2093
2094                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2095                 *bit *= RK3188_PULL_BITS_PER_PIN;
2096         }
2097 }
2098
2099 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2100                                         int pin_num, struct regmap **regmap,
2101                                         int *reg, u8 *bit)
2102 {
2103         struct rockchip_pinctrl *info = bank->drvdata;
2104         int drv_num = (pin_num / 8);
2105
2106         /*  The bank0:16 and bank1:32 pins are located in PMU */
2107         if ((bank->bank_num == 0) || (bank->bank_num == 1))
2108                 *regmap = info->regmap_pmu;
2109         else
2110                 *regmap = info->regmap_base;
2111
2112         *reg = bank->drv[drv_num].offset;
2113         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2114             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2115                 *bit = (pin_num % 8) * 3;
2116         else
2117                 *bit = (pin_num % 8) * 2;
2118 }
2119
2120 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2121         { 2, 4, 8, 12, -1, -1, -1, -1 },
2122         { 3, 6, 9, 12, -1, -1, -1, -1 },
2123         { 5, 10, 15, 20, -1, -1, -1, -1 },
2124         { 4, 6, 8, 10, 12, 14, 16, 18 },
2125         { 4, 7, 10, 13, 16, 19, 22, 26 }
2126 };
2127
2128 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2129                                      int pin_num)
2130 {
2131         struct rockchip_pinctrl *info = bank->drvdata;
2132         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2133         struct regmap *regmap;
2134         int reg, ret;
2135         u32 data, temp, rmask_bits;
2136         u8 bit;
2137         int drv_type = bank->drv[pin_num / 8].drv_type;
2138
2139         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2140
2141         switch (drv_type) {
2142         case DRV_TYPE_IO_1V8_3V0_AUTO:
2143         case DRV_TYPE_IO_3V3_ONLY:
2144                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2145                 switch (bit) {
2146                 case 0 ... 12:
2147                         /* regular case, nothing to do */
2148                         break;
2149                 case 15:
2150                         /*
2151                          * drive-strength offset is special, as it is
2152                          * spread over 2 registers
2153                          */
2154                         ret = regmap_read(regmap, reg, &data);
2155                         if (ret)
2156                                 return ret;
2157
2158                         ret = regmap_read(regmap, reg + 0x4, &temp);
2159                         if (ret)
2160                                 return ret;
2161
2162                         /*
2163                          * the bit data[15] contains bit 0 of the value
2164                          * while temp[1:0] contains bits 2 and 1
2165                          */
2166                         data >>= 15;
2167                         temp &= 0x3;
2168                         temp <<= 1;
2169                         data |= temp;
2170
2171                         return rockchip_perpin_drv_list[drv_type][data];
2172                 case 18 ... 21:
2173                         /* setting fully enclosed in the second register */
2174                         reg += 4;
2175                         bit -= 16;
2176                         break;
2177                 default:
2178                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2179                                 bit, drv_type);
2180                         return -EINVAL;
2181                 }
2182
2183                 break;
2184         case DRV_TYPE_IO_DEFAULT:
2185         case DRV_TYPE_IO_1V8_OR_3V0:
2186         case DRV_TYPE_IO_1V8_ONLY:
2187                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2188                 break;
2189         default:
2190                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2191                         drv_type);
2192                 return -EINVAL;
2193         }
2194
2195         ret = regmap_read(regmap, reg, &data);
2196         if (ret)
2197                 return ret;
2198
2199         data >>= bit;
2200         data &= (1 << rmask_bits) - 1;
2201
2202         return rockchip_perpin_drv_list[drv_type][data];
2203 }
2204
2205 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2206                                      int pin_num, int strength)
2207 {
2208         struct rockchip_pinctrl *info = bank->drvdata;
2209         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2210         struct regmap *regmap;
2211         int reg, ret, i;
2212         u32 data, rmask, rmask_bits, temp;
2213         u8 bit;
2214         int drv_type = bank->drv[pin_num / 8].drv_type;
2215
2216         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
2217                 bank->bank_num, pin_num, strength);
2218
2219         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2220
2221         ret = -EINVAL;
2222         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2223                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2224                         ret = i;
2225                         break;
2226                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2227                         ret = rockchip_perpin_drv_list[drv_type][i];
2228                         break;
2229                 }
2230         }
2231
2232         if (ret < 0) {
2233                 dev_err(info->dev, "unsupported driver strength %d\n",
2234                         strength);
2235                 return ret;
2236         }
2237
2238         switch (drv_type) {
2239         case DRV_TYPE_IO_1V8_3V0_AUTO:
2240         case DRV_TYPE_IO_3V3_ONLY:
2241                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2242                 switch (bit) {
2243                 case 0 ... 12:
2244                         /* regular case, nothing to do */
2245                         break;
2246                 case 15:
2247                         /*
2248                          * drive-strength offset is special, as it is spread
2249                          * over 2 registers, the bit data[15] contains bit 0
2250                          * of the value while temp[1:0] contains bits 2 and 1
2251                          */
2252                         data = (ret & 0x1) << 15;
2253                         temp = (ret >> 0x1) & 0x3;
2254
2255                         rmask = BIT(15) | BIT(31);
2256                         data |= BIT(31);
2257                         ret = regmap_update_bits(regmap, reg, rmask, data);
2258                         if (ret)
2259                                 return ret;
2260
2261                         rmask = 0x3 | (0x3 << 16);
2262                         temp |= (0x3 << 16);
2263                         reg += 0x4;
2264                         ret = regmap_update_bits(regmap, reg, rmask, temp);
2265
2266                         return ret;
2267                 case 18 ... 21:
2268                         /* setting fully enclosed in the second register */
2269                         reg += 4;
2270                         bit -= 16;
2271                         break;
2272                 default:
2273                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2274                                 bit, drv_type);
2275                         return -EINVAL;
2276                 }
2277                 break;
2278         case DRV_TYPE_IO_DEFAULT:
2279         case DRV_TYPE_IO_1V8_OR_3V0:
2280         case DRV_TYPE_IO_1V8_ONLY:
2281                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2282                 break;
2283         default:
2284                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2285                         drv_type);
2286                 return -EINVAL;
2287         }
2288
2289         /* enable the write to the equivalent lower bits */
2290         data = ((1 << rmask_bits) - 1) << (bit + 16);
2291         rmask = data | (data >> 16);
2292         data |= (ret << bit);
2293
2294         ret = regmap_update_bits(regmap, reg, rmask, data);
2295
2296         return ret;
2297 }
2298
2299 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2300         {
2301                 PIN_CONFIG_BIAS_DISABLE,
2302                 PIN_CONFIG_BIAS_PULL_UP,
2303                 PIN_CONFIG_BIAS_PULL_DOWN,
2304                 PIN_CONFIG_BIAS_BUS_HOLD
2305         },
2306         {
2307                 PIN_CONFIG_BIAS_DISABLE,
2308                 PIN_CONFIG_BIAS_PULL_DOWN,
2309                 PIN_CONFIG_BIAS_DISABLE,
2310                 PIN_CONFIG_BIAS_PULL_UP
2311         },
2312 };
2313
2314 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2315 {
2316         struct rockchip_pinctrl *info = bank->drvdata;
2317         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2318         struct regmap *regmap;
2319         int reg, ret, pull_type;
2320         u8 bit;
2321         u32 data;
2322
2323         /* rk3066b does support any pulls */
2324         if (ctrl->type == RK3066B)
2325                 return PIN_CONFIG_BIAS_DISABLE;
2326
2327         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2328
2329         ret = regmap_read(regmap, reg, &data);
2330         if (ret)
2331                 return ret;
2332
2333         switch (ctrl->type) {
2334         case RK2928:
2335         case RK3128:
2336                 return !(data & BIT(bit))
2337                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2338                                 : PIN_CONFIG_BIAS_DISABLE;
2339         case PX30:
2340         case RV1108:
2341         case RK3188:
2342         case RK3288:
2343         case RK3308:
2344         case RK3368:
2345         case RK3399:
2346                 pull_type = bank->pull_type[pin_num / 8];
2347                 data >>= bit;
2348                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2349
2350                 return rockchip_pull_list[pull_type][data];
2351         default:
2352                 dev_err(info->dev, "unsupported pinctrl type\n");
2353                 return -EINVAL;
2354         };
2355 }
2356
2357 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2358                                         int pin_num, int pull)
2359 {
2360         struct rockchip_pinctrl *info = bank->drvdata;
2361         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2362         struct regmap *regmap;
2363         int reg, ret, i, pull_type;
2364         u8 bit;
2365         u32 data, rmask;
2366
2367         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2368                  bank->bank_num, pin_num, pull);
2369
2370         /* rk3066b does support any pulls */
2371         if (ctrl->type == RK3066B)
2372                 return pull ? -EINVAL : 0;
2373
2374         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2375
2376         switch (ctrl->type) {
2377         case RK2928:
2378         case RK3128:
2379                 data = BIT(bit + 16);
2380                 if (pull == PIN_CONFIG_BIAS_DISABLE)
2381                         data |= BIT(bit);
2382                 ret = regmap_write(regmap, reg, data);
2383                 break;
2384         case PX30:
2385         case RV1108:
2386         case RK3188:
2387         case RK3288:
2388         case RK3308:
2389         case RK3368:
2390         case RK3399:
2391                 pull_type = bank->pull_type[pin_num / 8];
2392                 ret = -EINVAL;
2393                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2394                         i++) {
2395                         if (rockchip_pull_list[pull_type][i] == pull) {
2396                                 ret = i;
2397                                 break;
2398                         }
2399                 }
2400
2401                 if (ret < 0) {
2402                         dev_err(info->dev, "unsupported pull setting %d\n",
2403                                 pull);
2404                         return ret;
2405                 }
2406
2407                 /* enable the write to the equivalent lower bits */
2408                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2409                 rmask = data | (data >> 16);
2410                 data |= (ret << bit);
2411
2412                 ret = regmap_update_bits(regmap, reg, rmask, data);
2413                 break;
2414         default:
2415                 dev_err(info->dev, "unsupported pinctrl type\n");
2416                 return -EINVAL;
2417         }
2418
2419         return ret;
2420 }
2421
2422 #define RK3328_SCHMITT_BITS_PER_PIN             1
2423 #define RK3328_SCHMITT_PINS_PER_REG             16
2424 #define RK3328_SCHMITT_BANK_STRIDE              8
2425 #define RK3328_SCHMITT_GRF_OFFSET               0x380
2426
2427 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2428                                            int pin_num,
2429                                            struct regmap **regmap,
2430                                            int *reg, u8 *bit)
2431 {
2432         struct rockchip_pinctrl *info = bank->drvdata;
2433
2434         *regmap = info->regmap_base;
2435         *reg = RK3328_SCHMITT_GRF_OFFSET;
2436
2437         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2438         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2439         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2440
2441         return 0;
2442 }
2443
2444 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2445 {
2446         struct rockchip_pinctrl *info = bank->drvdata;
2447         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2448         struct regmap *regmap;
2449         int reg, ret;
2450         u8 bit;
2451         u32 data;
2452
2453         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2454         if (ret)
2455                 return ret;
2456
2457         ret = regmap_read(regmap, reg, &data);
2458         if (ret)
2459                 return ret;
2460
2461         data >>= bit;
2462         return data & 0x1;
2463 }
2464
2465 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2466                                 int pin_num, int enable)
2467 {
2468         struct rockchip_pinctrl *info = bank->drvdata;
2469         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2470         struct regmap *regmap;
2471         int reg, ret;
2472         u8 bit;
2473         u32 data, rmask;
2474
2475         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2476                 bank->bank_num, pin_num, enable);
2477
2478         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2479         if (ret)
2480                 return ret;
2481
2482         /* enable the write to the equivalent lower bits */
2483         data = BIT(bit + 16) | (enable << bit);
2484         rmask = BIT(bit + 16) | BIT(bit);
2485
2486         return regmap_update_bits(regmap, reg, rmask, data);
2487 }
2488
2489 /*
2490  * Pinmux_ops handling
2491  */
2492
2493 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2494 {
2495         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2496
2497         return info->nfunctions;
2498 }
2499
2500 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2501                                           unsigned selector)
2502 {
2503         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2504
2505         return info->functions[selector].name;
2506 }
2507
2508 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2509                                 unsigned selector, const char * const **groups,
2510                                 unsigned * const num_groups)
2511 {
2512         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2513
2514         *groups = info->functions[selector].groups;
2515         *num_groups = info->functions[selector].ngroups;
2516
2517         return 0;
2518 }
2519
2520 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2521                             unsigned group)
2522 {
2523         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2524         const unsigned int *pins = info->groups[group].pins;
2525         const struct rockchip_pin_config *data = info->groups[group].data;
2526         struct rockchip_pin_bank *bank;
2527         int cnt, ret = 0;
2528
2529         dev_dbg(info->dev, "enable function %s group %s\n",
2530                 info->functions[selector].name, info->groups[group].name);
2531
2532         /*
2533          * for each pin in the pin group selected, program the corresponding
2534          * pin function number in the config register.
2535          */
2536         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2537                 bank = pin_to_bank(info, pins[cnt]);
2538                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2539                                        data[cnt].func);
2540                 if (ret)
2541                         break;
2542         }
2543
2544         if (ret) {
2545                 /* revert the already done pin settings */
2546                 for (cnt--; cnt >= 0; cnt--)
2547                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2548
2549                 return ret;
2550         }
2551
2552         return 0;
2553 }
2554
2555 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2556 {
2557         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2558         u32 data;
2559         int ret;
2560
2561         ret = clk_enable(bank->clk);
2562         if (ret < 0) {
2563                 dev_err(bank->drvdata->dev,
2564                         "failed to enable clock for bank %s\n", bank->name);
2565                 return ret;
2566         }
2567         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2568         clk_disable(bank->clk);
2569
2570         if (data & BIT(offset))
2571                 return GPIO_LINE_DIRECTION_OUT;
2572
2573         return GPIO_LINE_DIRECTION_IN;
2574 }
2575
2576 /*
2577  * The calls to gpio_direction_output() and gpio_direction_input()
2578  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2579  * function called from the gpiolib interface).
2580  */
2581 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2582                                             int pin, bool input)
2583 {
2584         struct rockchip_pin_bank *bank;
2585         int ret;
2586         unsigned long flags;
2587         u32 data;
2588
2589         bank = gpiochip_get_data(chip);
2590
2591         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2592         if (ret < 0)
2593                 return ret;
2594
2595         clk_enable(bank->clk);
2596         raw_spin_lock_irqsave(&bank->slock, flags);
2597
2598         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2599         /* set bit to 1 for output, 0 for input */
2600         if (!input)
2601                 data |= BIT(pin);
2602         else
2603                 data &= ~BIT(pin);
2604         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2605
2606         raw_spin_unlock_irqrestore(&bank->slock, flags);
2607         clk_disable(bank->clk);
2608
2609         return 0;
2610 }
2611
2612 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2613                                               struct pinctrl_gpio_range *range,
2614                                               unsigned offset, bool input)
2615 {
2616         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2617         struct gpio_chip *chip;
2618         int pin;
2619
2620         chip = range->gc;
2621         pin = offset - chip->base;
2622         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2623                  offset, range->name, pin, input ? "input" : "output");
2624
2625         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2626                                                 input);
2627 }
2628
2629 static const struct pinmux_ops rockchip_pmx_ops = {
2630         .get_functions_count    = rockchip_pmx_get_funcs_count,
2631         .get_function_name      = rockchip_pmx_get_func_name,
2632         .get_function_groups    = rockchip_pmx_get_groups,
2633         .set_mux                = rockchip_pmx_set,
2634         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2635 };
2636
2637 /*
2638  * Pinconf_ops handling
2639  */
2640
2641 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2642                                         enum pin_config_param pull)
2643 {
2644         switch (ctrl->type) {
2645         case RK2928:
2646         case RK3128:
2647                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2648                                         pull == PIN_CONFIG_BIAS_DISABLE);
2649         case RK3066B:
2650                 return pull ? false : true;
2651         case PX30:
2652         case RV1108:
2653         case RK3188:
2654         case RK3288:
2655         case RK3308:
2656         case RK3368:
2657         case RK3399:
2658                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2659         }
2660
2661         return false;
2662 }
2663
2664 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2665 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2666
2667 /* set the pin config settings for a specified pin */
2668 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2669                                 unsigned long *configs, unsigned num_configs)
2670 {
2671         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2672         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2673         enum pin_config_param param;
2674         u32 arg;
2675         int i;
2676         int rc;
2677
2678         for (i = 0; i < num_configs; i++) {
2679                 param = pinconf_to_config_param(configs[i]);
2680                 arg = pinconf_to_config_argument(configs[i]);
2681
2682                 switch (param) {
2683                 case PIN_CONFIG_BIAS_DISABLE:
2684                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2685                                 param);
2686                         if (rc)
2687                                 return rc;
2688                         break;
2689                 case PIN_CONFIG_BIAS_PULL_UP:
2690                 case PIN_CONFIG_BIAS_PULL_DOWN:
2691                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2692                 case PIN_CONFIG_BIAS_BUS_HOLD:
2693                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2694                                 return -ENOTSUPP;
2695
2696                         if (!arg)
2697                                 return -EINVAL;
2698
2699                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2700                                 param);
2701                         if (rc)
2702                                 return rc;
2703                         break;
2704                 case PIN_CONFIG_OUTPUT:
2705                         rockchip_gpio_set(&bank->gpio_chip,
2706                                           pin - bank->pin_base, arg);
2707                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2708                                           pin - bank->pin_base, false);
2709                         if (rc)
2710                                 return rc;
2711                         break;
2712                 case PIN_CONFIG_DRIVE_STRENGTH:
2713                         /* rk3288 is the first with per-pin drive-strength */
2714                         if (!info->ctrl->drv_calc_reg)
2715                                 return -ENOTSUPP;
2716
2717                         rc = rockchip_set_drive_perpin(bank,
2718                                                 pin - bank->pin_base, arg);
2719                         if (rc < 0)
2720                                 return rc;
2721                         break;
2722                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2723                         if (!info->ctrl->schmitt_calc_reg)
2724                                 return -ENOTSUPP;
2725
2726                         rc = rockchip_set_schmitt(bank,
2727                                                   pin - bank->pin_base, arg);
2728                         if (rc < 0)
2729                                 return rc;
2730                         break;
2731                 default:
2732                         return -ENOTSUPP;
2733                         break;
2734                 }
2735         } /* for each config */
2736
2737         return 0;
2738 }
2739
2740 /* get the pin config settings for a specified pin */
2741 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2742                                                         unsigned long *config)
2743 {
2744         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2745         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2746         enum pin_config_param param = pinconf_to_config_param(*config);
2747         u16 arg;
2748         int rc;
2749
2750         switch (param) {
2751         case PIN_CONFIG_BIAS_DISABLE:
2752                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2753                         return -EINVAL;
2754
2755                 arg = 0;
2756                 break;
2757         case PIN_CONFIG_BIAS_PULL_UP:
2758         case PIN_CONFIG_BIAS_PULL_DOWN:
2759         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2760         case PIN_CONFIG_BIAS_BUS_HOLD:
2761                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2762                         return -ENOTSUPP;
2763
2764                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2765                         return -EINVAL;
2766
2767                 arg = 1;
2768                 break;
2769         case PIN_CONFIG_OUTPUT:
2770                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2771                 if (rc != RK_FUNC_GPIO)
2772                         return -EINVAL;
2773
2774                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2775                 if (rc < 0)
2776                         return rc;
2777
2778                 arg = rc ? 1 : 0;
2779                 break;
2780         case PIN_CONFIG_DRIVE_STRENGTH:
2781                 /* rk3288 is the first with per-pin drive-strength */
2782                 if (!info->ctrl->drv_calc_reg)
2783                         return -ENOTSUPP;
2784
2785                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2786                 if (rc < 0)
2787                         return rc;
2788
2789                 arg = rc;
2790                 break;
2791         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2792                 if (!info->ctrl->schmitt_calc_reg)
2793                         return -ENOTSUPP;
2794
2795                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2796                 if (rc < 0)
2797                         return rc;
2798
2799                 arg = rc;
2800                 break;
2801         default:
2802                 return -ENOTSUPP;
2803                 break;
2804         }
2805
2806         *config = pinconf_to_config_packed(param, arg);
2807
2808         return 0;
2809 }
2810
2811 static const struct pinconf_ops rockchip_pinconf_ops = {
2812         .pin_config_get                 = rockchip_pinconf_get,
2813         .pin_config_set                 = rockchip_pinconf_set,
2814         .is_generic                     = true,
2815 };
2816
2817 static const struct of_device_id rockchip_bank_match[] = {
2818         { .compatible = "rockchip,gpio-bank" },
2819         { .compatible = "rockchip,rk3188-gpio-bank0" },
2820         {},
2821 };
2822
2823 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2824                                                 struct device_node *np)
2825 {
2826         struct device_node *child;
2827
2828         for_each_child_of_node(np, child) {
2829                 if (of_match_node(rockchip_bank_match, child))
2830                         continue;
2831
2832                 info->nfunctions++;
2833                 info->ngroups += of_get_child_count(child);
2834         }
2835 }
2836
2837 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2838                                               struct rockchip_pin_group *grp,
2839                                               struct rockchip_pinctrl *info,
2840                                               u32 index)
2841 {
2842         struct rockchip_pin_bank *bank;
2843         int size;
2844         const __be32 *list;
2845         int num;
2846         int i, j;
2847         int ret;
2848
2849         dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2850
2851         /* Initialise group */
2852         grp->name = np->name;
2853
2854         /*
2855          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2856          * do sanity check and calculate pins number
2857          */
2858         list = of_get_property(np, "rockchip,pins", &size);
2859         /* we do not check return since it's safe node passed down */
2860         size /= sizeof(*list);
2861         if (!size || size % 4) {
2862                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2863                 return -EINVAL;
2864         }
2865
2866         grp->npins = size / 4;
2867
2868         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2869                                                 GFP_KERNEL);
2870         grp->data = devm_kcalloc(info->dev,
2871                                         grp->npins,
2872                                         sizeof(struct rockchip_pin_config),
2873                                         GFP_KERNEL);
2874         if (!grp->pins || !grp->data)
2875                 return -ENOMEM;
2876
2877         for (i = 0, j = 0; i < size; i += 4, j++) {
2878                 const __be32 *phandle;
2879                 struct device_node *np_config;
2880
2881                 num = be32_to_cpu(*list++);
2882                 bank = bank_num_to_bank(info, num);
2883                 if (IS_ERR(bank))
2884                         return PTR_ERR(bank);
2885
2886                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2887                 grp->data[j].func = be32_to_cpu(*list++);
2888
2889                 phandle = list++;
2890                 if (!phandle)
2891                         return -EINVAL;
2892
2893                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2894                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2895                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2896                 if (ret)
2897                         return ret;
2898         }
2899
2900         return 0;
2901 }
2902
2903 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2904                                                 struct rockchip_pinctrl *info,
2905                                                 u32 index)
2906 {
2907         struct device_node *child;
2908         struct rockchip_pmx_func *func;
2909         struct rockchip_pin_group *grp;
2910         int ret;
2911         static u32 grp_index;
2912         u32 i = 0;
2913
2914         dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2915
2916         func = &info->functions[index];
2917
2918         /* Initialise function */
2919         func->name = np->name;
2920         func->ngroups = of_get_child_count(np);
2921         if (func->ngroups <= 0)
2922                 return 0;
2923
2924         func->groups = devm_kcalloc(info->dev,
2925                         func->ngroups, sizeof(char *), GFP_KERNEL);
2926         if (!func->groups)
2927                 return -ENOMEM;
2928
2929         for_each_child_of_node(np, child) {
2930                 func->groups[i] = child->name;
2931                 grp = &info->groups[grp_index++];
2932                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2933                 if (ret) {
2934                         of_node_put(child);
2935                         return ret;
2936                 }
2937         }
2938
2939         return 0;
2940 }
2941
2942 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2943                                               struct rockchip_pinctrl *info)
2944 {
2945         struct device *dev = &pdev->dev;
2946         struct device_node *np = dev->of_node;
2947         struct device_node *child;
2948         int ret;
2949         int i;
2950
2951         rockchip_pinctrl_child_count(info, np);
2952
2953         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2954         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2955
2956         info->functions = devm_kcalloc(dev,
2957                                               info->nfunctions,
2958                                               sizeof(struct rockchip_pmx_func),
2959                                               GFP_KERNEL);
2960         if (!info->functions)
2961                 return -ENOMEM;
2962
2963         info->groups = devm_kcalloc(dev,
2964                                             info->ngroups,
2965                                             sizeof(struct rockchip_pin_group),
2966                                             GFP_KERNEL);
2967         if (!info->groups)
2968                 return -ENOMEM;
2969
2970         i = 0;
2971
2972         for_each_child_of_node(np, child) {
2973                 if (of_match_node(rockchip_bank_match, child))
2974                         continue;
2975
2976                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2977                 if (ret) {
2978                         dev_err(&pdev->dev, "failed to parse function\n");
2979                         of_node_put(child);
2980                         return ret;
2981                 }
2982         }
2983
2984         return 0;
2985 }
2986
2987 static int rockchip_pinctrl_register(struct platform_device *pdev,
2988                                         struct rockchip_pinctrl *info)
2989 {
2990         struct pinctrl_desc *ctrldesc = &info->pctl;
2991         struct pinctrl_pin_desc *pindesc, *pdesc;
2992         struct rockchip_pin_bank *pin_bank;
2993         int pin, bank, ret;
2994         int k;
2995
2996         ctrldesc->name = "rockchip-pinctrl";
2997         ctrldesc->owner = THIS_MODULE;
2998         ctrldesc->pctlops = &rockchip_pctrl_ops;
2999         ctrldesc->pmxops = &rockchip_pmx_ops;
3000         ctrldesc->confops = &rockchip_pinconf_ops;
3001
3002         pindesc = devm_kcalloc(&pdev->dev,
3003                                info->ctrl->nr_pins, sizeof(*pindesc),
3004                                GFP_KERNEL);
3005         if (!pindesc)
3006                 return -ENOMEM;
3007
3008         ctrldesc->pins = pindesc;
3009         ctrldesc->npins = info->ctrl->nr_pins;
3010
3011         pdesc = pindesc;
3012         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
3013                 pin_bank = &info->ctrl->pin_banks[bank];
3014                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3015                         pdesc->number = k;
3016                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
3017                                                 pin_bank->name, pin);
3018                         pdesc++;
3019                 }
3020         }
3021
3022         ret = rockchip_pinctrl_parse_dt(pdev, info);
3023         if (ret)
3024                 return ret;
3025
3026         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3027         if (IS_ERR(info->pctl_dev)) {
3028                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
3029                 return PTR_ERR(info->pctl_dev);
3030         }
3031
3032         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
3033                 pin_bank = &info->ctrl->pin_banks[bank];
3034                 pin_bank->grange.name = pin_bank->name;
3035                 pin_bank->grange.id = bank;
3036                 pin_bank->grange.pin_base = pin_bank->pin_base;
3037                 pin_bank->grange.base = pin_bank->gpio_chip.base;
3038                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
3039                 pin_bank->grange.gc = &pin_bank->gpio_chip;
3040                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
3041         }
3042
3043         return 0;
3044 }
3045
3046 /*
3047  * GPIO handling
3048  */
3049
3050 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3051 {
3052         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3053         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
3054         unsigned long flags;
3055         u32 data;
3056
3057         clk_enable(bank->clk);
3058         raw_spin_lock_irqsave(&bank->slock, flags);
3059
3060         data = readl(reg);
3061         data &= ~BIT(offset);
3062         if (value)
3063                 data |= BIT(offset);
3064         writel(data, reg);
3065
3066         raw_spin_unlock_irqrestore(&bank->slock, flags);
3067         clk_disable(bank->clk);
3068 }
3069
3070 /*
3071  * Returns the level of the pin for input direction and setting of the DR
3072  * register for output gpios.
3073  */
3074 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
3075 {
3076         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3077         u32 data;
3078
3079         clk_enable(bank->clk);
3080         data = readl(bank->reg_base + GPIO_EXT_PORT);
3081         clk_disable(bank->clk);
3082         data >>= offset;
3083         data &= 1;
3084         return data;
3085 }
3086
3087 /*
3088  * gpiolib gpio_direction_input callback function. The setting of the pin
3089  * mux function as 'gpio input' will be handled by the pinctrl subsystem
3090  * interface.
3091  */
3092 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
3093 {
3094         return pinctrl_gpio_direction_input(gc->base + offset);
3095 }
3096
3097 /*
3098  * gpiolib gpio_direction_output callback function. The setting of the pin
3099  * mux function as 'gpio output' will be handled by the pinctrl subsystem
3100  * interface.
3101  */
3102 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
3103                                           unsigned offset, int value)
3104 {
3105         rockchip_gpio_set(gc, offset, value);
3106         return pinctrl_gpio_direction_output(gc->base + offset);
3107 }
3108
3109 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
3110                                        unsigned int offset, bool enable)
3111 {
3112         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3113         void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
3114         unsigned long flags;
3115         u32 data;
3116
3117         clk_enable(bank->clk);
3118         raw_spin_lock_irqsave(&bank->slock, flags);
3119
3120         data = readl(reg);
3121         if (enable)
3122                 data |= BIT(offset);
3123         else
3124                 data &= ~BIT(offset);
3125         writel(data, reg);
3126
3127         raw_spin_unlock_irqrestore(&bank->slock, flags);
3128         clk_disable(bank->clk);
3129 }
3130
3131 /*
3132  * gpiolib set_config callback function. The setting of the pin
3133  * mux function as 'gpio output' will be handled by the pinctrl subsystem
3134  * interface.
3135  */
3136 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
3137                                   unsigned long config)
3138 {
3139         enum pin_config_param param = pinconf_to_config_param(config);
3140
3141         switch (param) {
3142         case PIN_CONFIG_INPUT_DEBOUNCE:
3143                 rockchip_gpio_set_debounce(gc, offset, true);
3144                 /*
3145                  * Rockchip's gpio could only support up to one period
3146                  * of the debounce clock(pclk), which is far away from
3147                  * satisftying the requirement, as pclk is usually near
3148                  * 100MHz shared by all peripherals. So the fact is it
3149                  * has crippled debounce capability could only be useful
3150                  * to prevent any spurious glitches from waking up the system
3151                  * if the gpio is conguired as wakeup interrupt source. Let's
3152                  * still return -ENOTSUPP as before, to make sure the caller
3153                  * of gpiod_set_debounce won't change its behaviour.
3154                  */
3155                 return -ENOTSUPP;
3156         default:
3157                 return -ENOTSUPP;
3158         }
3159 }
3160
3161 /*
3162  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
3163  * and a virtual IRQ, if not already present.
3164  */
3165 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
3166 {
3167         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3168         unsigned int virq;
3169
3170         if (!bank->domain)
3171                 return -ENXIO;
3172
3173         clk_enable(bank->clk);
3174         virq = irq_create_mapping(bank->domain, offset);
3175         clk_disable(bank->clk);
3176
3177         return (virq) ? : -ENXIO;
3178 }
3179
3180 static const struct gpio_chip rockchip_gpiolib_chip = {
3181         .request = gpiochip_generic_request,
3182         .free = gpiochip_generic_free,
3183         .set = rockchip_gpio_set,
3184         .get = rockchip_gpio_get,
3185         .get_direction  = rockchip_gpio_get_direction,
3186         .direction_input = rockchip_gpio_direction_input,
3187         .direction_output = rockchip_gpio_direction_output,
3188         .set_config = rockchip_gpio_set_config,
3189         .to_irq = rockchip_gpio_to_irq,
3190         .owner = THIS_MODULE,
3191 };
3192
3193 /*
3194  * Interrupt handling
3195  */
3196
3197 static void rockchip_irq_demux(struct irq_desc *desc)
3198 {
3199         struct irq_chip *chip = irq_desc_get_chip(desc);
3200         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
3201         u32 pend;
3202
3203         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
3204
3205         chained_irq_enter(chip, desc);
3206
3207         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
3208
3209         while (pend) {
3210                 unsigned int irq, virq;
3211
3212                 irq = __ffs(pend);
3213                 pend &= ~BIT(irq);
3214                 virq = irq_find_mapping(bank->domain, irq);
3215
3216                 if (!virq) {
3217                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
3218                         continue;
3219                 }
3220
3221                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
3222
3223                 /*
3224                  * Triggering IRQ on both rising and falling edge
3225                  * needs manual intervention.
3226                  */
3227                 if (bank->toggle_edge_mode & BIT(irq)) {
3228                         u32 data, data_old, polarity;
3229                         unsigned long flags;
3230
3231                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
3232                         do {
3233                                 raw_spin_lock_irqsave(&bank->slock, flags);
3234
3235                                 polarity = readl_relaxed(bank->reg_base +
3236                                                          GPIO_INT_POLARITY);
3237                                 if (data & BIT(irq))
3238                                         polarity &= ~BIT(irq);
3239                                 else
3240                                         polarity |= BIT(irq);
3241                                 writel(polarity,
3242                                        bank->reg_base + GPIO_INT_POLARITY);
3243
3244                                 raw_spin_unlock_irqrestore(&bank->slock, flags);
3245
3246                                 data_old = data;
3247                                 data = readl_relaxed(bank->reg_base +
3248                                                      GPIO_EXT_PORT);
3249                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
3250                 }
3251
3252                 generic_handle_irq(virq);
3253         }
3254
3255         chained_irq_exit(chip, desc);
3256 }
3257
3258 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
3259 {
3260         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3261         struct rockchip_pin_bank *bank = gc->private;
3262         u32 mask = BIT(d->hwirq);
3263         u32 polarity;
3264         u32 level;
3265         u32 data;
3266         unsigned long flags;
3267         int ret;
3268
3269         /* make sure the pin is configured as gpio input */
3270         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3271         if (ret < 0)
3272                 return ret;
3273
3274         clk_enable(bank->clk);
3275         raw_spin_lock_irqsave(&bank->slock, flags);
3276
3277         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3278         data &= ~mask;
3279         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3280
3281         raw_spin_unlock_irqrestore(&bank->slock, flags);
3282
3283         if (type & IRQ_TYPE_EDGE_BOTH)
3284                 irq_set_handler_locked(d, handle_edge_irq);
3285         else
3286                 irq_set_handler_locked(d, handle_level_irq);
3287
3288         raw_spin_lock_irqsave(&bank->slock, flags);
3289         irq_gc_lock(gc);
3290
3291         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
3292         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
3293
3294         switch (type) {
3295         case IRQ_TYPE_EDGE_BOTH:
3296                 bank->toggle_edge_mode |= mask;
3297                 level |= mask;
3298
3299                 /*
3300                  * Determine gpio state. If 1 next interrupt should be falling
3301                  * otherwise rising.
3302                  */
3303                 data = readl(bank->reg_base + GPIO_EXT_PORT);
3304                 if (data & mask)
3305                         polarity &= ~mask;
3306                 else
3307                         polarity |= mask;
3308                 break;
3309         case IRQ_TYPE_EDGE_RISING:
3310                 bank->toggle_edge_mode &= ~mask;
3311                 level |= mask;
3312                 polarity |= mask;
3313                 break;
3314         case IRQ_TYPE_EDGE_FALLING:
3315                 bank->toggle_edge_mode &= ~mask;
3316                 level |= mask;
3317                 polarity &= ~mask;
3318                 break;
3319         case IRQ_TYPE_LEVEL_HIGH:
3320                 bank->toggle_edge_mode &= ~mask;
3321                 level &= ~mask;
3322                 polarity |= mask;
3323                 break;
3324         case IRQ_TYPE_LEVEL_LOW:
3325                 bank->toggle_edge_mode &= ~mask;
3326                 level &= ~mask;
3327                 polarity &= ~mask;
3328                 break;
3329         default:
3330                 irq_gc_unlock(gc);
3331                 raw_spin_unlock_irqrestore(&bank->slock, flags);
3332                 clk_disable(bank->clk);
3333                 return -EINVAL;
3334         }
3335
3336         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
3337         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
3338
3339         irq_gc_unlock(gc);
3340         raw_spin_unlock_irqrestore(&bank->slock, flags);
3341         clk_disable(bank->clk);
3342
3343         return 0;
3344 }
3345
3346 static void rockchip_irq_suspend(struct irq_data *d)
3347 {
3348         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3349         struct rockchip_pin_bank *bank = gc->private;
3350
3351         clk_enable(bank->clk);
3352         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3353         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
3354         clk_disable(bank->clk);
3355 }
3356
3357 static void rockchip_irq_resume(struct irq_data *d)
3358 {
3359         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3360         struct rockchip_pin_bank *bank = gc->private;
3361
3362         clk_enable(bank->clk);
3363         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3364         clk_disable(bank->clk);
3365 }
3366
3367 static void rockchip_irq_enable(struct irq_data *d)
3368 {
3369         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3370         struct rockchip_pin_bank *bank = gc->private;
3371
3372         clk_enable(bank->clk);
3373         irq_gc_mask_clr_bit(d);
3374 }
3375
3376 static void rockchip_irq_disable(struct irq_data *d)
3377 {
3378         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3379         struct rockchip_pin_bank *bank = gc->private;
3380
3381         irq_gc_mask_set_bit(d);
3382         clk_disable(bank->clk);
3383 }
3384
3385 static int rockchip_interrupts_register(struct platform_device *pdev,
3386                                                 struct rockchip_pinctrl *info)
3387 {
3388         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3389         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3390         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3391         struct irq_chip_generic *gc;
3392         int ret;
3393         int i;
3394
3395         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3396                 if (!bank->valid) {
3397                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3398                                  bank->name);
3399                         continue;
3400                 }
3401
3402                 ret = clk_enable(bank->clk);
3403                 if (ret) {
3404                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3405                                 bank->name);
3406                         continue;
3407                 }
3408
3409                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3410                                                 &irq_generic_chip_ops, NULL);
3411                 if (!bank->domain) {
3412                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3413                                  bank->name);
3414                         clk_disable(bank->clk);
3415                         continue;
3416                 }
3417
3418                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3419                                          "rockchip_gpio_irq", handle_level_irq,
3420                                          clr, 0, 0);
3421                 if (ret) {
3422                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3423                                 bank->name);
3424                         irq_domain_remove(bank->domain);
3425                         clk_disable(bank->clk);
3426                         continue;
3427                 }
3428
3429                 gc = irq_get_domain_generic_chip(bank->domain, 0);
3430                 gc->reg_base = bank->reg_base;
3431                 gc->private = bank;
3432                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3433                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3434                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3435                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3436                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3437                 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3438                 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3439                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3440                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3441                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3442                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3443                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3444
3445                 /*
3446                  * Linux assumes that all interrupts start out disabled/masked.
3447                  * Our driver only uses the concept of masked and always keeps
3448                  * things enabled, so for us that's all masked and all enabled.
3449                  */
3450                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3451                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3452                 gc->mask_cache = 0xffffffff;
3453
3454                 irq_set_chained_handler_and_data(bank->irq,
3455                                                  rockchip_irq_demux, bank);
3456                 clk_disable(bank->clk);
3457         }
3458
3459         return 0;
3460 }
3461
3462 static int rockchip_gpiolib_register(struct platform_device *pdev,
3463                                                 struct rockchip_pinctrl *info)
3464 {
3465         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3466         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3467         struct gpio_chip *gc;
3468         int ret;
3469         int i;
3470
3471         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3472                 if (!bank->valid) {
3473                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3474                                  bank->name);
3475                         continue;
3476                 }
3477
3478                 bank->gpio_chip = rockchip_gpiolib_chip;
3479
3480                 gc = &bank->gpio_chip;
3481                 gc->base = bank->pin_base;
3482                 gc->ngpio = bank->nr_pins;
3483                 gc->parent = &pdev->dev;
3484                 gc->of_node = bank->of_node;
3485                 gc->label = bank->name;
3486
3487                 ret = gpiochip_add_data(gc, bank);
3488                 if (ret) {
3489                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3490                                                         gc->label, ret);
3491                         goto fail;
3492                 }
3493         }
3494
3495         rockchip_interrupts_register(pdev, info);
3496
3497         return 0;
3498
3499 fail:
3500         for (--i, --bank; i >= 0; --i, --bank) {
3501                 if (!bank->valid)
3502                         continue;
3503                 gpiochip_remove(&bank->gpio_chip);
3504         }
3505         return ret;
3506 }
3507
3508 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3509                                                 struct rockchip_pinctrl *info)
3510 {
3511         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3512         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3513         int i;
3514
3515         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3516                 if (!bank->valid)
3517                         continue;
3518                 gpiochip_remove(&bank->gpio_chip);
3519         }
3520
3521         return 0;
3522 }
3523
3524 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3525                                   struct rockchip_pinctrl *info)
3526 {
3527         struct resource res;
3528         void __iomem *base;
3529
3530         if (of_address_to_resource(bank->of_node, 0, &res)) {
3531                 dev_err(info->dev, "cannot find IO resource for bank\n");
3532                 return -ENOENT;
3533         }
3534
3535         bank->reg_base = devm_ioremap_resource(info->dev, &res);
3536         if (IS_ERR(bank->reg_base))
3537                 return PTR_ERR(bank->reg_base);
3538
3539         /*
3540          * special case, where parts of the pull setting-registers are
3541          * part of the PMU register space
3542          */
3543         if (of_device_is_compatible(bank->of_node,
3544                                     "rockchip,rk3188-gpio-bank0")) {
3545                 struct device_node *node;
3546
3547                 node = of_parse_phandle(bank->of_node->parent,
3548                                         "rockchip,pmu", 0);
3549                 if (!node) {
3550                         if (of_address_to_resource(bank->of_node, 1, &res)) {
3551                                 dev_err(info->dev, "cannot find IO resource for bank\n");
3552                                 return -ENOENT;
3553                         }
3554
3555                         base = devm_ioremap_resource(info->dev, &res);
3556                         if (IS_ERR(base))
3557                                 return PTR_ERR(base);
3558                         rockchip_regmap_config.max_register =
3559                                                     resource_size(&res) - 4;
3560                         rockchip_regmap_config.name =
3561                                             "rockchip,rk3188-gpio-bank0-pull";
3562                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3563                                                     base,
3564                                                     &rockchip_regmap_config);
3565                 }
3566                 of_node_put(node);
3567         }
3568
3569         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3570
3571         bank->clk = of_clk_get(bank->of_node, 0);
3572         if (IS_ERR(bank->clk))
3573                 return PTR_ERR(bank->clk);
3574
3575         return clk_prepare(bank->clk);
3576 }
3577
3578 static const struct of_device_id rockchip_pinctrl_dt_match[];
3579
3580 /* retrieve the soc specific data */
3581 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3582                                                 struct rockchip_pinctrl *d,
3583                                                 struct platform_device *pdev)
3584 {
3585         const struct of_device_id *match;
3586         struct device_node *node = pdev->dev.of_node;
3587         struct device_node *np;
3588         struct rockchip_pin_ctrl *ctrl;
3589         struct rockchip_pin_bank *bank;
3590         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3591
3592         match = of_match_node(rockchip_pinctrl_dt_match, node);
3593         ctrl = (struct rockchip_pin_ctrl *)match->data;
3594
3595         for_each_child_of_node(node, np) {
3596                 if (!of_find_property(np, "gpio-controller", NULL))
3597                         continue;
3598
3599                 bank = ctrl->pin_banks;
3600                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3601                         if (!strcmp(bank->name, np->name)) {
3602                                 bank->of_node = np;
3603
3604                                 if (!rockchip_get_bank_data(bank, d))
3605                                         bank->valid = true;
3606
3607                                 break;
3608                         }
3609                 }
3610         }
3611
3612         grf_offs = ctrl->grf_mux_offset;
3613         pmu_offs = ctrl->pmu_mux_offset;
3614         drv_pmu_offs = ctrl->pmu_drv_offset;
3615         drv_grf_offs = ctrl->grf_drv_offset;
3616         bank = ctrl->pin_banks;
3617         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3618                 int bank_pins = 0;
3619
3620                 raw_spin_lock_init(&bank->slock);
3621                 bank->drvdata = d;
3622                 bank->pin_base = ctrl->nr_pins;
3623                 ctrl->nr_pins += bank->nr_pins;
3624
3625                 /* calculate iomux and drv offsets */
3626                 for (j = 0; j < 4; j++) {
3627                         struct rockchip_iomux *iom = &bank->iomux[j];
3628                         struct rockchip_drv *drv = &bank->drv[j];
3629                         int inc;
3630
3631                         if (bank_pins >= bank->nr_pins)
3632                                 break;
3633
3634                         /* preset iomux offset value, set new start value */
3635                         if (iom->offset >= 0) {
3636                                 if (iom->type & IOMUX_SOURCE_PMU)
3637                                         pmu_offs = iom->offset;
3638                                 else
3639                                         grf_offs = iom->offset;
3640                         } else { /* set current iomux offset */
3641                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3642                                                         pmu_offs : grf_offs;
3643                         }
3644
3645                         /* preset drv offset value, set new start value */
3646                         if (drv->offset >= 0) {
3647                                 if (iom->type & IOMUX_SOURCE_PMU)
3648                                         drv_pmu_offs = drv->offset;
3649                                 else
3650                                         drv_grf_offs = drv->offset;
3651                         } else { /* set current drv offset */
3652                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3653                                                 drv_pmu_offs : drv_grf_offs;
3654                         }
3655
3656                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3657                                 i, j, iom->offset, drv->offset);
3658
3659                         /*
3660                          * Increase offset according to iomux width.
3661                          * 4bit iomux'es are spread over two registers.
3662                          */
3663                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3664                                             IOMUX_WIDTH_3BIT |
3665                                             IOMUX_WIDTH_2BIT)) ? 8 : 4;
3666                         if (iom->type & IOMUX_SOURCE_PMU)
3667                                 pmu_offs += inc;
3668                         else
3669                                 grf_offs += inc;
3670
3671                         /*
3672                          * Increase offset according to drv width.
3673                          * 3bit drive-strenth'es are spread over two registers.
3674                          */
3675                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3676                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3677                                 inc = 8;
3678                         else
3679                                 inc = 4;
3680
3681                         if (iom->type & IOMUX_SOURCE_PMU)
3682                                 drv_pmu_offs += inc;
3683                         else
3684                                 drv_grf_offs += inc;
3685
3686                         bank_pins += 8;
3687                 }
3688
3689                 /* calculate the per-bank recalced_mask */
3690                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3691                         int pin = 0;
3692
3693                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3694                                 pin = ctrl->iomux_recalced[j].pin;
3695                                 bank->recalced_mask |= BIT(pin);
3696                         }
3697                 }
3698
3699                 /* calculate the per-bank route_mask */
3700                 for (j = 0; j < ctrl->niomux_routes; j++) {
3701                         int pin = 0;
3702
3703                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3704                                 pin = ctrl->iomux_routes[j].pin;
3705                                 bank->route_mask |= BIT(pin);
3706                         }
3707                 }
3708         }
3709
3710         return ctrl;
3711 }
3712
3713 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3714 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3715
3716 static u32 rk3288_grf_gpio6c_iomux;
3717
3718 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3719 {
3720         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3721         int ret = pinctrl_force_sleep(info->pctl_dev);
3722
3723         if (ret)
3724                 return ret;
3725
3726         /*
3727          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3728          * the setting here, and restore it at resume.
3729          */
3730         if (info->ctrl->type == RK3288) {
3731                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3732                                   &rk3288_grf_gpio6c_iomux);
3733                 if (ret) {
3734                         pinctrl_force_default(info->pctl_dev);
3735                         return ret;
3736                 }
3737         }
3738
3739         return 0;
3740 }
3741
3742 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3743 {
3744         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3745         int ret;
3746
3747         if (info->ctrl->type == RK3288) {
3748                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3749                                    rk3288_grf_gpio6c_iomux |
3750                                    GPIO6C6_SEL_WRITE_ENABLE);
3751                 if (ret)
3752                         return ret;
3753         }
3754
3755         return pinctrl_force_default(info->pctl_dev);
3756 }
3757
3758 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3759                          rockchip_pinctrl_resume);
3760
3761 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3762 {
3763         struct rockchip_pinctrl *info;
3764         struct device *dev = &pdev->dev;
3765         struct rockchip_pin_ctrl *ctrl;
3766         struct device_node *np = pdev->dev.of_node, *node;
3767         struct resource *res;
3768         void __iomem *base;
3769         int ret;
3770
3771         if (!dev->of_node) {
3772                 dev_err(dev, "device tree node not found\n");
3773                 return -ENODEV;
3774         }
3775
3776         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3777         if (!info)
3778                 return -ENOMEM;
3779
3780         info->dev = dev;
3781
3782         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3783         if (!ctrl) {
3784                 dev_err(dev, "driver data not available\n");
3785                 return -EINVAL;
3786         }
3787         info->ctrl = ctrl;
3788
3789         node = of_parse_phandle(np, "rockchip,grf", 0);
3790         if (node) {
3791                 info->regmap_base = syscon_node_to_regmap(node);
3792                 of_node_put(node);
3793                 if (IS_ERR(info->regmap_base))
3794                         return PTR_ERR(info->regmap_base);
3795         } else {
3796                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3797                 base = devm_ioremap_resource(&pdev->dev, res);
3798                 if (IS_ERR(base))
3799                         return PTR_ERR(base);
3800
3801                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3802                 rockchip_regmap_config.name = "rockchip,pinctrl";
3803                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3804                                                     &rockchip_regmap_config);
3805
3806                 /* to check for the old dt-bindings */
3807                 info->reg_size = resource_size(res);
3808
3809                 /* Honor the old binding, with pull registers as 2nd resource */
3810                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3811                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3812                         base = devm_ioremap_resource(&pdev->dev, res);
3813                         if (IS_ERR(base))
3814                                 return PTR_ERR(base);
3815
3816                         rockchip_regmap_config.max_register =
3817                                                         resource_size(res) - 4;
3818                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3819                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3820                                                     base,
3821                                                     &rockchip_regmap_config);
3822                 }
3823         }
3824
3825         /* try to find the optional reference to the pmu syscon */
3826         node = of_parse_phandle(np, "rockchip,pmu", 0);
3827         if (node) {
3828                 info->regmap_pmu = syscon_node_to_regmap(node);
3829                 of_node_put(node);
3830                 if (IS_ERR(info->regmap_pmu))
3831                         return PTR_ERR(info->regmap_pmu);
3832         }
3833
3834         ret = rockchip_gpiolib_register(pdev, info);
3835         if (ret)
3836                 return ret;
3837
3838         ret = rockchip_pinctrl_register(pdev, info);
3839         if (ret) {
3840                 rockchip_gpiolib_unregister(pdev, info);
3841                 return ret;
3842         }
3843
3844         platform_set_drvdata(pdev, info);
3845
3846         return 0;
3847 }
3848
3849 static struct rockchip_pin_bank px30_pin_banks[] = {
3850         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3851                                              IOMUX_SOURCE_PMU,
3852                                              IOMUX_SOURCE_PMU,
3853                                              IOMUX_SOURCE_PMU
3854                             ),
3855         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3856                                              IOMUX_WIDTH_4BIT,
3857                                              IOMUX_WIDTH_4BIT,
3858                                              IOMUX_WIDTH_4BIT
3859                             ),
3860         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3861                                              IOMUX_WIDTH_4BIT,
3862                                              IOMUX_WIDTH_4BIT,
3863                                              IOMUX_WIDTH_4BIT
3864                             ),
3865         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3866                                              IOMUX_WIDTH_4BIT,
3867                                              IOMUX_WIDTH_4BIT,
3868                                              IOMUX_WIDTH_4BIT
3869                             ),
3870 };
3871
3872 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3873                 .pin_banks              = px30_pin_banks,
3874                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
3875                 .label                  = "PX30-GPIO",
3876                 .type                   = PX30,
3877                 .grf_mux_offset         = 0x0,
3878                 .pmu_mux_offset         = 0x0,
3879                 .iomux_routes           = px30_mux_route_data,
3880                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
3881                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
3882                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
3883                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
3884 };
3885
3886 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3887         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3888                                              IOMUX_SOURCE_PMU,
3889                                              IOMUX_SOURCE_PMU,
3890                                              IOMUX_SOURCE_PMU),
3891         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3892         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3893         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3894 };
3895
3896 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3897         .pin_banks              = rv1108_pin_banks,
3898         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3899         .label                  = "RV1108-GPIO",
3900         .type                   = RV1108,
3901         .grf_mux_offset         = 0x10,
3902         .pmu_mux_offset         = 0x0,
3903         .iomux_recalced         = rv1108_mux_recalced_data,
3904         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3905         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3906         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3907         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3908 };
3909
3910 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3911         PIN_BANK(0, 32, "gpio0"),
3912         PIN_BANK(1, 32, "gpio1"),
3913         PIN_BANK(2, 32, "gpio2"),
3914         PIN_BANK(3, 32, "gpio3"),
3915 };
3916
3917 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3918                 .pin_banks              = rk2928_pin_banks,
3919                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3920                 .label                  = "RK2928-GPIO",
3921                 .type                   = RK2928,
3922                 .grf_mux_offset         = 0xa8,
3923                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3924 };
3925
3926 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3927         PIN_BANK(0, 32, "gpio0"),
3928         PIN_BANK(1, 32, "gpio1"),
3929         PIN_BANK(2, 32, "gpio2"),
3930 };
3931
3932 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3933                 .pin_banks              = rk3036_pin_banks,
3934                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3935                 .label                  = "RK3036-GPIO",
3936                 .type                   = RK2928,
3937                 .grf_mux_offset         = 0xa8,
3938                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3939 };
3940
3941 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3942         PIN_BANK(0, 32, "gpio0"),
3943         PIN_BANK(1, 32, "gpio1"),
3944         PIN_BANK(2, 32, "gpio2"),
3945         PIN_BANK(3, 32, "gpio3"),
3946         PIN_BANK(4, 32, "gpio4"),
3947         PIN_BANK(6, 16, "gpio6"),
3948 };
3949
3950 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3951                 .pin_banks              = rk3066a_pin_banks,
3952                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3953                 .label                  = "RK3066a-GPIO",
3954                 .type                   = RK2928,
3955                 .grf_mux_offset         = 0xa8,
3956                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3957 };
3958
3959 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3960         PIN_BANK(0, 32, "gpio0"),
3961         PIN_BANK(1, 32, "gpio1"),
3962         PIN_BANK(2, 32, "gpio2"),
3963         PIN_BANK(3, 32, "gpio3"),
3964 };
3965
3966 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3967                 .pin_banks      = rk3066b_pin_banks,
3968                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3969                 .label          = "RK3066b-GPIO",
3970                 .type           = RK3066B,
3971                 .grf_mux_offset = 0x60,
3972 };
3973
3974 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3975         PIN_BANK(0, 32, "gpio0"),
3976         PIN_BANK(1, 32, "gpio1"),
3977         PIN_BANK(2, 32, "gpio2"),
3978         PIN_BANK(3, 32, "gpio3"),
3979 };
3980
3981 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3982                 .pin_banks              = rk3128_pin_banks,
3983                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3984                 .label                  = "RK3128-GPIO",
3985                 .type                   = RK3128,
3986                 .grf_mux_offset         = 0xa8,
3987                 .iomux_recalced         = rk3128_mux_recalced_data,
3988                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3989                 .iomux_routes           = rk3128_mux_route_data,
3990                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3991                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3992 };
3993
3994 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3995         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3996         PIN_BANK(1, 32, "gpio1"),
3997         PIN_BANK(2, 32, "gpio2"),
3998         PIN_BANK(3, 32, "gpio3"),
3999 };
4000
4001 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
4002                 .pin_banks              = rk3188_pin_banks,
4003                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
4004                 .label                  = "RK3188-GPIO",
4005                 .type                   = RK3188,
4006                 .grf_mux_offset         = 0x60,
4007                 .iomux_routes           = rk3188_mux_route_data,
4008                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
4009                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
4010 };
4011
4012 static struct rockchip_pin_bank rk3228_pin_banks[] = {
4013         PIN_BANK(0, 32, "gpio0"),
4014         PIN_BANK(1, 32, "gpio1"),
4015         PIN_BANK(2, 32, "gpio2"),
4016         PIN_BANK(3, 32, "gpio3"),
4017 };
4018
4019 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
4020                 .pin_banks              = rk3228_pin_banks,
4021                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
4022                 .label                  = "RK3228-GPIO",
4023                 .type                   = RK3288,
4024                 .grf_mux_offset         = 0x0,
4025                 .iomux_routes           = rk3228_mux_route_data,
4026                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
4027                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
4028                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
4029 };
4030
4031 static struct rockchip_pin_bank rk3288_pin_banks[] = {
4032         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
4033                                              IOMUX_SOURCE_PMU,
4034                                              IOMUX_SOURCE_PMU,
4035                                              IOMUX_UNROUTED
4036                             ),
4037         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4038                                              IOMUX_UNROUTED,
4039                                              IOMUX_UNROUTED,
4040                                              0
4041                             ),
4042         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4043         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4044         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4045                                              IOMUX_WIDTH_4BIT,
4046                                              0,
4047                                              0
4048                             ),
4049         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4050                                              0,
4051                                              0,
4052                                              IOMUX_UNROUTED
4053                             ),
4054         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4055         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4056                                              0,
4057                                              IOMUX_WIDTH_4BIT,
4058                                              IOMUX_UNROUTED
4059                             ),
4060         PIN_BANK(8, 16, "gpio8"),
4061 };
4062
4063 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
4064                 .pin_banks              = rk3288_pin_banks,
4065                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
4066                 .label                  = "RK3288-GPIO",
4067                 .type                   = RK3288,
4068                 .grf_mux_offset         = 0x0,
4069                 .pmu_mux_offset         = 0x84,
4070                 .iomux_routes           = rk3288_mux_route_data,
4071                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
4072                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
4073                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
4074 };
4075
4076 static struct rockchip_pin_bank rk3308_pin_banks[] = {
4077         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4078                                              IOMUX_WIDTH_2BIT,
4079                                              IOMUX_WIDTH_2BIT,
4080                                              IOMUX_WIDTH_2BIT),
4081         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4082                                              IOMUX_WIDTH_2BIT,
4083                                              IOMUX_WIDTH_2BIT,
4084                                              IOMUX_WIDTH_2BIT),
4085         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4086                                              IOMUX_WIDTH_2BIT,
4087                                              IOMUX_WIDTH_2BIT,
4088                                              IOMUX_WIDTH_2BIT),
4089         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4090                                              IOMUX_WIDTH_2BIT,
4091                                              IOMUX_WIDTH_2BIT,
4092                                              IOMUX_WIDTH_2BIT),
4093         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4094                                              IOMUX_WIDTH_2BIT,
4095                                              IOMUX_WIDTH_2BIT,
4096                                              IOMUX_WIDTH_2BIT),
4097 };
4098
4099 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
4100                 .pin_banks              = rk3308_pin_banks,
4101                 .nr_banks               = ARRAY_SIZE(rk3308_pin_banks),
4102                 .label                  = "RK3308-GPIO",
4103                 .type                   = RK3308,
4104                 .grf_mux_offset         = 0x0,
4105                 .iomux_recalced         = rk3308_mux_recalced_data,
4106                 .niomux_recalced        = ARRAY_SIZE(rk3308_mux_recalced_data),
4107                 .iomux_routes           = rk3308_mux_route_data,
4108                 .niomux_routes          = ARRAY_SIZE(rk3308_mux_route_data),
4109                 .pull_calc_reg          = rk3308_calc_pull_reg_and_bit,
4110                 .drv_calc_reg           = rk3308_calc_drv_reg_and_bit,
4111                 .schmitt_calc_reg       = rk3308_calc_schmitt_reg_and_bit,
4112 };
4113
4114 static struct rockchip_pin_bank rk3328_pin_banks[] = {
4115         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4116         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4117         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4118                              IOMUX_WIDTH_3BIT,
4119                              IOMUX_WIDTH_3BIT,
4120                              0),
4121         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4122                              IOMUX_WIDTH_3BIT,
4123                              IOMUX_WIDTH_3BIT,
4124                              0,
4125                              0),
4126 };
4127
4128 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4129                 .pin_banks              = rk3328_pin_banks,
4130                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
4131                 .label                  = "RK3328-GPIO",
4132                 .type                   = RK3288,
4133                 .grf_mux_offset         = 0x0,
4134                 .iomux_recalced         = rk3328_mux_recalced_data,
4135                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
4136                 .iomux_routes           = rk3328_mux_route_data,
4137                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
4138                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
4139                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
4140                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
4141 };
4142
4143 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4144         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4145                                              IOMUX_SOURCE_PMU,
4146                                              IOMUX_SOURCE_PMU,
4147                                              IOMUX_SOURCE_PMU
4148                             ),
4149         PIN_BANK(1, 32, "gpio1"),
4150         PIN_BANK(2, 32, "gpio2"),
4151         PIN_BANK(3, 32, "gpio3"),
4152 };
4153
4154 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4155                 .pin_banks              = rk3368_pin_banks,
4156                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
4157                 .label                  = "RK3368-GPIO",
4158                 .type                   = RK3368,
4159                 .grf_mux_offset         = 0x0,
4160                 .pmu_mux_offset         = 0x0,
4161                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
4162                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
4163 };
4164
4165 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4166         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4167                                                          IOMUX_SOURCE_PMU,
4168                                                          IOMUX_SOURCE_PMU,
4169                                                          IOMUX_SOURCE_PMU,
4170                                                          IOMUX_SOURCE_PMU,
4171                                                          DRV_TYPE_IO_1V8_ONLY,
4172                                                          DRV_TYPE_IO_1V8_ONLY,
4173                                                          DRV_TYPE_IO_DEFAULT,
4174                                                          DRV_TYPE_IO_DEFAULT,
4175                                                          0x80,
4176                                                          0x88,
4177                                                          -1,
4178                                                          -1,
4179                                                          PULL_TYPE_IO_1V8_ONLY,
4180                                                          PULL_TYPE_IO_1V8_ONLY,
4181                                                          PULL_TYPE_IO_DEFAULT,
4182                                                          PULL_TYPE_IO_DEFAULT
4183                                                         ),
4184         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4185                                         IOMUX_SOURCE_PMU,
4186                                         IOMUX_SOURCE_PMU,
4187                                         IOMUX_SOURCE_PMU,
4188                                         DRV_TYPE_IO_1V8_OR_3V0,
4189                                         DRV_TYPE_IO_1V8_OR_3V0,
4190                                         DRV_TYPE_IO_1V8_OR_3V0,
4191                                         DRV_TYPE_IO_1V8_OR_3V0,
4192                                         0xa0,
4193                                         0xa8,
4194                                         0xb0,
4195                                         0xb8
4196                                         ),
4197         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4198                                       DRV_TYPE_IO_1V8_OR_3V0,
4199                                       DRV_TYPE_IO_1V8_ONLY,
4200                                       DRV_TYPE_IO_1V8_ONLY,
4201                                       PULL_TYPE_IO_DEFAULT,
4202                                       PULL_TYPE_IO_DEFAULT,
4203                                       PULL_TYPE_IO_1V8_ONLY,
4204                                       PULL_TYPE_IO_1V8_ONLY
4205                                       ),
4206         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4207                            DRV_TYPE_IO_3V3_ONLY,
4208                            DRV_TYPE_IO_3V3_ONLY,
4209                            DRV_TYPE_IO_1V8_OR_3V0
4210                            ),
4211         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4212                            DRV_TYPE_IO_1V8_3V0_AUTO,
4213                            DRV_TYPE_IO_1V8_OR_3V0,
4214                            DRV_TYPE_IO_1V8_OR_3V0
4215                            ),
4216 };
4217
4218 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4219                 .pin_banks              = rk3399_pin_banks,
4220                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
4221                 .label                  = "RK3399-GPIO",
4222                 .type                   = RK3399,
4223                 .grf_mux_offset         = 0xe000,
4224                 .pmu_mux_offset         = 0x0,
4225                 .grf_drv_offset         = 0xe100,
4226                 .pmu_drv_offset         = 0x80,
4227                 .iomux_routes           = rk3399_mux_route_data,
4228                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
4229                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
4230                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
4231 };
4232
4233 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4234         { .compatible = "rockchip,px30-pinctrl",
4235                 .data = &px30_pin_ctrl },
4236         { .compatible = "rockchip,rv1108-pinctrl",
4237                 .data = &rv1108_pin_ctrl },
4238         { .compatible = "rockchip,rk2928-pinctrl",
4239                 .data = &rk2928_pin_ctrl },
4240         { .compatible = "rockchip,rk3036-pinctrl",
4241                 .data = &rk3036_pin_ctrl },
4242         { .compatible = "rockchip,rk3066a-pinctrl",
4243                 .data = &rk3066a_pin_ctrl },
4244         { .compatible = "rockchip,rk3066b-pinctrl",
4245                 .data = &rk3066b_pin_ctrl },
4246         { .compatible = "rockchip,rk3128-pinctrl",
4247                 .data = (void *)&rk3128_pin_ctrl },
4248         { .compatible = "rockchip,rk3188-pinctrl",
4249                 .data = &rk3188_pin_ctrl },
4250         { .compatible = "rockchip,rk3228-pinctrl",
4251                 .data = &rk3228_pin_ctrl },
4252         { .compatible = "rockchip,rk3288-pinctrl",
4253                 .data = &rk3288_pin_ctrl },
4254         { .compatible = "rockchip,rk3308-pinctrl",
4255                 .data = &rk3308_pin_ctrl },
4256         { .compatible = "rockchip,rk3328-pinctrl",
4257                 .data = &rk3328_pin_ctrl },
4258         { .compatible = "rockchip,rk3368-pinctrl",
4259                 .data = &rk3368_pin_ctrl },
4260         { .compatible = "rockchip,rk3399-pinctrl",
4261                 .data = &rk3399_pin_ctrl },
4262         {},
4263 };
4264
4265 static struct platform_driver rockchip_pinctrl_driver = {
4266         .probe          = rockchip_pinctrl_probe,
4267         .driver = {
4268                 .name   = "rockchip-pinctrl",
4269                 .pm = &rockchip_pinctrl_dev_pm_ops,
4270                 .of_match_table = rockchip_pinctrl_dt_match,
4271         },
4272 };
4273
4274 static int __init rockchip_pinctrl_drv_register(void)
4275 {
4276         return platform_driver_register(&rockchip_pinctrl_driver);
4277 }
4278 postcore_initcall(rockchip_pinctrl_drv_register);