drivers/pinctrl/pinctrl-ocelot.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Microsemi SoCs pinctrl driver
   4  *
   5  * Author: <alexandre.belloni@free-electrons.com>
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2017 Microsemi Corporation
   8  */
   9
  10 #include <linux/gpio/driver.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/pinctrl/pinctrl.h>
  17 #include <linux/pinctrl/pinmux.h>
  18 #include <linux/pinctrl/pinconf.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/slab.h>
  23
  24 #include "core.h"
  25 #include "pinconf.h"
  26 #include "pinmux.h"
  27
  28 #define ocelot_clrsetbits(addr, clear, set) \
  29         writel((readl(addr) & ~(clear)) | (set), (addr))
  30
  31 /* PINCONFIG bits (sparx5 only) */
  32 enum {
  33         PINCONF_BIAS,
  34         PINCONF_SCHMITT,
  35         PINCONF_DRIVE_STRENGTH,
  36 };
  37
  38 #define BIAS_PD_BIT BIT(4)
  39 #define BIAS_PU_BIT BIT(3)
  40 #define BIAS_BITS   (BIAS_PD_BIT|BIAS_PU_BIT)
  41 #define SCHMITT_BIT BIT(2)
  42 #define DRIVE_BITS  GENMASK(1, 0)
  43
  44 /* GPIO standard registers */
  45 #define OCELOT_GPIO_OUT_SET     0x0
  46 #define OCELOT_GPIO_OUT_CLR     0x4
  47 #define OCELOT_GPIO_OUT         0x8
  48 #define OCELOT_GPIO_IN          0xc
  49 #define OCELOT_GPIO_OE          0x10
  50 #define OCELOT_GPIO_INTR        0x14
  51 #define OCELOT_GPIO_INTR_ENA    0x18
  52 #define OCELOT_GPIO_INTR_IDENT  0x1c
  53 #define OCELOT_GPIO_ALT0        0x20
  54 #define OCELOT_GPIO_ALT1        0x24
  55 #define OCELOT_GPIO_SD_MAP      0x28
  56
  57 #define OCELOT_FUNC_PER_PIN     4
  58
  59 enum {
  60         FUNC_NONE,
  61         FUNC_GPIO,
  62         FUNC_IRQ0,
  63         FUNC_IRQ0_IN,
  64         FUNC_IRQ0_OUT,
  65         FUNC_IRQ1,
  66         FUNC_IRQ1_IN,
  67         FUNC_IRQ1_OUT,
  68         FUNC_EXT_IRQ,
  69         FUNC_MIIM,
  70         FUNC_PHY_LED,
  71         FUNC_PCI_WAKE,
  72         FUNC_MD,
  73         FUNC_PTP0,
  74         FUNC_PTP1,
  75         FUNC_PTP2,
  76         FUNC_PTP3,
  77         FUNC_PWM,
  78         FUNC_RECO_CLK,
  79         FUNC_SFP,
  80         FUNC_SG0,
  81         FUNC_SG1,
  82         FUNC_SG2,
  83         FUNC_SI,
  84         FUNC_SI2,
  85         FUNC_TACHO,
  86         FUNC_TWI,
  87         FUNC_TWI2,
  88         FUNC_TWI3,
  89         FUNC_TWI_SCL_M,
  90         FUNC_UART,
  91         FUNC_UART2,
  92         FUNC_UART3,
  93         FUNC_PLL_STAT,
  94         FUNC_EMMC,
  95         FUNC_REF_CLK,
  96         FUNC_RCVRD_CLK,
  97         FUNC_MAX
  98 };
  99
 100 static const char *const ocelot_function_names[] = {
 101         [FUNC_NONE]             = "none",
 102         [FUNC_GPIO]             = "gpio",
 103         [FUNC_IRQ0]             = "irq0",
 104         [FUNC_IRQ0_IN]          = "irq0_in",
 105         [FUNC_IRQ0_OUT]         = "irq0_out",
 106         [FUNC_IRQ1]             = "irq1",
 107         [FUNC_IRQ1_IN]          = "irq1_in",
 108         [FUNC_IRQ1_OUT]         = "irq1_out",
 109         [FUNC_EXT_IRQ]          = "ext_irq",
 110         [FUNC_MIIM]             = "miim",
 111         [FUNC_PHY_LED]          = "phy_led",
 112         [FUNC_PCI_WAKE]         = "pci_wake",
 113         [FUNC_MD]               = "md",
 114         [FUNC_PTP0]             = "ptp0",
 115         [FUNC_PTP1]             = "ptp1",
 116         [FUNC_PTP2]             = "ptp2",
 117         [FUNC_PTP3]             = "ptp3",
 118         [FUNC_PWM]              = "pwm",
 119         [FUNC_RECO_CLK]         = "reco_clk",
 120         [FUNC_SFP]              = "sfp",
 121         [FUNC_SG0]              = "sg0",
 122         [FUNC_SG1]              = "sg1",
 123         [FUNC_SG2]              = "sg2",
 124         [FUNC_SI]               = "si",
 125         [FUNC_SI2]              = "si2",
 126         [FUNC_TACHO]            = "tacho",
 127         [FUNC_TWI]              = "twi",
 128         [FUNC_TWI2]             = "twi2",
 129         [FUNC_TWI3]             = "twi3",
 130         [FUNC_TWI_SCL_M]        = "twi_scl_m",
 131         [FUNC_UART]             = "uart",
 132         [FUNC_UART2]            = "uart2",
 133         [FUNC_UART3]            = "uart3",
 134         [FUNC_PLL_STAT]         = "pll_stat",
 135         [FUNC_EMMC]             = "emmc",
 136         [FUNC_REF_CLK]          = "ref_clk",
 137         [FUNC_RCVRD_CLK]        = "rcvrd_clk",
 138 };
 139
 140 struct ocelot_pmx_func {
 141         const char **groups;
 142         unsigned int ngroups;
 143 };
 144
 145 struct ocelot_pin_caps {
 146         unsigned int pin;
 147         unsigned char functions[OCELOT_FUNC_PER_PIN];
 148 };
 149
 150 struct ocelot_pinctrl {
 151         struct device *dev;
 152         struct pinctrl_dev *pctl;
 153         struct gpio_chip gpio_chip;
 154         struct regmap *map;
 155         void __iomem *pincfg;
 156         struct pinctrl_desc *desc;
 157         struct ocelot_pmx_func func[FUNC_MAX];
 158         u8 stride;
 159 };
 160
 161 #define LUTON_P(p, f0, f1)                                              \
 162 static struct ocelot_pin_caps luton_pin_##p = {                         \
 163         .pin = p,                                                       \
 164         .functions = {                                                  \
 165                         FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE,     \
 166         },                                                              \
 167 }
 168
 169 LUTON_P(0,  SG0,       NONE);
 170 LUTON_P(1,  SG0,       NONE);
 171 LUTON_P(2,  SG0,       NONE);
 172 LUTON_P(3,  SG0,       NONE);
 173 LUTON_P(4,  TACHO,     NONE);
 174 LUTON_P(5,  TWI,       PHY_LED);
 175 LUTON_P(6,  TWI,       PHY_LED);
 176 LUTON_P(7,  NONE,      PHY_LED);
 177 LUTON_P(8,  EXT_IRQ,   PHY_LED);
 178 LUTON_P(9,  EXT_IRQ,   PHY_LED);
 179 LUTON_P(10, SFP,       PHY_LED);
 180 LUTON_P(11, SFP,       PHY_LED);
 181 LUTON_P(12, SFP,       PHY_LED);
 182 LUTON_P(13, SFP,       PHY_LED);
 183 LUTON_P(14, SI,        PHY_LED);
 184 LUTON_P(15, SI,        PHY_LED);
 185 LUTON_P(16, SI,        PHY_LED);
 186 LUTON_P(17, SFP,       PHY_LED);
 187 LUTON_P(18, SFP,       PHY_LED);
 188 LUTON_P(19, SFP,       PHY_LED);
 189 LUTON_P(20, SFP,       PHY_LED);
 190 LUTON_P(21, SFP,       PHY_LED);
 191 LUTON_P(22, SFP,       PHY_LED);
 192 LUTON_P(23, SFP,       PHY_LED);
 193 LUTON_P(24, SFP,       PHY_LED);
 194 LUTON_P(25, SFP,       PHY_LED);
 195 LUTON_P(26, SFP,       PHY_LED);
 196 LUTON_P(27, SFP,       PHY_LED);
 197 LUTON_P(28, SFP,       PHY_LED);
 198 LUTON_P(29, PWM,       NONE);
 199 LUTON_P(30, UART,      NONE);
 200 LUTON_P(31, UART,      NONE);
 201
 202 #define LUTON_PIN(n) {                                          \
 203         .number = n,                                            \
 204         .name = "GPIO_"#n,                                      \
 205         .drv_data = &luton_pin_##n                              \
 206 }
 207
 208 static const struct pinctrl_pin_desc luton_pins[] = {
 209         LUTON_PIN(0),
 210         LUTON_PIN(1),
 211         LUTON_PIN(2),
 212         LUTON_PIN(3),
 213         LUTON_PIN(4),
 214         LUTON_PIN(5),
 215         LUTON_PIN(6),
 216         LUTON_PIN(7),
 217         LUTON_PIN(8),
 218         LUTON_PIN(9),
 219         LUTON_PIN(10),
 220         LUTON_PIN(11),
 221         LUTON_PIN(12),
 222         LUTON_PIN(13),
 223         LUTON_PIN(14),
 224         LUTON_PIN(15),
 225         LUTON_PIN(16),
 226         LUTON_PIN(17),
 227         LUTON_PIN(18),
 228         LUTON_PIN(19),
 229         LUTON_PIN(20),
 230         LUTON_PIN(21),
 231         LUTON_PIN(22),
 232         LUTON_PIN(23),
 233         LUTON_PIN(24),
 234         LUTON_PIN(25),
 235         LUTON_PIN(26),
 236         LUTON_PIN(27),
 237         LUTON_PIN(28),
 238         LUTON_PIN(29),
 239         LUTON_PIN(30),
 240         LUTON_PIN(31),
 241 };
 242
 243 #define SERVAL_P(p, f0, f1, f2)                                         \
 244 static struct ocelot_pin_caps serval_pin_##p = {                        \
 245         .pin = p,                                                       \
 246         .functions = {                                                  \
 247                         FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2,     \
 248         },                                                              \
 249 }
 250
 251 SERVAL_P(0,  SG0,       NONE,      NONE);
 252 SERVAL_P(1,  SG0,       NONE,      NONE);
 253 SERVAL_P(2,  SG0,       NONE,      NONE);
 254 SERVAL_P(3,  SG0,       NONE,      NONE);
 255 SERVAL_P(4,  TACHO,     NONE,      NONE);
 256 SERVAL_P(5,  PWM,       NONE,      NONE);
 257 SERVAL_P(6,  TWI,       NONE,      NONE);
 258 SERVAL_P(7,  TWI,       NONE,      NONE);
 259 SERVAL_P(8,  SI,        NONE,      NONE);
 260 SERVAL_P(9,  SI,        MD,        NONE);
 261 SERVAL_P(10, SI,        MD,        NONE);
 262 SERVAL_P(11, SFP,       MD,        TWI_SCL_M);
 263 SERVAL_P(12, SFP,       MD,        TWI_SCL_M);
 264 SERVAL_P(13, SFP,       UART2,     TWI_SCL_M);
 265 SERVAL_P(14, SFP,       UART2,     TWI_SCL_M);
 266 SERVAL_P(15, SFP,       PTP0,      TWI_SCL_M);
 267 SERVAL_P(16, SFP,       PTP0,      TWI_SCL_M);
 268 SERVAL_P(17, SFP,       PCI_WAKE,  TWI_SCL_M);
 269 SERVAL_P(18, SFP,       NONE,      TWI_SCL_M);
 270 SERVAL_P(19, SFP,       NONE,      TWI_SCL_M);
 271 SERVAL_P(20, SFP,       NONE,      TWI_SCL_M);
 272 SERVAL_P(21, SFP,       NONE,      TWI_SCL_M);
 273 SERVAL_P(22, NONE,      NONE,      NONE);
 274 SERVAL_P(23, NONE,      NONE,      NONE);
 275 SERVAL_P(24, NONE,      NONE,      NONE);
 276 SERVAL_P(25, NONE,      NONE,      NONE);
 277 SERVAL_P(26, UART,      NONE,      NONE);
 278 SERVAL_P(27, UART,      NONE,      NONE);
 279 SERVAL_P(28, IRQ0,      NONE,      NONE);
 280 SERVAL_P(29, IRQ1,      NONE,      NONE);
 281 SERVAL_P(30, PTP0,      NONE,      NONE);
 282 SERVAL_P(31, PTP0,      NONE,      NONE);
 283
 284 #define SERVAL_PIN(n) {                                         \
 285         .number = n,                                            \
 286         .name = "GPIO_"#n,                                      \
 287         .drv_data = &serval_pin_##n                             \
 288 }
 289
 290 static const struct pinctrl_pin_desc serval_pins[] = {
 291         SERVAL_PIN(0),
 292         SERVAL_PIN(1),
 293         SERVAL_PIN(2),
 294         SERVAL_PIN(3),
 295         SERVAL_PIN(4),
 296         SERVAL_PIN(5),
 297         SERVAL_PIN(6),
 298         SERVAL_PIN(7),
 299         SERVAL_PIN(8),
 300         SERVAL_PIN(9),
 301         SERVAL_PIN(10),
 302         SERVAL_PIN(11),
 303         SERVAL_PIN(12),
 304         SERVAL_PIN(13),
 305         SERVAL_PIN(14),
 306         SERVAL_PIN(15),
 307         SERVAL_PIN(16),
 308         SERVAL_PIN(17),
 309         SERVAL_PIN(18),
 310         SERVAL_PIN(19),
 311         SERVAL_PIN(20),
 312         SERVAL_PIN(21),
 313         SERVAL_PIN(22),
 314         SERVAL_PIN(23),
 315         SERVAL_PIN(24),
 316         SERVAL_PIN(25),
 317         SERVAL_PIN(26),
 318         SERVAL_PIN(27),
 319         SERVAL_PIN(28),
 320         SERVAL_PIN(29),
 321         SERVAL_PIN(30),
 322         SERVAL_PIN(31),
 323 };
 324
 325 #define OCELOT_P(p, f0, f1, f2)                                         \
 326 static struct ocelot_pin_caps ocelot_pin_##p = {                        \
 327         .pin = p,                                                       \
 328         .functions = {                                                  \
 329                         FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2,     \
 330         },                                                              \
 331 }
 332
 333 OCELOT_P(0,  SG0,       NONE,      NONE);
 334 OCELOT_P(1,  SG0,       NONE,      NONE);
 335 OCELOT_P(2,  SG0,       NONE,      NONE);
 336 OCELOT_P(3,  SG0,       NONE,      NONE);
 337 OCELOT_P(4,  IRQ0_IN,   IRQ0_OUT,  TWI_SCL_M);
 338 OCELOT_P(5,  IRQ1_IN,   IRQ1_OUT,  PCI_WAKE);
 339 OCELOT_P(6,  UART,      TWI_SCL_M, NONE);
 340 OCELOT_P(7,  UART,      TWI_SCL_M, NONE);
 341 OCELOT_P(8,  SI,        TWI_SCL_M, IRQ0_OUT);
 342 OCELOT_P(9,  SI,        TWI_SCL_M, IRQ1_OUT);
 343 OCELOT_P(10, PTP2,      TWI_SCL_M, SFP);
 344 OCELOT_P(11, PTP3,      TWI_SCL_M, SFP);
 345 OCELOT_P(12, UART2,     TWI_SCL_M, SFP);
 346 OCELOT_P(13, UART2,     TWI_SCL_M, SFP);
 347 OCELOT_P(14, MIIM,      TWI_SCL_M, SFP);
 348 OCELOT_P(15, MIIM,      TWI_SCL_M, SFP);
 349 OCELOT_P(16, TWI,       NONE,      SI);
 350 OCELOT_P(17, TWI,       TWI_SCL_M, SI);
 351 OCELOT_P(18, PTP0,      TWI_SCL_M, NONE);
 352 OCELOT_P(19, PTP1,      TWI_SCL_M, NONE);
 353 OCELOT_P(20, RECO_CLK,  TACHO,     TWI_SCL_M);
 354 OCELOT_P(21, RECO_CLK,  PWM,       TWI_SCL_M);
 355
 356 #define OCELOT_PIN(n) {                                         \
 357         .number = n,                                            \
 358         .name = "GPIO_"#n,                                      \
 359         .drv_data = &ocelot_pin_##n                             \
 360 }
 361
 362 static const struct pinctrl_pin_desc ocelot_pins[] = {
 363         OCELOT_PIN(0),
 364         OCELOT_PIN(1),
 365         OCELOT_PIN(2),
 366         OCELOT_PIN(3),
 367         OCELOT_PIN(4),
 368         OCELOT_PIN(5),
 369         OCELOT_PIN(6),
 370         OCELOT_PIN(7),
 371         OCELOT_PIN(8),
 372         OCELOT_PIN(9),
 373         OCELOT_PIN(10),
 374         OCELOT_PIN(11),
 375         OCELOT_PIN(12),
 376         OCELOT_PIN(13),
 377         OCELOT_PIN(14),
 378         OCELOT_PIN(15),
 379         OCELOT_PIN(16),
 380         OCELOT_PIN(17),
 381         OCELOT_PIN(18),
 382         OCELOT_PIN(19),
 383         OCELOT_PIN(20),
 384         OCELOT_PIN(21),
 385 };
 386
 387 #define JAGUAR2_P(p, f0, f1)                                            \
 388 static struct ocelot_pin_caps jaguar2_pin_##p = {                       \
 389         .pin = p,                                                       \
 390         .functions = {                                                  \
 391                         FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE      \
 392         },                                                              \
 393 }
 394
 395 JAGUAR2_P(0,  SG0,       NONE);
 396 JAGUAR2_P(1,  SG0,       NONE);
 397 JAGUAR2_P(2,  SG0,       NONE);
 398 JAGUAR2_P(3,  SG0,       NONE);
 399 JAGUAR2_P(4,  SG1,       NONE);
 400 JAGUAR2_P(5,  SG1,       NONE);
 401 JAGUAR2_P(6,  IRQ0_IN,   IRQ0_OUT);
 402 JAGUAR2_P(7,  IRQ1_IN,   IRQ1_OUT);
 403 JAGUAR2_P(8,  PTP0,      NONE);
 404 JAGUAR2_P(9,  PTP1,      NONE);
 405 JAGUAR2_P(10, UART,      NONE);
 406 JAGUAR2_P(11, UART,      NONE);
 407 JAGUAR2_P(12, SG1,       NONE);
 408 JAGUAR2_P(13, SG1,       NONE);
 409 JAGUAR2_P(14, TWI,       TWI_SCL_M);
 410 JAGUAR2_P(15, TWI,       NONE);
 411 JAGUAR2_P(16, SI,        TWI_SCL_M);
 412 JAGUAR2_P(17, SI,        TWI_SCL_M);
 413 JAGUAR2_P(18, SI,        TWI_SCL_M);
 414 JAGUAR2_P(19, PCI_WAKE,  NONE);
 415 JAGUAR2_P(20, IRQ0_OUT,  TWI_SCL_M);
 416 JAGUAR2_P(21, IRQ1_OUT,  TWI_SCL_M);
 417 JAGUAR2_P(22, TACHO,     NONE);
 418 JAGUAR2_P(23, PWM,       NONE);
 419 JAGUAR2_P(24, UART2,     NONE);
 420 JAGUAR2_P(25, UART2,     SI);
 421 JAGUAR2_P(26, PTP2,      SI);
 422 JAGUAR2_P(27, PTP3,      SI);
 423 JAGUAR2_P(28, TWI2,      SI);
 424 JAGUAR2_P(29, TWI2,      SI);
 425 JAGUAR2_P(30, SG2,       SI);
 426 JAGUAR2_P(31, SG2,       SI);
 427 JAGUAR2_P(32, SG2,       SI);
 428 JAGUAR2_P(33, SG2,       SI);
 429 JAGUAR2_P(34, NONE,      TWI_SCL_M);
 430 JAGUAR2_P(35, NONE,      TWI_SCL_M);
 431 JAGUAR2_P(36, NONE,      TWI_SCL_M);
 432 JAGUAR2_P(37, NONE,      TWI_SCL_M);
 433 JAGUAR2_P(38, NONE,      TWI_SCL_M);
 434 JAGUAR2_P(39, NONE,      TWI_SCL_M);
 435 JAGUAR2_P(40, NONE,      TWI_SCL_M);
 436 JAGUAR2_P(41, NONE,      TWI_SCL_M);
 437 JAGUAR2_P(42, NONE,      TWI_SCL_M);
 438 JAGUAR2_P(43, NONE,      TWI_SCL_M);
 439 JAGUAR2_P(44, NONE,      SFP);
 440 JAGUAR2_P(45, NONE,      SFP);
 441 JAGUAR2_P(46, NONE,      SFP);
 442 JAGUAR2_P(47, NONE,      SFP);
 443 JAGUAR2_P(48, SFP,       NONE);
 444 JAGUAR2_P(49, SFP,       SI);
 445 JAGUAR2_P(50, SFP,       SI);
 446 JAGUAR2_P(51, SFP,       SI);
 447 JAGUAR2_P(52, SFP,       NONE);
 448 JAGUAR2_P(53, SFP,       NONE);
 449 JAGUAR2_P(54, SFP,       NONE);
 450 JAGUAR2_P(55, SFP,       NONE);
 451 JAGUAR2_P(56, MIIM,      SFP);
 452 JAGUAR2_P(57, MIIM,      SFP);
 453 JAGUAR2_P(58, MIIM,      SFP);
 454 JAGUAR2_P(59, MIIM,      SFP);
 455 JAGUAR2_P(60, NONE,      NONE);
 456 JAGUAR2_P(61, NONE,      NONE);
 457 JAGUAR2_P(62, NONE,      NONE);
 458 JAGUAR2_P(63, NONE,      NONE);
 459
 460 #define JAGUAR2_PIN(n) {                                        \
 461         .number = n,                                            \
 462         .name = "GPIO_"#n,                                      \
 463         .drv_data = &jaguar2_pin_##n                            \
 464 }
 465
 466 static const struct pinctrl_pin_desc jaguar2_pins[] = {
 467         JAGUAR2_PIN(0),
 468         JAGUAR2_PIN(1),
 469         JAGUAR2_PIN(2),
 470         JAGUAR2_PIN(3),
 471         JAGUAR2_PIN(4),
 472         JAGUAR2_PIN(5),
 473         JAGUAR2_PIN(6),
 474         JAGUAR2_PIN(7),
 475         JAGUAR2_PIN(8),
 476         JAGUAR2_PIN(9),
 477         JAGUAR2_PIN(10),
 478         JAGUAR2_PIN(11),
 479         JAGUAR2_PIN(12),
 480         JAGUAR2_PIN(13),
 481         JAGUAR2_PIN(14),
 482         JAGUAR2_PIN(15),
 483         JAGUAR2_PIN(16),
 484         JAGUAR2_PIN(17),
 485         JAGUAR2_PIN(18),
 486         JAGUAR2_PIN(19),
 487         JAGUAR2_PIN(20),
 488         JAGUAR2_PIN(21),
 489         JAGUAR2_PIN(22),
 490         JAGUAR2_PIN(23),
 491         JAGUAR2_PIN(24),
 492         JAGUAR2_PIN(25),
 493         JAGUAR2_PIN(26),
 494         JAGUAR2_PIN(27),
 495         JAGUAR2_PIN(28),
 496         JAGUAR2_PIN(29),
 497         JAGUAR2_PIN(30),
 498         JAGUAR2_PIN(31),
 499         JAGUAR2_PIN(32),
 500         JAGUAR2_PIN(33),
 501         JAGUAR2_PIN(34),
 502         JAGUAR2_PIN(35),
 503         JAGUAR2_PIN(36),
 504         JAGUAR2_PIN(37),
 505         JAGUAR2_PIN(38),
 506         JAGUAR2_PIN(39),
 507         JAGUAR2_PIN(40),
 508         JAGUAR2_PIN(41),
 509         JAGUAR2_PIN(42),
 510         JAGUAR2_PIN(43),
 511         JAGUAR2_PIN(44),
 512         JAGUAR2_PIN(45),
 513         JAGUAR2_PIN(46),
 514         JAGUAR2_PIN(47),
 515         JAGUAR2_PIN(48),
 516         JAGUAR2_PIN(49),
 517         JAGUAR2_PIN(50),
 518         JAGUAR2_PIN(51),
 519         JAGUAR2_PIN(52),
 520         JAGUAR2_PIN(53),
 521         JAGUAR2_PIN(54),
 522         JAGUAR2_PIN(55),
 523         JAGUAR2_PIN(56),
 524         JAGUAR2_PIN(57),
 525         JAGUAR2_PIN(58),
 526         JAGUAR2_PIN(59),
 527         JAGUAR2_PIN(60),
 528         JAGUAR2_PIN(61),
 529         JAGUAR2_PIN(62),
 530         JAGUAR2_PIN(63),
 531 };
 532
 533 #define SPARX5_P(p, f0, f1, f2)                                 \
 534 static struct ocelot_pin_caps sparx5_pin_##p = {                        \
 535         .pin = p,                                                       \
 536         .functions = {                                                  \
 537                 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2              \
 538         },                                                              \
 539 }
 540
 541 SPARX5_P(0,  SG0,       PLL_STAT,  NONE);
 542 SPARX5_P(1,  SG0,       NONE,      NONE);
 543 SPARX5_P(2,  SG0,       NONE,      NONE);
 544 SPARX5_P(3,  SG0,       NONE,      NONE);
 545 SPARX5_P(4,  SG1,       NONE,      NONE);
 546 SPARX5_P(5,  SG1,       NONE,      NONE);
 547 SPARX5_P(6,  IRQ0_IN,   IRQ0_OUT,  SFP);
 548 SPARX5_P(7,  IRQ1_IN,   IRQ1_OUT,  SFP);
 549 SPARX5_P(8,  PTP0,      NONE,      SFP);
 550 SPARX5_P(9,  PTP1,      SFP,       TWI_SCL_M);
 551 SPARX5_P(10, UART,      NONE,      NONE);
 552 SPARX5_P(11, UART,      NONE,      NONE);
 553 SPARX5_P(12, SG1,       NONE,      NONE);
 554 SPARX5_P(13, SG1,       NONE,      NONE);
 555 SPARX5_P(14, TWI,       TWI_SCL_M, NONE);
 556 SPARX5_P(15, TWI,       NONE,      NONE);
 557 SPARX5_P(16, SI,        TWI_SCL_M, SFP);
 558 SPARX5_P(17, SI,        TWI_SCL_M, SFP);
 559 SPARX5_P(18, SI,        TWI_SCL_M, SFP);
 560 SPARX5_P(19, PCI_WAKE,  TWI_SCL_M, SFP);
 561 SPARX5_P(20, IRQ0_OUT,  TWI_SCL_M, SFP);
 562 SPARX5_P(21, IRQ1_OUT,  TACHO,     SFP);
 563 SPARX5_P(22, TACHO,     IRQ0_OUT,  TWI_SCL_M);
 564 SPARX5_P(23, PWM,       UART3,     TWI_SCL_M);
 565 SPARX5_P(24, PTP2,      UART3,     TWI_SCL_M);
 566 SPARX5_P(25, PTP3,      SI,        TWI_SCL_M);
 567 SPARX5_P(26, UART2,     SI,        TWI_SCL_M);
 568 SPARX5_P(27, UART2,     SI,        TWI_SCL_M);
 569 SPARX5_P(28, TWI2,      SI,        SFP);
 570 SPARX5_P(29, TWI2,      SI,        SFP);
 571 SPARX5_P(30, SG2,       SI,        PWM);
 572 SPARX5_P(31, SG2,       SI,        TWI_SCL_M);
 573 SPARX5_P(32, SG2,       SI,        TWI_SCL_M);
 574 SPARX5_P(33, SG2,       SI,        SFP);
 575 SPARX5_P(34, NONE,      TWI_SCL_M, EMMC);
 576 SPARX5_P(35, SFP,       TWI_SCL_M, EMMC);
 577 SPARX5_P(36, SFP,       TWI_SCL_M, EMMC);
 578 SPARX5_P(37, SFP,       NONE,      EMMC);
 579 SPARX5_P(38, NONE,      TWI_SCL_M, EMMC);
 580 SPARX5_P(39, SI2,       TWI_SCL_M, EMMC);
 581 SPARX5_P(40, SI2,       TWI_SCL_M, EMMC);
 582 SPARX5_P(41, SI2,       TWI_SCL_M, EMMC);
 583 SPARX5_P(42, SI2,       TWI_SCL_M, EMMC);
 584 SPARX5_P(43, SI2,       TWI_SCL_M, EMMC);
 585 SPARX5_P(44, SI,        SFP,       EMMC);
 586 SPARX5_P(45, SI,        SFP,       EMMC);
 587 SPARX5_P(46, NONE,      SFP,       EMMC);
 588 SPARX5_P(47, NONE,      SFP,       EMMC);
 589 SPARX5_P(48, TWI3,      SI,        SFP);
 590 SPARX5_P(49, TWI3,      NONE,      SFP);
 591 SPARX5_P(50, SFP,       NONE,      TWI_SCL_M);
 592 SPARX5_P(51, SFP,       SI,        TWI_SCL_M);
 593 SPARX5_P(52, SFP,       MIIM,      TWI_SCL_M);
 594 SPARX5_P(53, SFP,       MIIM,      TWI_SCL_M);
 595 SPARX5_P(54, SFP,       PTP2,      TWI_SCL_M);
 596 SPARX5_P(55, SFP,       PTP3,      PCI_WAKE);
 597 SPARX5_P(56, MIIM,      SFP,       TWI_SCL_M);
 598 SPARX5_P(57, MIIM,      SFP,       TWI_SCL_M);
 599 SPARX5_P(58, MIIM,      SFP,       TWI_SCL_M);
 600 SPARX5_P(59, MIIM,      SFP,       NONE);
 601 SPARX5_P(60, RECO_CLK,  NONE,      NONE);
 602 SPARX5_P(61, RECO_CLK,  NONE,      NONE);
 603 SPARX5_P(62, RECO_CLK,  PLL_STAT,  NONE);
 604 SPARX5_P(63, RECO_CLK,  NONE,      NONE);
 605
 606 #define SPARX5_PIN(n) {                                 \
 607         .number = n,                                            \
 608         .name = "GPIO_"#n,                                      \
 609         .drv_data = &sparx5_pin_##n                             \
 610 }
 611
 612 static const struct pinctrl_pin_desc sparx5_pins[] = {
 613         SPARX5_PIN(0),
 614         SPARX5_PIN(1),
 615         SPARX5_PIN(2),
 616         SPARX5_PIN(3),
 617         SPARX5_PIN(4),
 618         SPARX5_PIN(5),
 619         SPARX5_PIN(6),
 620         SPARX5_PIN(7),
 621         SPARX5_PIN(8),
 622         SPARX5_PIN(9),
 623         SPARX5_PIN(10),
 624         SPARX5_PIN(11),
 625         SPARX5_PIN(12),
 626         SPARX5_PIN(13),
 627         SPARX5_PIN(14),
 628         SPARX5_PIN(15),
 629         SPARX5_PIN(16),
 630         SPARX5_PIN(17),
 631         SPARX5_PIN(18),
 632         SPARX5_PIN(19),
 633         SPARX5_PIN(20),
 634         SPARX5_PIN(21),
 635         SPARX5_PIN(22),
 636         SPARX5_PIN(23),
 637         SPARX5_PIN(24),
 638         SPARX5_PIN(25),
 639         SPARX5_PIN(26),
 640         SPARX5_PIN(27),
 641         SPARX5_PIN(28),
 642         SPARX5_PIN(29),
 643         SPARX5_PIN(30),
 644         SPARX5_PIN(31),
 645         SPARX5_PIN(32),
 646         SPARX5_PIN(33),
 647         SPARX5_PIN(34),
 648         SPARX5_PIN(35),
 649         SPARX5_PIN(36),
 650         SPARX5_PIN(37),
 651         SPARX5_PIN(38),
 652         SPARX5_PIN(39),
 653         SPARX5_PIN(40),
 654         SPARX5_PIN(41),
 655         SPARX5_PIN(42),
 656         SPARX5_PIN(43),
 657         SPARX5_PIN(44),
 658         SPARX5_PIN(45),
 659         SPARX5_PIN(46),
 660         SPARX5_PIN(47),
 661         SPARX5_PIN(48),
 662         SPARX5_PIN(49),
 663         SPARX5_PIN(50),
 664         SPARX5_PIN(51),
 665         SPARX5_PIN(52),
 666         SPARX5_PIN(53),
 667         SPARX5_PIN(54),
 668         SPARX5_PIN(55),
 669         SPARX5_PIN(56),
 670         SPARX5_PIN(57),
 671         SPARX5_PIN(58),
 672         SPARX5_PIN(59),
 673         SPARX5_PIN(60),
 674         SPARX5_PIN(61),
 675         SPARX5_PIN(62),
 676         SPARX5_PIN(63),
 677 };
 678
 679 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
 680 {
 681         return ARRAY_SIZE(ocelot_function_names);
 682 }
 683
 684 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
 685                                             unsigned int function)
 686 {
 687         return ocelot_function_names[function];
 688 }
 689
 690 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
 691                                       unsigned int function,
 692                                       const char *const **groups,
 693                                       unsigned *const num_groups)
 694 {
 695         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 696
 697         *groups  = info->func[function].groups;
 698         *num_groups = info->func[function].ngroups;
 699
 700         return 0;
 701 }
 702
 703 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
 704                                    unsigned int pin, unsigned int function)
 705 {
 706         struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
 707         int i;
 708
 709         for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
 710                 if (function == p->functions[i])
 711                         return i;
 712         }
 713
 714         return -1;
 715 }
 716
 717 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
 718
 719 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
 720                                  unsigned int selector, unsigned int group)
 721 {
 722         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 723         struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
 724         unsigned int p = pin->pin % 32;
 725         int f;
 726
 727         f = ocelot_pin_function_idx(info, group, selector);
 728         if (f < 0)
 729                 return -EINVAL;
 730
 731         /*
 732          * f is encoded on two bits.
 733          * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
 734          * ALT[1]
 735          * This is racy because both registers can't be updated at the same time
 736          * but it doesn't matter much for now.
 737          * Note: ALT0/ALT1 are organized specially for 64 gpio targets
 738          */
 739         regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
 740                            BIT(p), f << p);
 741         regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
 742                            BIT(p), f << (p - 1));
 743
 744         return 0;
 745 }
 746
 747 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
 748
 749 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
 750                                      struct pinctrl_gpio_range *range,
 751                                      unsigned int pin, bool input)
 752 {
 753         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 754         unsigned int p = pin % 32;
 755
 756         regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
 757                            input ? 0 : BIT(p));
 758
 759         return 0;
 760 }
 761
 762 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
 763                                       struct pinctrl_gpio_range *range,
 764                                       unsigned int offset)
 765 {
 766         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 767         unsigned int p = offset % 32;
 768
 769         regmap_update_bits(info->map, REG_ALT(0, info, offset),
 770                            BIT(p), 0);
 771         regmap_update_bits(info->map, REG_ALT(1, info, offset),
 772                            BIT(p), 0);
 773
 774         return 0;
 775 }
 776
 777 static const struct pinmux_ops ocelot_pmx_ops = {
 778         .get_functions_count = ocelot_get_functions_count,
 779         .get_function_name = ocelot_get_function_name,
 780         .get_function_groups = ocelot_get_function_groups,
 781         .set_mux = ocelot_pinmux_set_mux,
 782         .gpio_set_direction = ocelot_gpio_set_direction,
 783         .gpio_request_enable = ocelot_gpio_request_enable,
 784 };
 785
 786 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
 787 {
 788         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 789
 790         return info->desc->npins;
 791 }
 792
 793 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
 794                                               unsigned int group)
 795 {
 796         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 797
 798         return info->desc->pins[group].name;
 799 }
 800
 801 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
 802                                       unsigned int group,
 803                                       const unsigned int **pins,
 804                                       unsigned int *num_pins)
 805 {
 806         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 807
 808         *pins = &info->desc->pins[group].number;
 809         *num_pins = 1;
 810
 811         return 0;
 812 }
 813
 814 static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
 815                                unsigned int pin,
 816                                unsigned int reg,
 817                                int *val)
 818 {
 819         int ret = -EOPNOTSUPP;
 820
 821         if (info->pincfg) {
 822                 u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
 823
 824                 ret = 0;
 825                 switch (reg) {
 826                 case PINCONF_BIAS:
 827                         *val = regcfg & BIAS_BITS;
 828                         break;
 829
 830                 case PINCONF_SCHMITT:
 831                         *val = regcfg & SCHMITT_BIT;
 832                         break;
 833
 834                 case PINCONF_DRIVE_STRENGTH:
 835                         *val = regcfg & DRIVE_BITS;
 836                         break;
 837
 838                 default:
 839                         ret = -EOPNOTSUPP;
 840                         break;
 841                 }
 842         }
 843         return ret;
 844 }
 845
 846 static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
 847                                unsigned int pin,
 848                                unsigned int reg,
 849                                int val)
 850 {
 851         int ret = -EOPNOTSUPP;
 852
 853         if (info->pincfg) {
 854                 void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
 855
 856                 ret = 0;
 857                 switch (reg) {
 858                 case PINCONF_BIAS:
 859                         ocelot_clrsetbits(regaddr, BIAS_BITS, val);
 860                         break;
 861
 862                 case PINCONF_SCHMITT:
 863                         ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
 864                         break;
 865
 866                 case PINCONF_DRIVE_STRENGTH:
 867                         if (val <= 3)
 868                                 ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
 869                         else
 870                                 ret = -EINVAL;
 871                         break;
 872
 873                 default:
 874                         ret = -EOPNOTSUPP;
 875                         break;
 876                 }
 877         }
 878         return ret;
 879 }
 880
 881 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
 882                               unsigned int pin, unsigned long *config)
 883 {
 884         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 885         u32 param = pinconf_to_config_param(*config);
 886         int val, err;
 887
 888         switch (param) {
 889         case PIN_CONFIG_BIAS_DISABLE:
 890         case PIN_CONFIG_BIAS_PULL_UP:
 891         case PIN_CONFIG_BIAS_PULL_DOWN:
 892                 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
 893                 if (err)
 894                         return err;
 895                 if (param == PIN_CONFIG_BIAS_DISABLE)
 896                         val = (val == 0);
 897                 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
 898                         val = (val & BIAS_PD_BIT ? true : false);
 899                 else    /* PIN_CONFIG_BIAS_PULL_UP */
 900                         val = (val & BIAS_PU_BIT ? true : false);
 901                 break;
 902
 903         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 904                 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
 905                 if (err)
 906                         return err;
 907
 908                 val = (val & SCHMITT_BIT ? true : false);
 909                 break;
 910
 911         case PIN_CONFIG_DRIVE_STRENGTH:
 912                 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
 913                                           &val);
 914                 if (err)
 915                         return err;
 916                 break;
 917
 918         case PIN_CONFIG_OUTPUT:
 919                 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
 920                                   &val);
 921                 if (err)
 922                         return err;
 923                 val = !!(val & BIT(pin % 32));
 924                 break;
 925
 926         case PIN_CONFIG_INPUT_ENABLE:
 927         case PIN_CONFIG_OUTPUT_ENABLE:
 928                 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
 929                                   &val);
 930                 if (err)
 931                         return err;
 932                 val = val & BIT(pin % 32);
 933                 if (param == PIN_CONFIG_OUTPUT_ENABLE)
 934                         val = !!val;
 935                 else
 936                         val = !val;
 937                 break;
 938
 939         default:
 940                 return -EOPNOTSUPP;
 941         }
 942
 943         *config = pinconf_to_config_packed(param, val);
 944
 945         return 0;
 946 }
 947
 948 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 949                               unsigned long *configs, unsigned int num_configs)
 950 {
 951         struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 952         u32 param, arg, p;
 953         int cfg, err = 0;
 954
 955         for (cfg = 0; cfg < num_configs; cfg++) {
 956                 param = pinconf_to_config_param(configs[cfg]);
 957                 arg = pinconf_to_config_argument(configs[cfg]);
 958
 959                 switch (param) {
 960                 case PIN_CONFIG_BIAS_DISABLE:
 961                 case PIN_CONFIG_BIAS_PULL_UP:
 962                 case PIN_CONFIG_BIAS_PULL_DOWN:
 963                         arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
 964                         (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
 965                         BIAS_PD_BIT;
 966
 967                         err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
 968                         if (err)
 969                                 goto err;
 970
 971                         break;
 972
 973                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 974                         arg = arg ? SCHMITT_BIT : 0;
 975                         err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
 976                                                   arg);
 977                         if (err)
 978                                 goto err;
 979
 980                         break;
 981
 982                 case PIN_CONFIG_DRIVE_STRENGTH:
 983                         err = ocelot_hw_set_value(info, pin,
 984                                                   PINCONF_DRIVE_STRENGTH,
 985                                                   arg);
 986                         if (err)
 987                                 goto err;
 988
 989                         break;
 990
 991                 case PIN_CONFIG_OUTPUT_ENABLE:
 992                 case PIN_CONFIG_INPUT_ENABLE:
 993                 case PIN_CONFIG_OUTPUT:
 994                         p = pin % 32;
 995                         if (arg)
 996                                 regmap_write(info->map,
 997                                              REG(OCELOT_GPIO_OUT_SET, info,
 998                                                  pin),
 999                                              BIT(p));
1000                         else
1001                                 regmap_write(info->map,
1002                                              REG(OCELOT_GPIO_OUT_CLR, info,
1003                                                  pin),
1004                                              BIT(p));
1005                         regmap_update_bits(info->map,
1006                                            REG(OCELOT_GPIO_OE, info, pin),
1007                                            BIT(p),
1008                                            param == PIN_CONFIG_INPUT_ENABLE ?
1009                                            0 : BIT(p));
1010                         break;
1011
1012                 default:
1013                         err = -EOPNOTSUPP;
1014                 }
1015         }
1016 err:
1017         return err;
1018 }
1019
1020 static const struct pinconf_ops ocelot_confops = {
1021         .is_generic = true,
1022         .pin_config_get = ocelot_pinconf_get,
1023         .pin_config_set = ocelot_pinconf_set,
1024         .pin_config_config_dbg_show = pinconf_generic_dump_config,
1025 };
1026
1027 static const struct pinctrl_ops ocelot_pctl_ops = {
1028         .get_groups_count = ocelot_pctl_get_groups_count,
1029         .get_group_name = ocelot_pctl_get_group_name,
1030         .get_group_pins = ocelot_pctl_get_group_pins,
1031         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1032         .dt_free_map = pinconf_generic_dt_free_map,
1033 };
1034
1035 static struct pinctrl_desc luton_desc = {
1036         .name = "luton-pinctrl",
1037         .pins = luton_pins,
1038         .npins = ARRAY_SIZE(luton_pins),
1039         .pctlops = &ocelot_pctl_ops,
1040         .pmxops = &ocelot_pmx_ops,
1041         .owner = THIS_MODULE,
1042 };
1043
1044 static struct pinctrl_desc serval_desc = {
1045         .name = "serval-pinctrl",
1046         .pins = serval_pins,
1047         .npins = ARRAY_SIZE(serval_pins),
1048         .pctlops = &ocelot_pctl_ops,
1049         .pmxops = &ocelot_pmx_ops,
1050         .owner = THIS_MODULE,
1051 };
1052
1053 static struct pinctrl_desc ocelot_desc = {
1054         .name = "ocelot-pinctrl",
1055         .pins = ocelot_pins,
1056         .npins = ARRAY_SIZE(ocelot_pins),
1057         .pctlops = &ocelot_pctl_ops,
1058         .pmxops = &ocelot_pmx_ops,
1059         .owner = THIS_MODULE,
1060 };
1061
1062 static struct pinctrl_desc jaguar2_desc = {
1063         .name = "jaguar2-pinctrl",
1064         .pins = jaguar2_pins,
1065         .npins = ARRAY_SIZE(jaguar2_pins),
1066         .pctlops = &ocelot_pctl_ops,
1067         .pmxops = &ocelot_pmx_ops,
1068         .owner = THIS_MODULE,
1069 };
1070
1071 static struct pinctrl_desc sparx5_desc = {
1072         .name = "sparx5-pinctrl",
1073         .pins = sparx5_pins,
1074         .npins = ARRAY_SIZE(sparx5_pins),
1075         .pctlops = &ocelot_pctl_ops,
1076         .pmxops = &ocelot_pmx_ops,
1077         .confops = &ocelot_confops,
1078         .owner = THIS_MODULE,
1079 };
1080
1081 static int ocelot_create_group_func_map(struct device *dev,
1082                                         struct ocelot_pinctrl *info)
1083 {
1084         int f, npins, i;
1085         u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
1086
1087         if (!pins)
1088                 return -ENOMEM;
1089
1090         for (f = 0; f < FUNC_MAX; f++) {
1091                 for (npins = 0, i = 0; i < info->desc->npins; i++) {
1092                         if (ocelot_pin_function_idx(info, i, f) >= 0)
1093                                 pins[npins++] = i;
1094                 }
1095
1096                 if (!npins)
1097                         continue;
1098
1099                 info->func[f].ngroups = npins;
1100                 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
1101                                                     GFP_KERNEL);
1102                 if (!info->func[f].groups) {
1103                         kfree(pins);
1104                         return -ENOMEM;
1105                 }
1106
1107                 for (i = 0; i < npins; i++)
1108                         info->func[f].groups[i] =
1109                                 info->desc->pins[pins[i]].name;
1110         }
1111
1112         kfree(pins);
1113
1114         return 0;
1115 }
1116
1117 static int ocelot_pinctrl_register(struct platform_device *pdev,
1118                                    struct ocelot_pinctrl *info)
1119 {
1120         int ret;
1121
1122         ret = ocelot_create_group_func_map(&pdev->dev, info);
1123         if (ret) {
1124                 dev_err(&pdev->dev, "Unable to create group func map.\n");
1125                 return ret;
1126         }
1127
1128         info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
1129         if (IS_ERR(info->pctl)) {
1130                 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1131                 return PTR_ERR(info->pctl);
1132         }
1133
1134         return 0;
1135 }
1136
1137 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
1138 {
1139         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1140         unsigned int val;
1141
1142         regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
1143
1144         return !!(val & BIT(offset % 32));
1145 }
1146
1147 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
1148                             int value)
1149 {
1150         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1151
1152         if (value)
1153                 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1154                              BIT(offset % 32));
1155         else
1156                 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1157                              BIT(offset % 32));
1158 }
1159
1160 static int ocelot_gpio_get_direction(struct gpio_chip *chip,
1161                                      unsigned int offset)
1162 {
1163         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1164         unsigned int val;
1165
1166         regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
1167
1168         if (val & BIT(offset % 32))
1169                 return GPIO_LINE_DIRECTION_OUT;
1170
1171         return GPIO_LINE_DIRECTION_IN;
1172 }
1173
1174 static int ocelot_gpio_direction_input(struct gpio_chip *chip,
1175                                        unsigned int offset)
1176 {
1177         return pinctrl_gpio_direction_input(chip->base + offset);
1178 }
1179
1180 static int ocelot_gpio_direction_output(struct gpio_chip *chip,
1181                                         unsigned int offset, int value)
1182 {
1183         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1184         unsigned int pin = BIT(offset % 32);
1185
1186         if (value)
1187                 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1188                              pin);
1189         else
1190                 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1191                              pin);
1192
1193         return pinctrl_gpio_direction_output(chip->base + offset);
1194 }
1195
1196 static const struct gpio_chip ocelot_gpiolib_chip = {
1197         .request = gpiochip_generic_request,
1198         .free = gpiochip_generic_free,
1199         .set = ocelot_gpio_set,
1200         .get = ocelot_gpio_get,
1201         .get_direction = ocelot_gpio_get_direction,
1202         .direction_input = ocelot_gpio_direction_input,
1203         .direction_output = ocelot_gpio_direction_output,
1204         .owner = THIS_MODULE,
1205 };
1206
1207 static void ocelot_irq_mask(struct irq_data *data)
1208 {
1209         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1210         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1211         unsigned int gpio = irqd_to_hwirq(data);
1212
1213         regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1214                            BIT(gpio % 32), 0);
1215 }
1216
1217 static void ocelot_irq_unmask(struct irq_data *data)
1218 {
1219         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1220         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1221         unsigned int gpio = irqd_to_hwirq(data);
1222
1223         regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1224                            BIT(gpio % 32), BIT(gpio % 32));
1225 }
1226
1227 static void ocelot_irq_ack(struct irq_data *data)
1228 {
1229         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1230         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1231         unsigned int gpio = irqd_to_hwirq(data);
1232
1233         regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1234                           BIT(gpio % 32), BIT(gpio % 32));
1235 }
1236
1237 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
1238
1239 static struct irq_chip ocelot_eoi_irqchip = {
1240         .name           = "gpio",
1241         .irq_mask       = ocelot_irq_mask,
1242         .irq_eoi        = ocelot_irq_ack,
1243         .irq_unmask     = ocelot_irq_unmask,
1244         .flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
1245         .irq_set_type   = ocelot_irq_set_type,
1246 };
1247
1248 static struct irq_chip ocelot_irqchip = {
1249         .name           = "gpio",
1250         .irq_mask       = ocelot_irq_mask,
1251         .irq_ack        = ocelot_irq_ack,
1252         .irq_unmask     = ocelot_irq_unmask,
1253         .irq_set_type   = ocelot_irq_set_type,
1254 };
1255
1256 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
1257 {
1258         type &= IRQ_TYPE_SENSE_MASK;
1259
1260         if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
1261                 return -EINVAL;
1262
1263         if (type & IRQ_TYPE_LEVEL_HIGH)
1264                 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
1265                                                  handle_fasteoi_irq, NULL);
1266         if (type & IRQ_TYPE_EDGE_BOTH)
1267                 irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
1268                                                  handle_edge_irq, NULL);
1269
1270         return 0;
1271 }
1272
1273 static void ocelot_irq_handler(struct irq_desc *desc)
1274 {
1275         struct irq_chip *parent_chip = irq_desc_get_chip(desc);
1276         struct gpio_chip *chip = irq_desc_get_handler_data(desc);
1277         struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1278         unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
1279         unsigned int reg = 0, irq, i;
1280         unsigned long irqs;
1281
1282         for (i = 0; i < info->stride; i++) {
1283                 regmap_read(info->map, id_reg + 4 * i, &reg);
1284                 if (!reg)
1285                         continue;
1286
1287                 chained_irq_enter(parent_chip, desc);
1288
1289                 irqs = reg;
1290
1291                 for_each_set_bit(irq, &irqs,
1292                                  min(32U, info->desc->npins - 32 * i))
1293                         generic_handle_irq(irq_linear_revmap(chip->irq.domain,
1294                                                              irq + 32 * i));
1295
1296                 chained_irq_exit(parent_chip, desc);
1297         }
1298 }
1299
1300 static int ocelot_gpiochip_register(struct platform_device *pdev,
1301                                     struct ocelot_pinctrl *info)
1302 {
1303         struct gpio_chip *gc;
1304         struct gpio_irq_chip *girq;
1305         int irq;
1306
1307         info->gpio_chip = ocelot_gpiolib_chip;
1308
1309         gc = &info->gpio_chip;
1310         gc->ngpio = info->desc->npins;
1311         gc->parent = &pdev->dev;
1312         gc->base = 0;
1313         gc->of_node = info->dev->of_node;
1314         gc->label = "ocelot-gpio";
1315
1316         irq = irq_of_parse_and_map(gc->of_node, 0);
1317         if (irq) {
1318                 girq = &gc->irq;
1319                 girq->chip = &ocelot_irqchip;
1320                 girq->parent_handler = ocelot_irq_handler;
1321                 girq->num_parents = 1;
1322                 girq->parents = devm_kcalloc(&pdev->dev, 1,
1323                                              sizeof(*girq->parents),
1324                                              GFP_KERNEL);
1325                 if (!girq->parents)
1326                         return -ENOMEM;
1327                 girq->parents[0] = irq;
1328                 girq->default_type = IRQ_TYPE_NONE;
1329                 girq->handler = handle_edge_irq;
1330         }
1331
1332         return devm_gpiochip_add_data(&pdev->dev, gc, info);
1333 }
1334
1335 static const struct of_device_id ocelot_pinctrl_of_match[] = {
1336         { .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
1337         { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
1338         { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
1339         { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
1340         { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
1341         {},
1342 };
1343
1344 static int ocelot_pinctrl_probe(struct platform_device *pdev)
1345 {
1346         struct device *dev = &pdev->dev;
1347         struct ocelot_pinctrl *info;
1348         void __iomem *base;
1349         struct resource *res;
1350         int ret;
1351         struct regmap_config regmap_config = {
1352                 .reg_bits = 32,
1353                 .val_bits = 32,
1354                 .reg_stride = 4,
1355         };
1356
1357         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1358         if (!info)
1359                 return -ENOMEM;
1360
1361         info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
1362
1363         base = devm_ioremap_resource(dev,
1364                         platform_get_resource(pdev, IORESOURCE_MEM, 0));
1365         if (IS_ERR(base)) {
1366                 dev_err(dev, "Failed to ioremap registers\n");
1367                 return PTR_ERR(base);
1368         }
1369
1370         info->stride = 1 + (info->desc->npins - 1) / 32;
1371
1372         regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
1373
1374         info->map = devm_regmap_init_mmio(dev, base, &regmap_config);
1375         if (IS_ERR(info->map)) {
1376                 dev_err(dev, "Failed to create regmap\n");
1377                 return PTR_ERR(info->map);
1378         }
1379         dev_set_drvdata(dev, info->map);
1380         info->dev = dev;
1381
1382         /* Pinconf registers */
1383         if (info->desc->confops) {
1384                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1385                 base = devm_ioremap_resource(dev, res);
1386                 if (IS_ERR(base))
1387                         dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
1388                 else
1389                         info->pincfg = base;
1390         }
1391
1392         ret = ocelot_pinctrl_register(pdev, info);
1393         if (ret)
1394                 return ret;
1395
1396         ret = ocelot_gpiochip_register(pdev, info);
1397         if (ret)
1398                 return ret;
1399
1400         dev_info(dev, "driver registered\n");
1401
1402         return 0;
1403 }
1404
1405 static struct platform_driver ocelot_pinctrl_driver = {
1406         .driver = {
1407                 .name = "pinctrl-ocelot",
1408                 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
1409                 .suppress_bind_attrs = true,
1410         },
1411         .probe = ocelot_pinctrl_probe,
1412 };
1413 builtin_platform_driver(ocelot_pinctrl_driver);