1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Microsemi/Microchip SoCs serial gpio driver
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/gpio/driver.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/reset.h>
22 #include <linux/spinlock.h>
27 #define SGPIO_BITS_PER_WORD 32
28 #define SGPIO_MAX_BITS 4
29 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
52 SGPIO_FLAGS_HAS_IRQ = BIT(0),
55 struct sgpio_properties {
61 #define SGPIO_LUTON_AUTO_REPEAT BIT(5)
62 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
63 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
64 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
66 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
67 #define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
68 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
69 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
70 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
72 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
73 #define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
74 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
75 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
76 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
78 #define SGPIO_MASTER_INTR_ENA BIT(0)
80 #define SGPIO_INT_TRG_LEVEL 0
81 #define SGPIO_INT_TRG_EDGE 1
82 #define SGPIO_INT_TRG_EDGE_FALL 2
83 #define SGPIO_INT_TRG_EDGE_RISE 3
85 #define SGPIO_TRG_LEVEL_HIGH 0
86 #define SGPIO_TRG_LEVEL_LOW 1
88 static const struct sgpio_properties properties_luton = {
89 .arch = SGPIO_ARCH_LUTON,
90 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
93 static const struct sgpio_properties properties_ocelot = {
94 .arch = SGPIO_ARCH_OCELOT,
95 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
98 static const struct sgpio_properties properties_sparx5 = {
99 .arch = SGPIO_ARCH_SPARX5,
100 .flags = SGPIO_FLAGS_HAS_IRQ,
101 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
104 static const char * const functions[] = { "gpio" };
107 struct sgpio_priv *priv;
109 struct gpio_chip gpio;
110 struct pinctrl_desc pctl_desc;
115 struct sgpio_bank in;
116 struct sgpio_bank out;
121 const struct sgpio_properties *properties;
123 /* protects the config register and single shot mode */
124 struct mutex poll_lock;
127 struct sgpio_port_addr {
132 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
133 struct sgpio_port_addr *addr)
135 addr->port = pin / priv->bitcount;
136 addr->bit = pin % priv->bitcount;
139 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
141 return bit + port * priv->bitcount;
144 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off)
146 return (priv->properties->regoff[rno] + off) *
147 regmap_get_reg_stride(priv->regs);
150 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
152 u32 addr = sgpio_get_addr(priv, rno, off);
156 ret = regmap_read(priv->regs, addr, &val);
157 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret);
162 static void sgpio_writel(struct sgpio_priv *priv,
163 u32 val, u32 rno, u32 off)
165 u32 addr = sgpio_get_addr(priv, rno, off);
168 ret = regmap_write(priv->regs, addr, val);
169 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret);
172 static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
173 u32 rno, u32 off, u32 clear, u32 set)
175 u32 addr = sgpio_get_addr(priv, rno, off);
178 ret = regmap_update_bits(priv->regs, addr, clear | set, set);
179 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
182 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
184 int width = priv->bitcount - 1;
187 switch (priv->properties->arch) {
188 case SGPIO_ARCH_LUTON:
189 clr = SGPIO_LUTON_PORT_WIDTH;
190 set = SGPIO_LUTON_AUTO_REPEAT |
191 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
193 case SGPIO_ARCH_OCELOT:
194 clr = SGPIO_OCELOT_PORT_WIDTH;
195 set = SGPIO_OCELOT_AUTO_REPEAT |
196 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
198 case SGPIO_ARCH_SPARX5:
199 clr = SGPIO_SPARX5_PORT_WIDTH;
200 set = SGPIO_SPARX5_AUTO_REPEAT |
201 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
206 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
209 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
213 switch (priv->properties->arch) {
214 case SGPIO_ARCH_LUTON:
215 clr = SGPIO_LUTON_CLK_FREQ;
216 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
218 case SGPIO_ARCH_OCELOT:
219 clr = SGPIO_OCELOT_CLK_FREQ;
220 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
222 case SGPIO_ARCH_SPARX5:
223 clr = SGPIO_SPARX5_CLK_FREQ;
224 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
229 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
232 static int sgpio_single_shot(struct sgpio_priv *priv)
234 u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
237 unsigned int single_shot;
238 unsigned int auto_repeat;
240 switch (priv->properties->arch) {
241 case SGPIO_ARCH_LUTON:
242 /* not supported for now */
244 case SGPIO_ARCH_OCELOT:
245 single_shot = SGPIO_OCELOT_SINGLE_SHOT;
246 auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
248 case SGPIO_ARCH_SPARX5:
249 single_shot = SGPIO_SPARX5_SINGLE_SHOT;
250 auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
257 * Trigger immediate burst. This only works when auto repeat is turned
258 * off. Otherwise, the single shot bit will never be cleared by the
259 * hardware. Measurements showed that an update might take as long as
260 * the burst gap. On a LAN9668 this is about 50ms for the largest
262 * After the manual burst, reenable the auto repeat mode again.
264 mutex_lock(&priv->poll_lock);
265 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
270 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
271 !(ctrl & single_shot), 100, 60000);
273 /* reenable auto repeat mode even if there was an error */
274 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
276 mutex_unlock(&priv->poll_lock);
281 static int sgpio_output_set(struct sgpio_priv *priv,
282 struct sgpio_port_addr *addr,
285 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
286 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
291 switch (priv->properties->arch) {
292 case SGPIO_ARCH_LUTON:
293 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
294 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
296 case SGPIO_ARCH_OCELOT:
297 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
298 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
300 case SGPIO_ARCH_SPARX5:
301 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
302 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
308 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
314 ret = sgpio_single_shot(priv);
322 static int sgpio_output_get(struct sgpio_priv *priv,
323 struct sgpio_port_addr *addr)
325 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
326 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
328 switch (priv->properties->arch) {
329 case SGPIO_ARCH_LUTON:
330 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
332 case SGPIO_ARCH_OCELOT:
333 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
335 case SGPIO_ARCH_SPARX5:
336 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
342 return !!(val & BIT(bit));
345 static int sgpio_input_get(struct sgpio_priv *priv,
346 struct sgpio_port_addr *addr)
348 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
351 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
352 unsigned int pin, unsigned long *config)
354 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
355 u32 param = pinconf_to_config_param(*config);
356 struct sgpio_priv *priv = bank->priv;
357 struct sgpio_port_addr addr;
360 sgpio_pin_to_addr(priv, pin, &addr);
363 case PIN_CONFIG_INPUT_ENABLE:
364 val = bank->is_input;
367 case PIN_CONFIG_OUTPUT_ENABLE:
368 val = !bank->is_input;
371 case PIN_CONFIG_OUTPUT:
374 val = sgpio_output_get(priv, &addr);
381 *config = pinconf_to_config_packed(param, val);
386 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
387 unsigned long *configs, unsigned int num_configs)
389 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
390 struct sgpio_priv *priv = bank->priv;
391 struct sgpio_port_addr addr;
395 sgpio_pin_to_addr(priv, pin, &addr);
397 for (cfg = 0; cfg < num_configs; cfg++) {
398 param = pinconf_to_config_param(configs[cfg]);
399 arg = pinconf_to_config_argument(configs[cfg]);
402 case PIN_CONFIG_OUTPUT:
405 err = sgpio_output_set(priv, &addr, arg);
416 static const struct pinconf_ops sgpio_confops = {
418 .pin_config_get = sgpio_pinconf_get,
419 .pin_config_set = sgpio_pinconf_set,
420 .pin_config_config_dbg_show = pinconf_generic_dump_config,
423 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
428 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
429 unsigned int function)
434 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
435 unsigned int function,
436 const char *const **groups,
437 unsigned *const num_groups)
440 *num_groups = ARRAY_SIZE(functions);
445 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
446 unsigned int selector, unsigned int group)
451 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
452 struct pinctrl_gpio_range *range,
453 unsigned int pin, bool input)
455 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
457 return (input == bank->is_input) ? 0 : -EINVAL;
460 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
461 struct pinctrl_gpio_range *range,
464 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
465 struct sgpio_priv *priv = bank->priv;
466 struct sgpio_port_addr addr;
468 sgpio_pin_to_addr(priv, offset, &addr);
470 if ((priv->ports & BIT(addr.port)) == 0) {
471 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
472 addr.port, addr.bit);
479 static const struct pinmux_ops sgpio_pmx_ops = {
480 .get_functions_count = sgpio_get_functions_count,
481 .get_function_name = sgpio_get_function_name,
482 .get_function_groups = sgpio_get_function_groups,
483 .set_mux = sgpio_pinmux_set_mux,
484 .gpio_set_direction = sgpio_gpio_set_direction,
485 .gpio_request_enable = sgpio_gpio_request_enable,
488 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
490 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
492 return bank->pctl_desc.npins;
495 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
498 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
500 return bank->pctl_desc.pins[group].name;
503 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
505 const unsigned int **pins,
506 unsigned int *num_pins)
508 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
510 *pins = &bank->pctl_desc.pins[group].number;
516 static const struct pinctrl_ops sgpio_pctl_ops = {
517 .get_groups_count = sgpio_pctl_get_groups_count,
518 .get_group_name = sgpio_pctl_get_group_name,
519 .get_group_pins = sgpio_pctl_get_group_pins,
520 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
521 .dt_free_map = pinconf_generic_dt_free_map,
524 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
526 struct sgpio_bank *bank = gpiochip_get_data(gc);
528 /* Fixed-position function */
529 return bank->is_input ? 0 : -EINVAL;
532 static int microchip_sgpio_direction_output(struct gpio_chip *gc,
533 unsigned int gpio, int value)
535 struct sgpio_bank *bank = gpiochip_get_data(gc);
536 struct sgpio_priv *priv = bank->priv;
537 struct sgpio_port_addr addr;
539 /* Fixed-position function */
543 sgpio_pin_to_addr(priv, gpio, &addr);
545 return sgpio_output_set(priv, &addr, value);
548 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
550 struct sgpio_bank *bank = gpiochip_get_data(gc);
552 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
555 static void microchip_sgpio_set_value(struct gpio_chip *gc,
556 unsigned int gpio, int value)
558 microchip_sgpio_direction_output(gc, gpio, value);
561 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
563 struct sgpio_bank *bank = gpiochip_get_data(gc);
564 struct sgpio_priv *priv = bank->priv;
565 struct sgpio_port_addr addr;
567 sgpio_pin_to_addr(priv, gpio, &addr);
569 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
572 static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
573 const struct of_phandle_args *gpiospec,
576 struct sgpio_bank *bank = gpiochip_get_data(gc);
577 struct sgpio_priv *priv = bank->priv;
581 * Note that the SGIO pin is defined by *2* numbers, a port
582 * number between 0 and 31, and a bit index, 0 to 3.
584 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
585 gpiospec->args[1] > priv->bitcount)
588 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
594 *flags = gpiospec->args[2];
599 static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
601 const char *range_property_name = "microchip,sgpio-port-ranges";
602 struct device *dev = priv->dev;
603 u32 range_params[64];
606 /* Calculate port mask */
607 nranges = device_property_count_u32(dev, range_property_name);
608 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
609 dev_err(dev, "%s port range: '%s' property\n",
610 nranges == -EINVAL ? "Missing" : "Invalid",
611 range_property_name);
615 ret = device_property_read_u32_array(dev, range_property_name,
616 range_params, nranges);
618 dev_err(dev, "failed to parse '%s' property: %d\n",
619 range_property_name, ret);
622 for (i = 0; i < nranges; i += 2) {
625 start = range_params[i];
626 end = range_params[i + 1];
627 if (start > end || end >= SGPIO_BITS_PER_WORD) {
628 dev_err(dev, "Ill-formed port-range [%d:%d]\n",
631 priv->ports |= GENMASK(end, start);
637 static void microchip_sgpio_irq_settype(struct irq_data *data,
641 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
642 struct sgpio_bank *bank = gpiochip_get_data(chip);
643 unsigned int gpio = irqd_to_hwirq(data);
644 struct sgpio_port_addr addr;
648 sgpio_pin_to_addr(bank->priv, gpio, &addr);
650 spin_lock_irqsave(&bank->priv->lock, flags);
652 /* Disable interrupt while changing type */
653 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
654 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
656 /* Type value spread over 2 registers sets: low, high bit */
657 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
658 BIT(addr.port), (!!(type & 0x1)) << addr.port);
659 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
660 BIT(addr.port), (!!(type & 0x2)) << addr.port);
662 if (type == SGPIO_INT_TRG_LEVEL)
663 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
664 BIT(addr.port), polarity << addr.port);
666 /* Possibly re-enable interrupts */
667 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
669 spin_unlock_irqrestore(&bank->priv->lock, flags);
672 static void microchip_sgpio_irq_setreg(struct irq_data *data,
676 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
677 struct sgpio_bank *bank = gpiochip_get_data(chip);
678 unsigned int gpio = irqd_to_hwirq(data);
679 struct sgpio_port_addr addr;
681 sgpio_pin_to_addr(bank->priv, gpio, &addr);
684 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
686 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
689 static void microchip_sgpio_irq_mask(struct irq_data *data)
691 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
693 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
694 gpiochip_disable_irq(chip, data->hwirq);
697 static void microchip_sgpio_irq_unmask(struct irq_data *data)
699 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
701 gpiochip_enable_irq(chip, data->hwirq);
702 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
705 static void microchip_sgpio_irq_ack(struct irq_data *data)
707 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
708 struct sgpio_bank *bank = gpiochip_get_data(chip);
709 unsigned int gpio = irqd_to_hwirq(data);
710 struct sgpio_port_addr addr;
712 sgpio_pin_to_addr(bank->priv, gpio, &addr);
714 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
717 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
719 type &= IRQ_TYPE_SENSE_MASK;
722 case IRQ_TYPE_EDGE_BOTH:
723 irq_set_handler_locked(data, handle_edge_irq);
724 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
726 case IRQ_TYPE_EDGE_RISING:
727 irq_set_handler_locked(data, handle_edge_irq);
728 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
730 case IRQ_TYPE_EDGE_FALLING:
731 irq_set_handler_locked(data, handle_edge_irq);
732 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
734 case IRQ_TYPE_LEVEL_HIGH:
735 irq_set_handler_locked(data, handle_level_irq);
736 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
738 case IRQ_TYPE_LEVEL_LOW:
739 irq_set_handler_locked(data, handle_level_irq);
740 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
749 static const struct irq_chip microchip_sgpio_irqchip = {
751 .irq_mask = microchip_sgpio_irq_mask,
752 .irq_ack = microchip_sgpio_irq_ack,
753 .irq_unmask = microchip_sgpio_irq_unmask,
754 .irq_set_type = microchip_sgpio_irq_set_type,
755 .flags = IRQCHIP_IMMUTABLE,
756 GPIOCHIP_IRQ_RESOURCE_HELPERS,
759 static void sgpio_irq_handler(struct irq_desc *desc)
761 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
762 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
763 struct sgpio_bank *bank = gpiochip_get_data(chip);
764 struct sgpio_priv *priv = bank->priv;
768 for (bit = 0; bit < priv->bitcount; bit++) {
769 val = sgpio_readl(priv, REG_INT_IDENT, bit);
773 chained_irq_enter(parent_chip, desc);
775 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
776 gpio = sgpio_addr_to_pin(priv, port, bit);
777 generic_handle_domain_irq(chip->irq.domain, gpio);
780 chained_irq_exit(parent_chip, desc);
784 static int microchip_sgpio_register_bank(struct device *dev,
785 struct sgpio_priv *priv,
786 struct fwnode_handle *fwnode,
789 struct pinctrl_pin_desc *pins;
790 struct pinctrl_desc *pctl_desc;
791 struct pinctrl_dev *pctldev;
792 struct sgpio_bank *bank;
793 struct gpio_chip *gc;
797 /* Get overall bank struct */
798 bank = (bankno == 0) ? &priv->in : &priv->out;
801 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
802 dev_info(dev, "failed to get number of gpios for bank%d\n",
807 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
808 if (priv->bitcount > SGPIO_MAX_BITS) {
809 dev_err(dev, "Bit width exceeds maximum (%d)\n",
814 pctl_desc = &bank->pctl_desc;
815 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
817 bank->is_input ? "in" : "out");
818 pctl_desc->pctlops = &sgpio_pctl_ops;
819 pctl_desc->pmxops = &sgpio_pmx_ops;
820 pctl_desc->confops = &sgpio_confops;
821 pctl_desc->owner = THIS_MODULE;
823 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
827 pctl_desc->npins = ngpios;
828 pctl_desc->pins = pins;
830 for (i = 0; i < ngpios; i++) {
831 struct sgpio_port_addr addr;
833 sgpio_pin_to_addr(priv, i, &addr);
836 pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
838 bank->is_input ? 'I' : 'O',
839 addr.port, addr.bit);
844 pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
846 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
849 gc->label = pctl_desc->name;
852 gc->owner = THIS_MODULE;
853 gc->get_direction = microchip_sgpio_get_direction;
854 gc->direction_input = microchip_sgpio_direction_input;
855 gc->direction_output = microchip_sgpio_direction_output;
856 gc->get = microchip_sgpio_get_value;
857 gc->set = microchip_sgpio_set_value;
858 gc->request = gpiochip_generic_request;
859 gc->free = gpiochip_generic_free;
860 gc->of_xlate = microchip_sgpio_of_xlate;
861 gc->of_gpio_n_cells = 3;
864 gc->can_sleep = !bank->is_input;
866 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
867 int irq = fwnode_irq_get(fwnode, 0);
870 struct gpio_irq_chip *girq = &gc->irq;
872 gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip);
873 girq->parent_handler = sgpio_irq_handler;
874 girq->num_parents = 1;
875 girq->parents = devm_kcalloc(dev, 1,
876 sizeof(*girq->parents),
880 girq->parents[0] = irq;
881 girq->default_type = IRQ_TYPE_NONE;
882 girq->handler = handle_bad_irq;
884 /* Disable all individual pins */
885 for (i = 0; i < SGPIO_MAX_BITS; i++)
886 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
888 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
892 ret = devm_gpiochip_add_data(dev, gc, bank);
894 dev_err(dev, "Failed to register: ret %d\n", ret);
899 static int microchip_sgpio_probe(struct platform_device *pdev)
901 int div_clock = 0, ret, port, i, nbanks;
902 struct device *dev = &pdev->dev;
903 struct fwnode_handle *fwnode;
904 struct reset_control *reset;
905 struct sgpio_priv *priv;
909 struct regmap_config regmap_config = {
915 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
920 spin_lock_init(&priv->lock);
921 mutex_init(&priv->poll_lock);
923 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
925 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
926 reset_control_reset(reset);
928 clk = devm_clk_get(dev, NULL);
930 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
932 div_clock = clk_get_rate(clk);
933 if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
934 priv->clock = 12500000;
935 if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
936 dev_err(dev, "Invalid frequency %d\n", priv->clock);
940 regs = devm_platform_ioremap_resource(pdev, 0);
942 return PTR_ERR(regs);
944 priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config);
945 if (IS_ERR(priv->regs))
946 return PTR_ERR(priv->regs);
948 priv->properties = device_get_match_data(dev);
949 priv->in.is_input = true;
951 /* Get rest of device properties */
952 ret = microchip_sgpio_get_ports(priv);
956 nbanks = device_get_child_node_count(dev);
958 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
963 device_for_each_child_node(dev, fwnode) {
964 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
966 fwnode_handle_put(fwnode);
971 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
972 dev_err(dev, "Banks must have same GPIO count\n");
976 sgpio_configure_bitstream(priv);
978 val = max(2U, div_clock / priv->clock);
979 sgpio_configure_clock(priv, val);
981 for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
982 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
983 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
988 static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
990 .compatible = "microchip,sparx5-sgpio",
991 .data = &properties_sparx5,
993 .compatible = "mscc,luton-sgpio",
994 .data = &properties_luton,
996 .compatible = "mscc,ocelot-sgpio",
997 .data = &properties_ocelot,
1003 static struct platform_driver microchip_sgpio_pinctrl_driver = {
1005 .name = "pinctrl-microchip-sgpio",
1006 .of_match_table = microchip_sgpio_gpio_of_match,
1007 .suppress_bind_attrs = true,
1009 .probe = microchip_sgpio_probe,
1011 builtin_platform_driver(microchip_sgpio_pinctrl_driver);