1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Microsemi/Microchip SoCs serial gpio driver
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/gpio/driver.h>
15 #include <linux/mfd/ocelot.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 #include <linux/spinlock.h>
28 #define SGPIO_BITS_PER_WORD 32
29 #define SGPIO_MAX_BITS 4
30 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
53 SGPIO_FLAGS_HAS_IRQ = BIT(0),
56 struct sgpio_properties {
62 #define SGPIO_LUTON_AUTO_REPEAT BIT(5)
63 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
64 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
65 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
67 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
68 #define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
69 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
70 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
71 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
73 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
74 #define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
75 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
76 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
77 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
79 #define SGPIO_MASTER_INTR_ENA BIT(0)
81 #define SGPIO_INT_TRG_LEVEL 0
82 #define SGPIO_INT_TRG_EDGE 1
83 #define SGPIO_INT_TRG_EDGE_FALL 2
84 #define SGPIO_INT_TRG_EDGE_RISE 3
86 #define SGPIO_TRG_LEVEL_HIGH 0
87 #define SGPIO_TRG_LEVEL_LOW 1
89 static const struct sgpio_properties properties_luton = {
90 .arch = SGPIO_ARCH_LUTON,
91 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
94 static const struct sgpio_properties properties_ocelot = {
95 .arch = SGPIO_ARCH_OCELOT,
96 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
99 static const struct sgpio_properties properties_sparx5 = {
100 .arch = SGPIO_ARCH_SPARX5,
101 .flags = SGPIO_FLAGS_HAS_IRQ,
102 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
105 static const char * const functions[] = { "gpio" };
108 struct sgpio_priv *priv;
110 struct gpio_chip gpio;
111 struct pinctrl_desc pctl_desc;
116 struct sgpio_bank in;
117 struct sgpio_bank out;
122 const struct sgpio_properties *properties;
124 /* protects the config register and single shot mode */
125 struct mutex poll_lock;
128 struct sgpio_port_addr {
133 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
134 struct sgpio_port_addr *addr)
136 addr->port = pin / priv->bitcount;
137 addr->bit = pin % priv->bitcount;
140 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
142 return bit + port * priv->bitcount;
145 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off)
147 return (priv->properties->regoff[rno] + off) *
148 regmap_get_reg_stride(priv->regs);
151 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
153 u32 addr = sgpio_get_addr(priv, rno, off);
157 ret = regmap_read(priv->regs, addr, &val);
158 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret);
163 static void sgpio_writel(struct sgpio_priv *priv,
164 u32 val, u32 rno, u32 off)
166 u32 addr = sgpio_get_addr(priv, rno, off);
169 ret = regmap_write(priv->regs, addr, val);
170 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret);
173 static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
174 u32 rno, u32 off, u32 clear, u32 set)
176 u32 addr = sgpio_get_addr(priv, rno, off);
179 ret = regmap_update_bits(priv->regs, addr, clear | set, set);
180 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
183 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
185 int width = priv->bitcount - 1;
188 switch (priv->properties->arch) {
189 case SGPIO_ARCH_LUTON:
190 clr = SGPIO_LUTON_PORT_WIDTH;
191 set = SGPIO_LUTON_AUTO_REPEAT |
192 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
194 case SGPIO_ARCH_OCELOT:
195 clr = SGPIO_OCELOT_PORT_WIDTH;
196 set = SGPIO_OCELOT_AUTO_REPEAT |
197 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
199 case SGPIO_ARCH_SPARX5:
200 clr = SGPIO_SPARX5_PORT_WIDTH;
201 set = SGPIO_SPARX5_AUTO_REPEAT |
202 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
207 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
210 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
214 switch (priv->properties->arch) {
215 case SGPIO_ARCH_LUTON:
216 clr = SGPIO_LUTON_CLK_FREQ;
217 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
219 case SGPIO_ARCH_OCELOT:
220 clr = SGPIO_OCELOT_CLK_FREQ;
221 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
223 case SGPIO_ARCH_SPARX5:
224 clr = SGPIO_SPARX5_CLK_FREQ;
225 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
230 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
233 static int sgpio_single_shot(struct sgpio_priv *priv)
235 u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
238 unsigned int single_shot;
239 unsigned int auto_repeat;
241 switch (priv->properties->arch) {
242 case SGPIO_ARCH_LUTON:
243 /* not supported for now */
245 case SGPIO_ARCH_OCELOT:
246 single_shot = SGPIO_OCELOT_SINGLE_SHOT;
247 auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
249 case SGPIO_ARCH_SPARX5:
250 single_shot = SGPIO_SPARX5_SINGLE_SHOT;
251 auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
258 * Trigger immediate burst. This only works when auto repeat is turned
259 * off. Otherwise, the single shot bit will never be cleared by the
260 * hardware. Measurements showed that an update might take as long as
261 * the burst gap. On a LAN9668 this is about 50ms for the largest
263 * After the manual burst, reenable the auto repeat mode again.
265 mutex_lock(&priv->poll_lock);
266 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
271 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
272 !(ctrl & single_shot), 100, 60000);
274 /* reenable auto repeat mode even if there was an error */
275 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
277 mutex_unlock(&priv->poll_lock);
282 static int sgpio_output_set(struct sgpio_priv *priv,
283 struct sgpio_port_addr *addr,
286 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
287 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
292 switch (priv->properties->arch) {
293 case SGPIO_ARCH_LUTON:
294 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
295 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
297 case SGPIO_ARCH_OCELOT:
298 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
299 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
301 case SGPIO_ARCH_SPARX5:
302 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
303 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
309 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
315 ret = sgpio_single_shot(priv);
323 static int sgpio_output_get(struct sgpio_priv *priv,
324 struct sgpio_port_addr *addr)
326 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
327 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
329 switch (priv->properties->arch) {
330 case SGPIO_ARCH_LUTON:
331 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
333 case SGPIO_ARCH_OCELOT:
334 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
336 case SGPIO_ARCH_SPARX5:
337 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
343 return !!(val & BIT(bit));
346 static int sgpio_input_get(struct sgpio_priv *priv,
347 struct sgpio_port_addr *addr)
349 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
352 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
353 unsigned int pin, unsigned long *config)
355 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
356 u32 param = pinconf_to_config_param(*config);
357 struct sgpio_priv *priv = bank->priv;
358 struct sgpio_port_addr addr;
361 sgpio_pin_to_addr(priv, pin, &addr);
364 case PIN_CONFIG_INPUT_ENABLE:
365 val = bank->is_input;
368 case PIN_CONFIG_OUTPUT_ENABLE:
369 val = !bank->is_input;
372 case PIN_CONFIG_OUTPUT:
375 val = sgpio_output_get(priv, &addr);
382 *config = pinconf_to_config_packed(param, val);
387 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
388 unsigned long *configs, unsigned int num_configs)
390 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
391 struct sgpio_priv *priv = bank->priv;
392 struct sgpio_port_addr addr;
396 sgpio_pin_to_addr(priv, pin, &addr);
398 for (cfg = 0; cfg < num_configs; cfg++) {
399 param = pinconf_to_config_param(configs[cfg]);
400 arg = pinconf_to_config_argument(configs[cfg]);
403 case PIN_CONFIG_OUTPUT:
406 err = sgpio_output_set(priv, &addr, arg);
417 static const struct pinconf_ops sgpio_confops = {
419 .pin_config_get = sgpio_pinconf_get,
420 .pin_config_set = sgpio_pinconf_set,
421 .pin_config_config_dbg_show = pinconf_generic_dump_config,
424 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
429 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
430 unsigned int function)
435 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
436 unsigned int function,
437 const char *const **groups,
438 unsigned *const num_groups)
441 *num_groups = ARRAY_SIZE(functions);
446 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
447 unsigned int selector, unsigned int group)
452 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
453 struct pinctrl_gpio_range *range,
454 unsigned int pin, bool input)
456 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
458 return (input == bank->is_input) ? 0 : -EINVAL;
461 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
462 struct pinctrl_gpio_range *range,
465 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
466 struct sgpio_priv *priv = bank->priv;
467 struct sgpio_port_addr addr;
469 sgpio_pin_to_addr(priv, offset, &addr);
471 if ((priv->ports & BIT(addr.port)) == 0) {
472 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
473 addr.port, addr.bit);
480 static const struct pinmux_ops sgpio_pmx_ops = {
481 .get_functions_count = sgpio_get_functions_count,
482 .get_function_name = sgpio_get_function_name,
483 .get_function_groups = sgpio_get_function_groups,
484 .set_mux = sgpio_pinmux_set_mux,
485 .gpio_set_direction = sgpio_gpio_set_direction,
486 .gpio_request_enable = sgpio_gpio_request_enable,
489 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
491 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
493 return bank->pctl_desc.npins;
496 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
499 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
501 return bank->pctl_desc.pins[group].name;
504 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
506 const unsigned int **pins,
507 unsigned int *num_pins)
509 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
511 *pins = &bank->pctl_desc.pins[group].number;
517 static const struct pinctrl_ops sgpio_pctl_ops = {
518 .get_groups_count = sgpio_pctl_get_groups_count,
519 .get_group_name = sgpio_pctl_get_group_name,
520 .get_group_pins = sgpio_pctl_get_group_pins,
521 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
522 .dt_free_map = pinconf_generic_dt_free_map,
525 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
527 struct sgpio_bank *bank = gpiochip_get_data(gc);
529 /* Fixed-position function */
530 return bank->is_input ? 0 : -EINVAL;
533 static int microchip_sgpio_direction_output(struct gpio_chip *gc,
534 unsigned int gpio, int value)
536 struct sgpio_bank *bank = gpiochip_get_data(gc);
537 struct sgpio_priv *priv = bank->priv;
538 struct sgpio_port_addr addr;
540 /* Fixed-position function */
544 sgpio_pin_to_addr(priv, gpio, &addr);
546 return sgpio_output_set(priv, &addr, value);
549 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
551 struct sgpio_bank *bank = gpiochip_get_data(gc);
553 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
556 static void microchip_sgpio_set_value(struct gpio_chip *gc,
557 unsigned int gpio, int value)
559 microchip_sgpio_direction_output(gc, gpio, value);
562 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
564 struct sgpio_bank *bank = gpiochip_get_data(gc);
565 struct sgpio_priv *priv = bank->priv;
566 struct sgpio_port_addr addr;
568 sgpio_pin_to_addr(priv, gpio, &addr);
570 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
573 static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
574 const struct of_phandle_args *gpiospec,
577 struct sgpio_bank *bank = gpiochip_get_data(gc);
578 struct sgpio_priv *priv = bank->priv;
582 * Note that the SGIO pin is defined by *2* numbers, a port
583 * number between 0 and 31, and a bit index, 0 to 3.
585 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
586 gpiospec->args[1] > priv->bitcount)
589 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
595 *flags = gpiospec->args[2];
600 static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
602 const char *range_property_name = "microchip,sgpio-port-ranges";
603 struct device *dev = priv->dev;
604 u32 range_params[64];
607 /* Calculate port mask */
608 nranges = device_property_count_u32(dev, range_property_name);
609 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
610 dev_err(dev, "%s port range: '%s' property\n",
611 nranges == -EINVAL ? "Missing" : "Invalid",
612 range_property_name);
616 ret = device_property_read_u32_array(dev, range_property_name,
617 range_params, nranges);
619 dev_err(dev, "failed to parse '%s' property: %d\n",
620 range_property_name, ret);
623 for (i = 0; i < nranges; i += 2) {
626 start = range_params[i];
627 end = range_params[i + 1];
628 if (start > end || end >= SGPIO_BITS_PER_WORD) {
629 dev_err(dev, "Ill-formed port-range [%d:%d]\n",
632 priv->ports |= GENMASK(end, start);
638 static void microchip_sgpio_irq_settype(struct irq_data *data,
642 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
643 struct sgpio_bank *bank = gpiochip_get_data(chip);
644 unsigned int gpio = irqd_to_hwirq(data);
645 struct sgpio_port_addr addr;
649 sgpio_pin_to_addr(bank->priv, gpio, &addr);
651 spin_lock_irqsave(&bank->priv->lock, flags);
653 /* Disable interrupt while changing type */
654 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
655 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
657 /* Type value spread over 2 registers sets: low, high bit */
658 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
659 BIT(addr.port), (!!(type & 0x1)) << addr.port);
660 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
661 BIT(addr.port), (!!(type & 0x2)) << addr.port);
663 if (type == SGPIO_INT_TRG_LEVEL)
664 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
665 BIT(addr.port), polarity << addr.port);
667 /* Possibly re-enable interrupts */
668 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
670 spin_unlock_irqrestore(&bank->priv->lock, flags);
673 static void microchip_sgpio_irq_setreg(struct irq_data *data,
677 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
678 struct sgpio_bank *bank = gpiochip_get_data(chip);
679 unsigned int gpio = irqd_to_hwirq(data);
680 struct sgpio_port_addr addr;
682 sgpio_pin_to_addr(bank->priv, gpio, &addr);
685 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
687 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
690 static void microchip_sgpio_irq_mask(struct irq_data *data)
692 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
694 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
695 gpiochip_disable_irq(chip, data->hwirq);
698 static void microchip_sgpio_irq_unmask(struct irq_data *data)
700 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
702 gpiochip_enable_irq(chip, data->hwirq);
703 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
706 static void microchip_sgpio_irq_ack(struct irq_data *data)
708 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
709 struct sgpio_bank *bank = gpiochip_get_data(chip);
710 unsigned int gpio = irqd_to_hwirq(data);
711 struct sgpio_port_addr addr;
713 sgpio_pin_to_addr(bank->priv, gpio, &addr);
715 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
718 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
720 type &= IRQ_TYPE_SENSE_MASK;
723 case IRQ_TYPE_EDGE_BOTH:
724 irq_set_handler_locked(data, handle_edge_irq);
725 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
727 case IRQ_TYPE_EDGE_RISING:
728 irq_set_handler_locked(data, handle_edge_irq);
729 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
731 case IRQ_TYPE_EDGE_FALLING:
732 irq_set_handler_locked(data, handle_edge_irq);
733 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
735 case IRQ_TYPE_LEVEL_HIGH:
736 irq_set_handler_locked(data, handle_level_irq);
737 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
739 case IRQ_TYPE_LEVEL_LOW:
740 irq_set_handler_locked(data, handle_level_irq);
741 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
750 static const struct irq_chip microchip_sgpio_irqchip = {
752 .irq_mask = microchip_sgpio_irq_mask,
753 .irq_ack = microchip_sgpio_irq_ack,
754 .irq_unmask = microchip_sgpio_irq_unmask,
755 .irq_set_type = microchip_sgpio_irq_set_type,
756 .flags = IRQCHIP_IMMUTABLE,
757 GPIOCHIP_IRQ_RESOURCE_HELPERS,
760 static void sgpio_irq_handler(struct irq_desc *desc)
762 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
763 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
764 struct sgpio_bank *bank = gpiochip_get_data(chip);
765 struct sgpio_priv *priv = bank->priv;
769 for (bit = 0; bit < priv->bitcount; bit++) {
770 val = sgpio_readl(priv, REG_INT_IDENT, bit);
774 chained_irq_enter(parent_chip, desc);
776 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
777 gpio = sgpio_addr_to_pin(priv, port, bit);
778 generic_handle_domain_irq(chip->irq.domain, gpio);
781 chained_irq_exit(parent_chip, desc);
785 static int microchip_sgpio_register_bank(struct device *dev,
786 struct sgpio_priv *priv,
787 struct fwnode_handle *fwnode,
790 struct pinctrl_pin_desc *pins;
791 struct pinctrl_desc *pctl_desc;
792 struct pinctrl_dev *pctldev;
793 struct sgpio_bank *bank;
794 struct gpio_chip *gc;
798 /* Get overall bank struct */
799 bank = (bankno == 0) ? &priv->in : &priv->out;
802 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
803 dev_info(dev, "failed to get number of gpios for bank%d\n",
808 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
809 if (priv->bitcount > SGPIO_MAX_BITS) {
810 dev_err(dev, "Bit width exceeds maximum (%d)\n",
815 pctl_desc = &bank->pctl_desc;
816 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
818 bank->is_input ? "in" : "out");
819 pctl_desc->pctlops = &sgpio_pctl_ops;
820 pctl_desc->pmxops = &sgpio_pmx_ops;
821 pctl_desc->confops = &sgpio_confops;
822 pctl_desc->owner = THIS_MODULE;
824 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
828 pctl_desc->npins = ngpios;
829 pctl_desc->pins = pins;
831 for (i = 0; i < ngpios; i++) {
832 struct sgpio_port_addr addr;
834 sgpio_pin_to_addr(priv, i, &addr);
837 pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
839 bank->is_input ? 'I' : 'O',
840 addr.port, addr.bit);
845 pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
847 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
850 gc->label = pctl_desc->name;
853 gc->owner = THIS_MODULE;
854 gc->get_direction = microchip_sgpio_get_direction;
855 gc->direction_input = microchip_sgpio_direction_input;
856 gc->direction_output = microchip_sgpio_direction_output;
857 gc->get = microchip_sgpio_get_value;
858 gc->set = microchip_sgpio_set_value;
859 gc->request = gpiochip_generic_request;
860 gc->free = gpiochip_generic_free;
861 gc->of_xlate = microchip_sgpio_of_xlate;
862 gc->of_gpio_n_cells = 3;
865 gc->can_sleep = !bank->is_input;
867 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
870 irq = fwnode_irq_get(fwnode, 0);
872 struct gpio_irq_chip *girq = &gc->irq;
874 gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip);
875 girq->parent_handler = sgpio_irq_handler;
876 girq->num_parents = 1;
877 girq->parents = devm_kcalloc(dev, 1,
878 sizeof(*girq->parents),
882 girq->parents[0] = irq;
883 girq->default_type = IRQ_TYPE_NONE;
884 girq->handler = handle_bad_irq;
886 /* Disable all individual pins */
887 for (i = 0; i < SGPIO_MAX_BITS; i++)
888 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
890 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
894 ret = devm_gpiochip_add_data(dev, gc, bank);
896 dev_err(dev, "Failed to register: ret %d\n", ret);
901 static int microchip_sgpio_probe(struct platform_device *pdev)
903 int div_clock = 0, ret, port, i, nbanks;
904 struct device *dev = &pdev->dev;
905 struct fwnode_handle *fwnode;
906 struct reset_control *reset;
907 struct sgpio_priv *priv;
910 struct regmap_config regmap_config = {
916 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
921 spin_lock_init(&priv->lock);
922 mutex_init(&priv->poll_lock);
924 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
926 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
927 reset_control_reset(reset);
929 clk = devm_clk_get(dev, NULL);
931 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
933 div_clock = clk_get_rate(clk);
934 if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
935 priv->clock = 12500000;
936 if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
937 dev_err(dev, "Invalid frequency %d\n", priv->clock);
941 priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config);
942 if (IS_ERR(priv->regs))
943 return PTR_ERR(priv->regs);
945 priv->properties = device_get_match_data(dev);
946 priv->in.is_input = true;
948 /* Get rest of device properties */
949 ret = microchip_sgpio_get_ports(priv);
953 nbanks = device_get_child_node_count(dev);
955 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
960 device_for_each_child_node(dev, fwnode) {
961 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
963 fwnode_handle_put(fwnode);
968 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
969 dev_err(dev, "Banks must have same GPIO count\n");
973 sgpio_configure_bitstream(priv);
975 val = max(2U, div_clock / priv->clock);
976 sgpio_configure_clock(priv, val);
978 for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
979 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
980 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
985 static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
987 .compatible = "microchip,sparx5-sgpio",
988 .data = &properties_sparx5,
990 .compatible = "mscc,luton-sgpio",
991 .data = &properties_luton,
993 .compatible = "mscc,ocelot-sgpio",
994 .data = &properties_ocelot,
999 MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match);
1001 static struct platform_driver microchip_sgpio_pinctrl_driver = {
1003 .name = "pinctrl-microchip-sgpio",
1004 .of_match_table = microchip_sgpio_gpio_of_match,
1005 .suppress_bind_attrs = true,
1007 .probe = microchip_sgpio_probe,
1009 module_platform_driver(microchip_sgpio_pinctrl_driver);
1011 MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");
1012 MODULE_LICENSE("GPL");