drivers/pinctrl/pinctrl-cy8c95x0.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
   4  *
   5  * Copyright (C) 2022 9elements GmbH
   6  * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>
   7  *          Naresh Solanki <Naresh.Solanki@9elements.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/bitmap.h>
  12 #include <linux/dmi.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/i2c.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/module.h>
  20 #include <linux/property.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinconf.h>
  26 #include <linux/pinctrl/pinconf-generic.h>
  27 #include <linux/pinctrl/pinmux.h>
  28
  29 /* Fast access registers */
  30 #define CY8C95X0_INPUT          0x00
  31 #define CY8C95X0_OUTPUT         0x08
  32 #define CY8C95X0_INTSTATUS      0x10
  33
  34 #define CY8C95X0_INPUT_(x)      (CY8C95X0_INPUT + (x))
  35 #define CY8C95X0_OUTPUT_(x)     (CY8C95X0_OUTPUT + (x))
  36 #define CY8C95X0_INTSTATUS_(x)  (CY8C95X0_INTSTATUS + (x))
  37
  38 /* Port Select configures the port */
  39 #define CY8C95X0_PORTSEL        0x18
  40 /* Port settings, write PORTSEL first */
  41 #define CY8C95X0_INTMASK        0x19
  42 #define CY8C95X0_PWMSEL         0x1A
  43 #define CY8C95X0_INVERT         0x1B
  44 #define CY8C95X0_DIRECTION      0x1C
  45 /* Drive mode register change state on writing '1' */
  46 #define CY8C95X0_DRV_PU         0x1D
  47 #define CY8C95X0_DRV_PD         0x1E
  48 #define CY8C95X0_DRV_ODH        0x1F
  49 #define CY8C95X0_DRV_ODL        0x20
  50 #define CY8C95X0_DRV_PP_FAST    0x21
  51 #define CY8C95X0_DRV_PP_SLOW    0x22
  52 #define CY8C95X0_DRV_HIZ        0x23
  53 #define CY8C95X0_DEVID          0x2E
  54 #define CY8C95X0_WATCHDOG       0x2F
  55 #define CY8C95X0_COMMAND        0x30
  56
  57 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
  58
  59 static const struct i2c_device_id cy8c95x0_id[] = {
  60         { "cy8c9520", 20, },
  61         { "cy8c9540", 40, },
  62         { "cy8c9560", 60, },
  63         { }
  64 };
  65 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
  66
  67 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
  68
  69 static const struct of_device_id cy8c95x0_dt_ids[] = {
  70         { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
  71         { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
  72         { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
  73         { }
  74 };
  75 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
  76
  77 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
  78
  79 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
  80         { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
  81         { }
  82 };
  83
  84 static int cy8c95x0_acpi_get_irq(struct device *dev)
  85 {
  86         int ret;
  87
  88         ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
  89         if (ret)
  90                 dev_warn(dev, "can't add GPIO ACPI mapping\n");
  91
  92         ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
  93         if (ret < 0)
  94                 return ret;
  95
  96         dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
  97         return ret;
  98 }
  99
 100 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
 101         {
 102                 /*
 103                  * On Intel Galileo Gen 1 board the IRQ pin is provided
 104                  * as an absolute number instead of being relative.
 105                  * Since first controller (gpio-sch.c) and second
 106                  * (gpio-dwapb.c) are at the fixed bases, we may safely
 107                  * refer to the number in the global space to get an IRQ
 108                  * out of it.
 109                  */
 110                 .matches = {
 111                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
 112                 },
 113         },
 114         {}
 115 };
 116
 117 #define MAX_BANK 8
 118 #define BANK_SZ 8
 119 #define MAX_LINE        (MAX_BANK * BANK_SZ)
 120
 121 #define CY8C95X0_GPIO_MASK              GENMASK(7, 0)
 122
 123 /**
 124  * struct cy8c95x0_pinctrl - driver data
 125  * @regmap:         Device's regmap
 126  * @irq_lock:       IRQ bus lock
 127  * @i2c_lock:       Mutex for the device internal mux register
 128  * @irq_mask:       I/O bits affected by interrupts
 129  * @irq_trig_raise: I/O bits affected by raising voltage level
 130  * @irq_trig_fall:  I/O bits affected by falling voltage level
 131  * @irq_trig_low:   I/O bits affected by a low voltage level
 132  * @irq_trig_high:  I/O bits affected by a high voltage level
 133  * @push_pull:      I/O bits configured as push pull driver
 134  * @shiftmask:      Mask used to compensate for Gport2 width
 135  * @nport:          Number of Gports in this chip
 136  * @gpio_chip:      gpiolib chip
 137  * @driver_data:    private driver data
 138  * @regulator:      Pointer to the regulator for the IC
 139  * @dev:            struct device
 140  * @pctldev:        pin controller device
 141  * @pinctrl_desc:   pin controller description
 142  * @name:           Chip controller name
 143  * @tpin:           Total number of pins
 144  */
 145 struct cy8c95x0_pinctrl {
 146         struct regmap *regmap;
 147         struct mutex irq_lock;
 148         struct mutex i2c_lock;
 149         DECLARE_BITMAP(irq_mask, MAX_LINE);
 150         DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
 151         DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
 152         DECLARE_BITMAP(irq_trig_low, MAX_LINE);
 153         DECLARE_BITMAP(irq_trig_high, MAX_LINE);
 154         DECLARE_BITMAP(push_pull, MAX_LINE);
 155         DECLARE_BITMAP(shiftmask, MAX_LINE);
 156         int nport;
 157         struct gpio_chip gpio_chip;
 158         unsigned long driver_data;
 159         struct regulator *regulator;
 160         struct device *dev;
 161         struct pinctrl_dev *pctldev;
 162         struct pinctrl_desc pinctrl_desc;
 163         char name[32];
 164         unsigned int tpin;
 165 };
 166
 167 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
 168         PINCTRL_PIN(0, "gp00"),
 169         PINCTRL_PIN(1, "gp01"),
 170         PINCTRL_PIN(2, "gp02"),
 171         PINCTRL_PIN(3, "gp03"),
 172         PINCTRL_PIN(4, "gp04"),
 173         PINCTRL_PIN(5, "gp05"),
 174         PINCTRL_PIN(6, "gp06"),
 175         PINCTRL_PIN(7, "gp07"),
 176
 177         PINCTRL_PIN(8, "gp10"),
 178         PINCTRL_PIN(9, "gp11"),
 179         PINCTRL_PIN(10, "gp12"),
 180         PINCTRL_PIN(11, "gp13"),
 181         PINCTRL_PIN(12, "gp14"),
 182         PINCTRL_PIN(13, "gp15"),
 183         PINCTRL_PIN(14, "gp16"),
 184         PINCTRL_PIN(15, "gp17"),
 185
 186         PINCTRL_PIN(16, "gp20"),
 187         PINCTRL_PIN(17, "gp21"),
 188         PINCTRL_PIN(18, "gp22"),
 189         PINCTRL_PIN(19, "gp23"),
 190
 191         PINCTRL_PIN(20, "gp30"),
 192         PINCTRL_PIN(21, "gp31"),
 193         PINCTRL_PIN(22, "gp32"),
 194         PINCTRL_PIN(23, "gp33"),
 195         PINCTRL_PIN(24, "gp34"),
 196         PINCTRL_PIN(25, "gp35"),
 197         PINCTRL_PIN(26, "gp36"),
 198         PINCTRL_PIN(27, "gp37"),
 199
 200         PINCTRL_PIN(28, "gp40"),
 201         PINCTRL_PIN(29, "gp41"),
 202         PINCTRL_PIN(30, "gp42"),
 203         PINCTRL_PIN(31, "gp43"),
 204         PINCTRL_PIN(32, "gp44"),
 205         PINCTRL_PIN(33, "gp45"),
 206         PINCTRL_PIN(34, "gp46"),
 207         PINCTRL_PIN(35, "gp47"),
 208
 209         PINCTRL_PIN(36, "gp50"),
 210         PINCTRL_PIN(37, "gp51"),
 211         PINCTRL_PIN(38, "gp52"),
 212         PINCTRL_PIN(39, "gp53"),
 213         PINCTRL_PIN(40, "gp54"),
 214         PINCTRL_PIN(41, "gp55"),
 215         PINCTRL_PIN(42, "gp56"),
 216         PINCTRL_PIN(43, "gp57"),
 217
 218         PINCTRL_PIN(44, "gp60"),
 219         PINCTRL_PIN(45, "gp61"),
 220         PINCTRL_PIN(46, "gp62"),
 221         PINCTRL_PIN(47, "gp63"),
 222         PINCTRL_PIN(48, "gp64"),
 223         PINCTRL_PIN(49, "gp65"),
 224         PINCTRL_PIN(50, "gp66"),
 225         PINCTRL_PIN(51, "gp67"),
 226
 227         PINCTRL_PIN(52, "gp70"),
 228         PINCTRL_PIN(53, "gp71"),
 229         PINCTRL_PIN(54, "gp72"),
 230         PINCTRL_PIN(55, "gp73"),
 231         PINCTRL_PIN(56, "gp74"),
 232         PINCTRL_PIN(57, "gp75"),
 233         PINCTRL_PIN(58, "gp76"),
 234         PINCTRL_PIN(59, "gp77"),
 235 };
 236
 237 static const char * const cy8c95x0_groups[] = {
 238         "gp00",
 239         "gp01",
 240         "gp02",
 241         "gp03",
 242         "gp04",
 243         "gp05",
 244         "gp06",
 245         "gp07",
 246
 247         "gp10",
 248         "gp11",
 249         "gp12",
 250         "gp13",
 251         "gp14",
 252         "gp15",
 253         "gp16",
 254         "gp17",
 255
 256         "gp20",
 257         "gp21",
 258         "gp22",
 259         "gp23",
 260
 261         "gp30",
 262         "gp31",
 263         "gp32",
 264         "gp33",
 265         "gp34",
 266         "gp35",
 267         "gp36",
 268         "gp37",
 269
 270         "gp40",
 271         "gp41",
 272         "gp42",
 273         "gp43",
 274         "gp44",
 275         "gp45",
 276         "gp46",
 277         "gp47",
 278
 279         "gp50",
 280         "gp51",
 281         "gp52",
 282         "gp53",
 283         "gp54",
 284         "gp55",
 285         "gp56",
 286         "gp57",
 287
 288         "gp60",
 289         "gp61",
 290         "gp62",
 291         "gp63",
 292         "gp64",
 293         "gp65",
 294         "gp66",
 295         "gp67",
 296
 297         "gp70",
 298         "gp71",
 299         "gp72",
 300         "gp73",
 301         "gp74",
 302         "gp75",
 303         "gp76",
 304         "gp77",
 305 };
 306
 307 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 308 {
 309         /* Account for GPORT2 which only has 4 bits */
 310         return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
 311 }
 312
 313 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 314 {
 315         /* Account for GPORT2 which only has 4 bits */
 316         return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
 317 }
 318
 319 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
 320 {
 321         switch (reg) {
 322         case 0x24 ... 0x27:
 323                 return false;
 324         default:
 325                 return true;
 326         }
 327 }
 328
 329 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
 330 {
 331         switch (reg) {
 332         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 333                 return false;
 334         case CY8C95X0_DEVID:
 335                 return false;
 336         case 0x24 ... 0x27:
 337                 return false;
 338         default:
 339                 return true;
 340         }
 341 }
 342
 343 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
 344 {
 345         switch (reg) {
 346         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 347         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 348         case CY8C95X0_INTMASK:
 349         case CY8C95X0_INVERT:
 350         case CY8C95X0_PWMSEL:
 351         case CY8C95X0_DIRECTION:
 352         case CY8C95X0_DRV_PU:
 353         case CY8C95X0_DRV_PD:
 354         case CY8C95X0_DRV_ODH:
 355         case CY8C95X0_DRV_ODL:
 356         case CY8C95X0_DRV_PP_FAST:
 357         case CY8C95X0_DRV_PP_SLOW:
 358         case CY8C95X0_DRV_HIZ:
 359                 return true;
 360         default:
 361                 return false;
 362         }
 363 }
 364
 365 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
 366 {
 367         switch (reg) {
 368         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 369                 return true;
 370         default:
 371                 return false;
 372         }
 373 }
 374
 375 static const struct reg_default cy8c95x0_reg_defaults[] = {
 376         { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
 377         { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
 378         { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
 379         { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
 380         { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
 381         { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
 382         { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
 383         { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
 384         { CY8C95X0_PORTSEL, 0 },
 385         { CY8C95X0_PWMSEL, 0 },
 386 };
 387
 388 static const struct regmap_config cy8c95x0_i2c_regmap = {
 389         .reg_bits = 8,
 390         .val_bits = 8,
 391
 392         .reg_defaults = cy8c95x0_reg_defaults,
 393         .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
 394
 395         .readable_reg = cy8c95x0_readable_register,
 396         .writeable_reg = cy8c95x0_writeable_register,
 397         .volatile_reg = cy8c95x0_volatile_register,
 398         .precious_reg = cy8c95x0_precious_register,
 399
 400         .cache_type = REGCACHE_FLAT,
 401         .max_register = CY8C95X0_COMMAND,
 402 };
 403
 404 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 405                                     unsigned long *val, unsigned long *mask)
 406 {
 407         DECLARE_BITMAP(tmask, MAX_LINE);
 408         DECLARE_BITMAP(tval, MAX_LINE);
 409         int write_val;
 410         int ret = 0;
 411         int i, off = 0;
 412         u8 bits;
 413
 414         /* Add the 4 bit gap of Gport2 */
 415         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 416         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 417         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 418
 419         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 420         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 421         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 422
 423         mutex_lock(&chip->i2c_lock);
 424         for (i = 0; i < chip->nport; i++) {
 425                 /* Skip over unused banks */
 426                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 427                 if (!bits)
 428                         continue;
 429
 430                 switch (reg) {
 431                 /* Muxed registers */
 432                 case CY8C95X0_INTMASK:
 433                 case CY8C95X0_PWMSEL:
 434                 case CY8C95X0_INVERT:
 435                 case CY8C95X0_DIRECTION:
 436                 case CY8C95X0_DRV_PU:
 437                 case CY8C95X0_DRV_PD:
 438                 case CY8C95X0_DRV_ODH:
 439                 case CY8C95X0_DRV_ODL:
 440                 case CY8C95X0_DRV_PP_FAST:
 441                 case CY8C95X0_DRV_PP_SLOW:
 442                 case CY8C95X0_DRV_HIZ:
 443                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 444                         if (ret < 0)
 445                                 goto out;
 446                         off = reg;
 447                         break;
 448                 /* Direct access registers */
 449                 case CY8C95X0_INPUT:
 450                 case CY8C95X0_OUTPUT:
 451                 case CY8C95X0_INTSTATUS:
 452                         off = reg + i;
 453                         break;
 454                 default:
 455                         ret = -EINVAL;
 456                         goto out;
 457                 }
 458
 459                 write_val = bitmap_get_value8(tval, i * BANK_SZ);
 460
 461                 ret = regmap_update_bits(chip->regmap, off, bits, write_val);
 462                 if (ret < 0)
 463                         goto out;
 464         }
 465 out:
 466         mutex_unlock(&chip->i2c_lock);
 467
 468         if (ret < 0)
 469                 dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret);
 470
 471         return ret;
 472 }
 473
 474 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 475                                    unsigned long *val, unsigned long *mask)
 476 {
 477         DECLARE_BITMAP(tmask, MAX_LINE);
 478         DECLARE_BITMAP(tval, MAX_LINE);
 479         DECLARE_BITMAP(tmp, MAX_LINE);
 480         int read_val;
 481         int ret = 0;
 482         int i, off = 0;
 483         u8 bits;
 484
 485         /* Add the 4 bit gap of Gport2 */
 486         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 487         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 488         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 489
 490         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 491         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 492         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 493
 494         mutex_lock(&chip->i2c_lock);
 495         for (i = 0; i < chip->nport; i++) {
 496                 /* Skip over unused banks */
 497                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 498                 if (!bits)
 499                         continue;
 500
 501                 switch (reg) {
 502                 /* Muxed registers */
 503                 case CY8C95X0_INTMASK:
 504                 case CY8C95X0_PWMSEL:
 505                 case CY8C95X0_INVERT:
 506                 case CY8C95X0_DIRECTION:
 507                 case CY8C95X0_DRV_PU:
 508                 case CY8C95X0_DRV_PD:
 509                 case CY8C95X0_DRV_ODH:
 510                 case CY8C95X0_DRV_ODL:
 511                 case CY8C95X0_DRV_PP_FAST:
 512                 case CY8C95X0_DRV_PP_SLOW:
 513                 case CY8C95X0_DRV_HIZ:
 514                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 515                         if (ret < 0)
 516                                 goto out;
 517                         off = reg;
 518                         break;
 519                 /* Direct access registers */
 520                 case CY8C95X0_INPUT:
 521                 case CY8C95X0_OUTPUT:
 522                 case CY8C95X0_INTSTATUS:
 523                         off = reg + i;
 524                         break;
 525                 default:
 526                         ret = -EINVAL;
 527                         goto out;
 528                 }
 529
 530                 ret = regmap_read(chip->regmap, off, &read_val);
 531                 if (ret < 0)
 532                         goto out;
 533
 534                 read_val &= bits;
 535                 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
 536                 bitmap_set_value8(tval, read_val, i * BANK_SZ);
 537         }
 538
 539         /* Fill the 4 bit gap of Gport2 */
 540         bitmap_shift_right(tmp, tval, 4, MAX_LINE);
 541         bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
 542
 543 out:
 544         mutex_unlock(&chip->i2c_lock);
 545
 546         if (ret < 0)
 547                 dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret);
 548
 549         return ret;
 550 }
 551
 552 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
 553 {
 554         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 555         u8 port = cypress_get_port(chip, off);
 556         u8 bit = cypress_get_pin_mask(chip, off);
 557         int ret;
 558
 559         mutex_lock(&chip->i2c_lock);
 560         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 561         if (ret)
 562                 goto out;
 563
 564         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
 565         if (ret)
 566                 goto out;
 567
 568         if (test_bit(off, chip->push_pull)) {
 569                 /*
 570                  * Disable driving the pin by forcing it to HighZ. Only setting the
 571                  * direction register isn't sufficient in Push-Pull mode.
 572                  */
 573                 ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
 574                 if (ret)
 575                         goto out;
 576
 577                 __clear_bit(off, chip->push_pull);
 578         }
 579
 580 out:
 581         mutex_unlock(&chip->i2c_lock);
 582
 583         return ret;
 584 }
 585
 586 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
 587                                           unsigned int off, int val)
 588 {
 589         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 590         u8 port = cypress_get_port(chip, off);
 591         u8 outreg = CY8C95X0_OUTPUT_(port);
 592         u8 bit = cypress_get_pin_mask(chip, off);
 593         int ret;
 594
 595         /* Set output level */
 596         ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 597         if (ret)
 598                 return ret;
 599
 600         mutex_lock(&chip->i2c_lock);
 601         /* Select port... */
 602         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 603         if (ret)
 604                 goto out;
 605
 606         /* ...then direction */
 607         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, 0);
 608
 609 out:
 610         mutex_unlock(&chip->i2c_lock);
 611
 612         return ret;
 613 }
 614
 615 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
 616 {
 617         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 618         u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off));
 619         u8 bit = cypress_get_pin_mask(chip, off);
 620         u32 reg_val;
 621         int ret;
 622
 623         ret = regmap_read(chip->regmap, inreg, &reg_val);
 624         if (ret < 0) {
 625                 /*
 626                  * NOTE:
 627                  * Diagnostic already emitted; that's all we should
 628                  * do unless gpio_*_value_cansleep() calls become different
 629                  * from their nonsleeping siblings (and report faults).
 630                  */
 631                 return 0;
 632         }
 633
 634         return !!(reg_val & bit);
 635 }
 636
 637 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
 638                                     int val)
 639 {
 640         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 641         u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off));
 642         u8 bit = cypress_get_pin_mask(chip, off);
 643
 644         regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 645 }
 646
 647 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
 648 {
 649         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 650         u8 port = cypress_get_port(chip, off);
 651         u8 bit = cypress_get_pin_mask(chip, off);
 652         u32 reg_val;
 653         int ret;
 654
 655         mutex_lock(&chip->i2c_lock);
 656
 657         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 658         if (ret < 0)
 659                 goto out;
 660
 661         ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, &reg_val);
 662         if (ret < 0)
 663                 goto out;
 664
 665         mutex_unlock(&chip->i2c_lock);
 666
 667         if (reg_val & bit)
 668                 return GPIO_LINE_DIRECTION_IN;
 669
 670         return GPIO_LINE_DIRECTION_OUT;
 671 out:
 672         mutex_unlock(&chip->i2c_lock);
 673         return ret;
 674 }
 675
 676 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
 677                                     unsigned int off,
 678                                     unsigned long *config)
 679 {
 680         enum pin_config_param param = pinconf_to_config_param(*config);
 681         u8 port = cypress_get_port(chip, off);
 682         u8 bit = cypress_get_pin_mask(chip, off);
 683         unsigned int reg;
 684         u32 reg_val;
 685         u16 arg = 0;
 686         int ret;
 687
 688         mutex_lock(&chip->i2c_lock);
 689
 690         /* Select port */
 691         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 692         if (ret < 0)
 693                 goto out;
 694
 695         switch (param) {
 696         case PIN_CONFIG_BIAS_PULL_UP:
 697                 reg = CY8C95X0_DRV_PU;
 698                 break;
 699         case PIN_CONFIG_BIAS_PULL_DOWN:
 700                 reg = CY8C95X0_DRV_PD;
 701                 break;
 702         case PIN_CONFIG_BIAS_DISABLE:
 703                 reg = CY8C95X0_DRV_HIZ;
 704                 break;
 705         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 706                 reg = CY8C95X0_DRV_ODL;
 707                 break;
 708         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 709                 reg = CY8C95X0_DRV_ODH;
 710                 break;
 711         case PIN_CONFIG_DRIVE_PUSH_PULL:
 712                 reg = CY8C95X0_DRV_PP_FAST;
 713                 break;
 714         case PIN_CONFIG_INPUT_ENABLE:
 715                 reg = CY8C95X0_DIRECTION;
 716                 break;
 717         case PIN_CONFIG_MODE_PWM:
 718                 reg = CY8C95X0_PWMSEL;
 719                 break;
 720         case PIN_CONFIG_OUTPUT:
 721                 reg = CY8C95X0_OUTPUT_(port);
 722                 break;
 723         case PIN_CONFIG_OUTPUT_ENABLE:
 724                 reg = CY8C95X0_DIRECTION;
 725                 break;
 726
 727         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 728         case PIN_CONFIG_BIAS_BUS_HOLD:
 729         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 730         case PIN_CONFIG_DRIVE_STRENGTH:
 731         case PIN_CONFIG_DRIVE_STRENGTH_UA:
 732         case PIN_CONFIG_INPUT_DEBOUNCE:
 733         case PIN_CONFIG_INPUT_SCHMITT:
 734         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 735         case PIN_CONFIG_MODE_LOW_POWER:
 736         case PIN_CONFIG_PERSIST_STATE:
 737         case PIN_CONFIG_POWER_SOURCE:
 738         case PIN_CONFIG_SKEW_DELAY:
 739         case PIN_CONFIG_SLEEP_HARDWARE_STATE:
 740         case PIN_CONFIG_SLEW_RATE:
 741         default:
 742                 ret = -ENOTSUPP;
 743                 goto out;
 744         }
 745         /*
 746          * Writing 1 to one of the drive mode registers will automatically
 747          * clear conflicting set bits in the other drive mode registers.
 748          */
 749         ret = regmap_read(chip->regmap, reg, &reg_val);
 750         if (reg_val & bit)
 751                 arg = 1;
 752
 753         *config = pinconf_to_config_packed(param, (u16)arg);
 754 out:
 755         mutex_unlock(&chip->i2c_lock);
 756
 757         return ret;
 758 }
 759
 760 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
 761                                     unsigned int off,
 762                                     unsigned long config)
 763 {
 764         u8 port = cypress_get_port(chip, off);
 765         u8 bit = cypress_get_pin_mask(chip, off);
 766         unsigned long param = pinconf_to_config_param(config);
 767         unsigned int reg;
 768         int ret;
 769
 770         mutex_lock(&chip->i2c_lock);
 771
 772         /* Select port */
 773         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 774         if (ret < 0)
 775                 goto out;
 776
 777         switch (param) {
 778         case PIN_CONFIG_BIAS_PULL_UP:
 779                 __clear_bit(off, chip->push_pull);
 780                 reg = CY8C95X0_DRV_PU;
 781                 break;
 782         case PIN_CONFIG_BIAS_PULL_DOWN:
 783                 __clear_bit(off, chip->push_pull);
 784                 reg = CY8C95X0_DRV_PD;
 785                 break;
 786         case PIN_CONFIG_BIAS_DISABLE:
 787                 __clear_bit(off, chip->push_pull);
 788                 reg = CY8C95X0_DRV_HIZ;
 789                 break;
 790         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 791                 __clear_bit(off, chip->push_pull);
 792                 reg = CY8C95X0_DRV_ODL;
 793                 break;
 794         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 795                 __clear_bit(off, chip->push_pull);
 796                 reg = CY8C95X0_DRV_ODH;
 797                 break;
 798         case PIN_CONFIG_DRIVE_PUSH_PULL:
 799                 __set_bit(off, chip->push_pull);
 800                 reg = CY8C95X0_DRV_PP_FAST;
 801                 break;
 802         case PIN_CONFIG_MODE_PWM:
 803                 reg = CY8C95X0_PWMSEL;
 804                 break;
 805         default:
 806                 ret = -ENOTSUPP;
 807                 goto out;
 808         }
 809         /*
 810          * Writing 1 to one of the drive mode registers will automatically
 811          * clear conflicting set bits in the other drive mode registers.
 812          */
 813         ret = regmap_write_bits(chip->regmap, reg, bit, bit);
 814
 815 out:
 816         mutex_unlock(&chip->i2c_lock);
 817         return ret;
 818 }
 819
 820 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
 821                                       unsigned long *mask, unsigned long *bits)
 822 {
 823         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 824
 825         return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
 826 }
 827
 828 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
 829                                        unsigned long *mask, unsigned long *bits)
 830 {
 831         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 832
 833         cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
 834 }
 835
 836 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
 837 {
 838         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 839         struct device *dev = chip->dev;
 840         int ret;
 841
 842         ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
 843         if (ret)
 844                 dev_err(dev, "failed to add GPIO pin range\n");
 845
 846         return ret;
 847 }
 848
 849 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
 850 {
 851         struct gpio_chip *gc = &chip->gpio_chip;
 852
 853         gc->direction_input  = cy8c95x0_gpio_direction_input;
 854         gc->direction_output = cy8c95x0_gpio_direction_output;
 855         gc->get = cy8c95x0_gpio_get_value;
 856         gc->set = cy8c95x0_gpio_set_value;
 857         gc->get_direction = cy8c95x0_gpio_get_direction;
 858         gc->get_multiple = cy8c95x0_gpio_get_multiple;
 859         gc->set_multiple = cy8c95x0_gpio_set_multiple;
 860         gc->set_config = gpiochip_generic_config,
 861         gc->can_sleep = true;
 862         gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
 863
 864         gc->base = -1;
 865         gc->ngpio = chip->tpin;
 866
 867         gc->parent = chip->dev;
 868         gc->owner = THIS_MODULE;
 869         gc->names = NULL;
 870
 871         gc->label = dev_name(chip->dev);
 872
 873         return devm_gpiochip_add_data(chip->dev, gc, chip);
 874 }
 875
 876 static void cy8c95x0_irq_mask(struct irq_data *d)
 877 {
 878         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 879         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 880         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 881
 882         set_bit(hwirq, chip->irq_mask);
 883         gpiochip_disable_irq(gc, hwirq);
 884 }
 885
 886 static void cy8c95x0_irq_unmask(struct irq_data *d)
 887 {
 888         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 889         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 890         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 891
 892         gpiochip_enable_irq(gc, hwirq);
 893         clear_bit(hwirq, chip->irq_mask);
 894 }
 895
 896 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
 897 {
 898         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 899         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 900
 901         mutex_lock(&chip->irq_lock);
 902 }
 903
 904 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
 905 {
 906         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 907         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 908         DECLARE_BITMAP(ones, MAX_LINE);
 909         DECLARE_BITMAP(irq_mask, MAX_LINE);
 910         DECLARE_BITMAP(reg_direction, MAX_LINE);
 911
 912         bitmap_fill(ones, MAX_LINE);
 913
 914         cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
 915
 916         /* Switch direction to input if needed */
 917         cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
 918         bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
 919         bitmap_complement(irq_mask, irq_mask, MAX_LINE);
 920
 921         /* Look for any newly setup interrupt */
 922         cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
 923
 924         mutex_unlock(&chip->irq_lock);
 925 }
 926
 927 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
 928 {
 929         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 930         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 931         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 932         unsigned int trig_type;
 933
 934         switch (type) {
 935         case IRQ_TYPE_EDGE_RISING:
 936         case IRQ_TYPE_EDGE_FALLING:
 937         case IRQ_TYPE_EDGE_BOTH:
 938                 trig_type = type;
 939                 break;
 940         case IRQ_TYPE_LEVEL_HIGH:
 941                 trig_type = IRQ_TYPE_EDGE_RISING;
 942                 break;
 943         case IRQ_TYPE_LEVEL_LOW:
 944                 trig_type = IRQ_TYPE_EDGE_FALLING;
 945                 break;
 946         default:
 947                 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
 948                 return -EINVAL;
 949         }
 950
 951         assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
 952         assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
 953         assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
 954         assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
 955
 956         return 0;
 957 }
 958
 959 static void cy8c95x0_irq_shutdown(struct irq_data *d)
 960 {
 961         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 962         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 963         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 964
 965         clear_bit(hwirq, chip->irq_trig_raise);
 966         clear_bit(hwirq, chip->irq_trig_fall);
 967         clear_bit(hwirq, chip->irq_trig_low);
 968         clear_bit(hwirq, chip->irq_trig_high);
 969 }
 970
 971 static const struct irq_chip cy8c95x0_irqchip = {
 972         .name = "cy8c95x0-irq",
 973         .irq_mask = cy8c95x0_irq_mask,
 974         .irq_unmask = cy8c95x0_irq_unmask,
 975         .irq_bus_lock = cy8c95x0_irq_bus_lock,
 976         .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
 977         .irq_set_type = cy8c95x0_irq_set_type,
 978         .irq_shutdown = cy8c95x0_irq_shutdown,
 979         .flags = IRQCHIP_IMMUTABLE,
 980         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 981 };
 982
 983 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
 984 {
 985         DECLARE_BITMAP(ones, MAX_LINE);
 986         DECLARE_BITMAP(cur_stat, MAX_LINE);
 987         DECLARE_BITMAP(new_stat, MAX_LINE);
 988         DECLARE_BITMAP(trigger, MAX_LINE);
 989
 990         bitmap_fill(ones, MAX_LINE);
 991
 992         /* Read the current interrupt status from the device */
 993         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
 994                 return false;
 995
 996         /* Check latched inputs */
 997         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
 998                 return false;
 999
1000         /* Apply filter for rising/falling edge selection */
1001         bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
1002                        cur_stat, MAX_LINE);
1003
1004         bitmap_and(pending, new_stat, trigger, MAX_LINE);
1005
1006         return !bitmap_empty(pending, MAX_LINE);
1007 }
1008
1009 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
1010 {
1011         struct cy8c95x0_pinctrl *chip = devid;
1012         struct gpio_chip *gc = &chip->gpio_chip;
1013         DECLARE_BITMAP(pending, MAX_LINE);
1014         int nested_irq, level;
1015         bool ret;
1016
1017         ret = cy8c95x0_irq_pending(chip, pending);
1018         if (!ret)
1019                 return IRQ_RETVAL(0);
1020
1021         ret = 0;
1022         for_each_set_bit(level, pending, MAX_LINE) {
1023                 /* Already accounted for 4bit gap in GPort2 */
1024                 nested_irq = irq_find_mapping(gc->irq.domain, level);
1025
1026                 if (unlikely(nested_irq <= 0)) {
1027                         dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
1028                         continue;
1029                 }
1030
1031                 if (test_bit(level, chip->irq_trig_low))
1032                         while (!cy8c95x0_gpio_get_value(gc, level))
1033                                 handle_nested_irq(nested_irq);
1034                 else if (test_bit(level, chip->irq_trig_high))
1035                         while (cy8c95x0_gpio_get_value(gc, level))
1036                                 handle_nested_irq(nested_irq);
1037                 else
1038                         handle_nested_irq(nested_irq);
1039
1040                 ret = 1;
1041         }
1042
1043         return IRQ_RETVAL(ret);
1044 }
1045
1046 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1047 {
1048         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1049
1050         return chip->tpin;
1051 }
1052
1053 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1054                                                    unsigned int group)
1055 {
1056         return cy8c95x0_groups[group];
1057 }
1058
1059 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1060                                            unsigned int group,
1061                                            const unsigned int **pins,
1062                                            unsigned int *num_pins)
1063 {
1064         *pins = &cy8c9560_pins[group].number;
1065         *num_pins = 1;
1066         return 0;
1067 }
1068
1069 static const char *cy8c95x0_get_fname(unsigned int selector)
1070 {
1071         if (selector == 0)
1072                 return "gpio";
1073         else
1074                 return "pwm";
1075 }
1076
1077 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1078                                   unsigned int pin)
1079 {
1080         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1081         DECLARE_BITMAP(mask, MAX_LINE);
1082         DECLARE_BITMAP(pwm, MAX_LINE);
1083
1084         bitmap_zero(mask, MAX_LINE);
1085         __set_bit(pin, mask);
1086
1087         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1088                 seq_puts(s, "not available");
1089                 return;
1090         }
1091
1092         seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1093 }
1094
1095 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1096         .get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1097         .get_group_name = cy8c95x0_pinctrl_get_group_name,
1098         .get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1099 #ifdef CONFIG_OF
1100         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1101         .dt_free_map = pinconf_generic_dt_free_map,
1102 #endif
1103         .pin_dbg_show = cy8c95x0_pin_dbg_show,
1104 };
1105
1106 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
1107 {
1108         return cy8c95x0_get_fname(selector);
1109 }
1110
1111 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1112 {
1113         return 2;
1114 }
1115
1116 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1117                                         const char * const **groups,
1118                                         unsigned int * const num_groups)
1119 {
1120         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1121
1122         *groups = cy8c95x0_groups;
1123         *num_groups = chip->tpin;
1124         return 0;
1125 }
1126
1127 static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip,
1128                                unsigned int val,
1129                                unsigned long off)
1130 {
1131         u8 port = cypress_get_port(chip, off);
1132         u8 bit = cypress_get_pin_mask(chip, off);
1133         int ret;
1134
1135         /* Select port */
1136         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1137         if (ret < 0)
1138                 return ret;
1139
1140         ret = regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, val ? bit : 0);
1141         if (ret < 0)
1142                 return ret;
1143
1144         /* Set direction to output & set output to 1 so that PWM can work */
1145         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
1146         if (ret < 0)
1147                 return ret;
1148
1149         return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit);
1150 }
1151
1152 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1153                             unsigned int group)
1154 {
1155         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1156         int ret;
1157
1158         mutex_lock(&chip->i2c_lock);
1159         ret = cy8c95x0_pinmux_cfg(chip, selector, group);
1160         mutex_unlock(&chip->i2c_lock);
1161
1162         return ret;
1163 }
1164
1165 static const struct pinmux_ops cy8c95x0_pmxops = {
1166         .get_functions_count = cy8c95x0_get_functions_count,
1167         .get_function_name = cy8c95x0_get_function_name,
1168         .get_function_groups = cy8c95x0_get_function_groups,
1169         .set_mux = cy8c95x0_set_mux,
1170         .strict = true,
1171 };
1172
1173 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1174                                 unsigned long *config)
1175 {
1176         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1177
1178         return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1179 }
1180
1181 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1182                                 unsigned long *configs, unsigned int num_configs)
1183 {
1184         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1185         int ret = 0;
1186         int i;
1187
1188         for (i = 0; i < num_configs; i++) {
1189                 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1190                 if (ret)
1191                         return ret;
1192         }
1193
1194         return ret;
1195 }
1196
1197 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1198         .pin_config_get = cy8c95x0_pinconf_get,
1199         .pin_config_set = cy8c95x0_pinconf_set,
1200         .is_generic = true,
1201 };
1202
1203 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1204 {
1205         struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1206         DECLARE_BITMAP(pending_irqs, MAX_LINE);
1207         int ret;
1208
1209         mutex_init(&chip->irq_lock);
1210
1211         bitmap_zero(pending_irqs, MAX_LINE);
1212
1213         /* Read IRQ status register to clear all pending interrupts */
1214         ret = cy8c95x0_irq_pending(chip, pending_irqs);
1215         if (ret) {
1216                 dev_err(chip->dev, "failed to clear irq status register\n");
1217                 return ret;
1218         }
1219
1220         /* Mask all interrupts */
1221         bitmap_fill(chip->irq_mask, MAX_LINE);
1222
1223         gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1224
1225         /* This will let us handle the parent IRQ in the driver */
1226         girq->parent_handler = NULL;
1227         girq->num_parents = 0;
1228         girq->parents = NULL;
1229         girq->default_type = IRQ_TYPE_NONE;
1230         girq->handler = handle_simple_irq;
1231         girq->threaded = true;
1232
1233         ret = devm_request_threaded_irq(chip->dev, irq,
1234                                         NULL, cy8c95x0_irq_handler,
1235                                         IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1236                                         dev_name(chip->dev), chip);
1237         if (ret) {
1238                 dev_err(chip->dev, "failed to request irq %d\n", irq);
1239                 return ret;
1240         }
1241         dev_info(chip->dev, "Registered threaded IRQ\n");
1242
1243         return 0;
1244 }
1245
1246 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1247 {
1248         struct pinctrl_desc *pd = &chip->pinctrl_desc;
1249
1250         pd->pctlops = &cy8c95x0_pinctrl_ops;
1251         pd->confops = &cy8c95x0_pinconf_ops;
1252         pd->pmxops = &cy8c95x0_pmxops;
1253         pd->name = dev_name(chip->dev);
1254         pd->pins = cy8c9560_pins;
1255         pd->npins = chip->tpin;
1256         pd->owner = THIS_MODULE;
1257
1258         chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1259         if (IS_ERR(chip->pctldev))
1260                 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1261                         "can't register controller\n");
1262
1263         return 0;
1264 }
1265
1266 static int cy8c95x0_detect(struct i2c_client *client,
1267                            struct i2c_board_info *info)
1268 {
1269         struct i2c_adapter *adapter = client->adapter;
1270         int ret;
1271         const char *name;
1272
1273         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1274                 return -ENODEV;
1275
1276         ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1277         if (ret < 0)
1278                 return ret;
1279         switch (ret & GENMASK(7, 4)) {
1280         case 0x20:
1281                 name = cy8c95x0_id[0].name;
1282                 break;
1283         case 0x40:
1284                 name = cy8c95x0_id[1].name;
1285                 break;
1286         case 0x60:
1287                 name = cy8c95x0_id[2].name;
1288                 break;
1289         default:
1290                 return -ENODEV;
1291         }
1292
1293         dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1294         strscpy(info->type, name, I2C_NAME_SIZE);
1295
1296         return 0;
1297 }
1298
1299 static int cy8c95x0_probe(struct i2c_client *client)
1300 {
1301         struct cy8c95x0_pinctrl *chip;
1302         struct regulator *reg;
1303         int ret;
1304
1305         chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1306         if (!chip)
1307                 return -ENOMEM;
1308
1309         chip->dev = &client->dev;
1310
1311         /* Set the device type */
1312         chip->driver_data = (unsigned long)device_get_match_data(&client->dev);
1313         if (!chip->driver_data)
1314                 chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data;
1315         if (!chip->driver_data)
1316                 return -ENODEV;
1317
1318         i2c_set_clientdata(client, chip);
1319
1320         chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1321         chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1322
1323         switch (chip->tpin) {
1324         case 20:
1325                 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1326                 break;
1327         case 40:
1328                 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1329                 break;
1330         case 60:
1331                 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1332                 break;
1333         default:
1334                 return -ENODEV;
1335         }
1336
1337         reg = devm_regulator_get(&client->dev, "vdd");
1338         if (IS_ERR(reg)) {
1339                 if (PTR_ERR(reg) == -EPROBE_DEFER)
1340                         return -EPROBE_DEFER;
1341         } else {
1342                 ret = regulator_enable(reg);
1343                 if (ret) {
1344                         dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1345                         return ret;
1346                 }
1347                 chip->regulator = reg;
1348         }
1349
1350         chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1351         if (IS_ERR(chip->regmap)) {
1352                 ret = PTR_ERR(chip->regmap);
1353                 goto err_exit;
1354         }
1355
1356         bitmap_zero(chip->push_pull, MAX_LINE);
1357         bitmap_zero(chip->shiftmask, MAX_LINE);
1358         bitmap_set(chip->shiftmask, 0, 20);
1359         mutex_init(&chip->i2c_lock);
1360
1361         if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1362                 ret = cy8c95x0_acpi_get_irq(&client->dev);
1363                 if (ret > 0)
1364                         client->irq = ret;
1365         }
1366
1367         if (client->irq) {
1368                 ret = cy8c95x0_irq_setup(chip, client->irq);
1369                 if (ret)
1370                         goto err_exit;
1371         }
1372
1373         ret = cy8c95x0_setup_pinctrl(chip);
1374         if (ret)
1375                 goto err_exit;
1376
1377         ret = cy8c95x0_setup_gpiochip(chip);
1378         if (ret)
1379                 goto err_exit;
1380
1381         return 0;
1382
1383 err_exit:
1384         if (!IS_ERR_OR_NULL(chip->regulator))
1385                 regulator_disable(chip->regulator);
1386         return ret;
1387 }
1388
1389 static void cy8c95x0_remove(struct i2c_client *client)
1390 {
1391         struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1392
1393         if (!IS_ERR_OR_NULL(chip->regulator))
1394                 regulator_disable(chip->regulator);
1395 }
1396
1397 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1398         { "INT3490", 40, },
1399         { }
1400 };
1401 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1402
1403 static struct i2c_driver cy8c95x0_driver = {
1404         .driver = {
1405                 .name   = "cy8c95x0-pinctrl",
1406                 .of_match_table = cy8c95x0_dt_ids,
1407                 .acpi_match_table = cy8c95x0_acpi_ids,
1408         },
1409         .probe_new      = cy8c95x0_probe,
1410         .remove         = cy8c95x0_remove,
1411         .id_table       = cy8c95x0_id,
1412         .detect         = cy8c95x0_detect,
1413 };
1414 module_i2c_driver(cy8c95x0_driver);
1415
1416 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1417 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1418 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1419 MODULE_LICENSE("GPL");