2 * Driver for the Atmel PIO4 controller
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/gpio/driver.h>
19 /* FIXME: needed for gpio_to_irq(), get rid of this */
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
23 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/slab.h>
33 #include "pinctrl-utils.h"
37 * In order to not introduce confusion between Atmel PIO groups and pinctrl
38 * framework groups, Atmel PIO groups will be called banks, line is kept to
39 * designed the pin id into this bank.
42 #define ATMEL_PIO_MSKR 0x0000
43 #define ATMEL_PIO_CFGR 0x0004
44 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
45 #define ATMEL_PIO_DIR_MASK BIT(8)
46 #define ATMEL_PIO_PUEN_MASK BIT(9)
47 #define ATMEL_PIO_PDEN_MASK BIT(10)
48 #define ATMEL_PIO_IFEN_MASK BIT(12)
49 #define ATMEL_PIO_IFSCEN_MASK BIT(13)
50 #define ATMEL_PIO_OPD_MASK BIT(14)
51 #define ATMEL_PIO_SCHMITT_MASK BIT(15)
52 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
53 #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
54 #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
55 #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
56 #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
57 #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
58 #define ATMEL_PIO_PDSR 0x0008
59 #define ATMEL_PIO_LOCKSR 0x000C
60 #define ATMEL_PIO_SODR 0x0010
61 #define ATMEL_PIO_CODR 0x0014
62 #define ATMEL_PIO_ODSR 0x0018
63 #define ATMEL_PIO_IER 0x0020
64 #define ATMEL_PIO_IDR 0x0024
65 #define ATMEL_PIO_IMR 0x0028
66 #define ATMEL_PIO_ISR 0x002C
67 #define ATMEL_PIO_IOFR 0x003C
69 #define ATMEL_PIO_NPINS_PER_BANK 32
70 #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
71 #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
72 #define ATMEL_PIO_BANK_OFFSET 0x40
74 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
75 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
76 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
78 struct atmel_pioctrl_data {
97 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
98 * @reg_base: base address of the controller.
99 * @clk: clock of the controller.
100 * @nbanks: number of PIO groups, it can vary depending on the SoC.
101 * @pinctrl_dev: pinctrl device registered.
102 * @groups: groups table to provide group name and pin in the group to pinctrl.
103 * @group_names: group names table to provide all the group/pin names to
105 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
106 * fields are set at probe time. Other ones are set when parsing dt
108 * @npins: number of pins.
109 * @gpio_chip: gpio chip registered.
110 * @irq_domain: irq domain for the gpio controller.
111 * @irqs: table containing the hw irq number of the bank. The index of the
112 * table is the bank id.
113 * @dev: device entry for the Atmel PIO controller.
114 * @node: node of the Atmel PIO controller.
116 struct atmel_pioctrl {
117 void __iomem *reg_base;
120 struct pinctrl_dev *pinctrl_dev;
121 struct atmel_group *groups;
122 const char * const *group_names;
123 struct atmel_pin **pins;
125 struct gpio_chip *gpio_chip;
126 struct irq_domain *irq_domain;
128 unsigned *pm_wakeup_sources;
132 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
133 } *pm_suspend_backup;
135 struct device_node *node;
138 static const char * const atmel_functions[] = {
139 "GPIO", "A", "B", "C", "D", "E", "F", "G"
143 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
144 unsigned int bank, unsigned int reg)
146 return readl_relaxed(atmel_pioctrl->reg_base
147 + ATMEL_PIO_BANK_OFFSET * bank + reg);
150 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
151 unsigned int bank, unsigned int reg,
154 writel_relaxed(val, atmel_pioctrl->reg_base
155 + ATMEL_PIO_BANK_OFFSET * bank + reg);
158 static void atmel_gpio_irq_ack(struct irq_data *d)
161 * Nothing to do, interrupt is cleared when reading the status
166 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
168 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
169 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
172 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
174 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
175 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
178 case IRQ_TYPE_EDGE_RISING:
179 irq_set_handler_locked(d, handle_edge_irq);
180 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
182 case IRQ_TYPE_EDGE_FALLING:
183 irq_set_handler_locked(d, handle_edge_irq);
184 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
186 case IRQ_TYPE_EDGE_BOTH:
187 irq_set_handler_locked(d, handle_edge_irq);
188 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
190 case IRQ_TYPE_LEVEL_LOW:
191 irq_set_handler_locked(d, handle_level_irq);
192 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
194 case IRQ_TYPE_LEVEL_HIGH:
195 irq_set_handler_locked(d, handle_level_irq);
196 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
203 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
208 static void atmel_gpio_irq_mask(struct irq_data *d)
210 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
211 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
213 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
217 static void atmel_gpio_irq_unmask(struct irq_data *d)
219 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
220 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
222 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
226 #ifdef CONFIG_PM_SLEEP
228 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
230 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
231 int bank = ATMEL_PIO_BANK(d->hwirq);
232 int line = ATMEL_PIO_LINE(d->hwirq);
234 /* The gpio controller has one interrupt line per bank. */
235 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
238 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
240 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
245 #define atmel_gpio_irq_set_wake NULL
246 #endif /* CONFIG_PM_SLEEP */
248 static struct irq_chip atmel_gpio_irq_chip = {
250 .irq_ack = atmel_gpio_irq_ack,
251 .irq_mask = atmel_gpio_irq_mask,
252 .irq_unmask = atmel_gpio_irq_unmask,
253 .irq_set_type = atmel_gpio_irq_set_type,
254 .irq_set_wake = atmel_gpio_irq_set_wake,
257 static void atmel_gpio_irq_handler(struct irq_desc *desc)
259 unsigned int irq = irq_desc_get_irq(desc);
260 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
261 struct irq_chip *chip = irq_desc_get_chip(desc);
265 /* Find from which bank is the irq received. */
266 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
267 if (atmel_pioctrl->irqs[n] == irq) {
274 dev_err(atmel_pioctrl->dev,
275 "no bank associated to irq %u\n", irq);
279 chained_irq_enter(chip, desc);
282 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
284 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
289 for_each_set_bit(n, &isr, BITS_PER_LONG)
290 generic_handle_irq(gpio_to_irq(bank *
291 ATMEL_PIO_NPINS_PER_BANK + n));
294 chained_irq_exit(chip, desc);
297 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
299 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
300 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
303 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
305 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
306 reg &= ~ATMEL_PIO_DIR_MASK;
307 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
312 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
314 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
315 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
318 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
320 return !!(reg & BIT(pin->line));
323 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
326 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
327 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
330 atmel_gpio_write(atmel_pioctrl, pin->bank,
331 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
334 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
336 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
337 reg |= ATMEL_PIO_DIR_MASK;
338 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
343 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
345 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
346 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
348 atmel_gpio_write(atmel_pioctrl, pin->bank,
349 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
353 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
355 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
357 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
360 static struct gpio_chip atmel_gpio_chip = {
361 .direction_input = atmel_gpio_direction_input,
362 .get = atmel_gpio_get,
363 .direction_output = atmel_gpio_direction_output,
364 .set = atmel_gpio_set,
365 .to_irq = atmel_gpio_to_irq,
369 /* --- PINCTRL --- */
370 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
373 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
374 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
375 unsigned line = atmel_pioctrl->pins[pin_id]->line;
376 void __iomem *addr = atmel_pioctrl->reg_base
377 + bank * ATMEL_PIO_BANK_OFFSET;
379 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
380 /* Have to set MSKR first, to access the right pin CFGR. */
383 return readl_relaxed(addr + ATMEL_PIO_CFGR);
386 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
387 unsigned pin_id, u32 conf)
389 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
390 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
391 unsigned line = atmel_pioctrl->pins[pin_id]->line;
392 void __iomem *addr = atmel_pioctrl->reg_base
393 + bank * ATMEL_PIO_BANK_OFFSET;
395 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
396 /* Have to set MSKR first, to access the right pin CFGR. */
398 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
401 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
403 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
405 return atmel_pioctrl->npins;
408 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
411 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
413 return atmel_pioctrl->groups[selector].name;
416 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
417 unsigned selector, const unsigned **pins,
420 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
422 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
428 static struct atmel_group *
429 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
431 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
434 for (i = 0; i < atmel_pioctrl->npins; i++) {
435 struct atmel_group *grp = atmel_pioctrl->groups + i;
444 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
445 struct device_node *np,
446 u32 pinfunc, const char **grp_name,
447 const char **func_name)
449 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
450 unsigned pin_id, func_id;
451 struct atmel_group *grp;
453 pin_id = ATMEL_GET_PIN_NO(pinfunc);
454 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
456 if (func_id >= ARRAY_SIZE(atmel_functions))
459 *func_name = atmel_functions[func_id];
461 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
464 *grp_name = grp->name;
466 atmel_pioctrl->pins[pin_id]->mux = func_id;
467 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
468 /* Want the device name not the group one. */
469 if (np->parent == atmel_pioctrl->node)
470 atmel_pioctrl->pins[pin_id]->device = np->name;
472 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
477 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
478 struct device_node *np,
479 struct pinctrl_map **map,
480 unsigned *reserved_maps,
483 unsigned num_pins, num_configs, reserve;
484 unsigned long *configs;
485 struct property *pins;
489 pins = of_find_property(np, "pinmux", NULL);
493 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
496 dev_err(pctldev->dev, "%pOF: could not parse node property\n",
501 num_pins = pins->length / sizeof(u32);
503 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
509 * Reserve maps, at least there is a mux map and an optional conf
516 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
521 for (i = 0; i < num_pins; i++) {
522 const char *group, *func;
524 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
528 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
533 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
537 ret = pinctrl_utils_add_map_configs(pctldev, map,
538 reserved_maps, num_maps, group,
539 configs, num_configs,
540 PIN_MAP_TYPE_CONFIGS_GROUP);
551 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
552 struct device_node *np_config,
553 struct pinctrl_map **map,
556 struct device_node *np;
557 unsigned reserved_maps;
565 * If all the pins of a device have the same configuration (or no one),
566 * it is useless to add a subnode, so directly parse node referenced by
569 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
570 &reserved_maps, num_maps);
572 for_each_child_of_node(np_config, np) {
573 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
574 &reserved_maps, num_maps);
583 pinctrl_utils_free_map(pctldev, *map, *num_maps);
584 dev_err(pctldev->dev, "can't create maps for node %pOF\n",
591 static const struct pinctrl_ops atmel_pctlops = {
592 .get_groups_count = atmel_pctl_get_groups_count,
593 .get_group_name = atmel_pctl_get_group_name,
594 .get_group_pins = atmel_pctl_get_group_pins,
595 .dt_node_to_map = atmel_pctl_dt_node_to_map,
596 .dt_free_map = pinctrl_utils_free_map,
599 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
601 return ARRAY_SIZE(atmel_functions);
604 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
607 return atmel_functions[selector];
610 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
612 const char * const **groups,
613 unsigned * const num_groups)
615 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
617 *groups = atmel_pioctrl->group_names;
618 *num_groups = atmel_pioctrl->npins;
623 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
627 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
631 dev_dbg(pctldev->dev, "enable function %s group %s\n",
632 atmel_functions[function], atmel_pioctrl->groups[group].name);
634 pin = atmel_pioctrl->groups[group].pin;
635 conf = atmel_pin_config_read(pctldev, pin);
636 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
637 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
638 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
639 atmel_pin_config_write(pctldev, pin, conf);
644 static const struct pinmux_ops atmel_pmxops = {
645 .get_functions_count = atmel_pmx_get_functions_count,
646 .get_function_name = atmel_pmx_get_function_name,
647 .get_function_groups = atmel_pmx_get_function_groups,
648 .set_mux = atmel_pmx_set_mux,
651 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
653 unsigned long *config)
655 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
656 unsigned param = pinconf_to_config_param(*config), arg = 0;
657 struct atmel_group *grp = atmel_pioctrl->groups + group;
658 unsigned pin_id = grp->pin;
661 res = atmel_pin_config_read(pctldev, pin_id);
664 case PIN_CONFIG_BIAS_PULL_UP:
665 if (!(res & ATMEL_PIO_PUEN_MASK))
669 case PIN_CONFIG_BIAS_PULL_DOWN:
670 if ((res & ATMEL_PIO_PUEN_MASK) ||
671 (!(res & ATMEL_PIO_PDEN_MASK)))
675 case PIN_CONFIG_BIAS_DISABLE:
676 if ((res & ATMEL_PIO_PUEN_MASK) ||
677 ((res & ATMEL_PIO_PDEN_MASK)))
681 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
682 if (!(res & ATMEL_PIO_OPD_MASK))
686 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
687 if (!(res & ATMEL_PIO_SCHMITT_MASK))
695 *config = pinconf_to_config_packed(param, arg);
699 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
701 unsigned long *configs,
702 unsigned num_configs)
704 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
705 struct atmel_group *grp = atmel_pioctrl->groups + group;
706 unsigned bank, pin, pin_id = grp->pin;
710 conf = atmel_pin_config_read(pctldev, pin_id);
712 for (i = 0; i < num_configs; i++) {
713 unsigned param = pinconf_to_config_param(configs[i]);
714 unsigned arg = pinconf_to_config_argument(configs[i]);
716 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
717 __func__, pin_id, configs[i]);
720 case PIN_CONFIG_BIAS_DISABLE:
721 conf &= (~ATMEL_PIO_PUEN_MASK);
722 conf &= (~ATMEL_PIO_PDEN_MASK);
724 case PIN_CONFIG_BIAS_PULL_UP:
725 conf |= ATMEL_PIO_PUEN_MASK;
726 conf &= (~ATMEL_PIO_PDEN_MASK);
728 case PIN_CONFIG_BIAS_PULL_DOWN:
729 conf |= ATMEL_PIO_PDEN_MASK;
730 conf &= (~ATMEL_PIO_PUEN_MASK);
732 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
734 conf &= (~ATMEL_PIO_OPD_MASK);
736 conf |= ATMEL_PIO_OPD_MASK;
738 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
740 conf |= ATMEL_PIO_SCHMITT_MASK;
742 conf &= (~ATMEL_PIO_SCHMITT_MASK);
744 case PIN_CONFIG_INPUT_DEBOUNCE:
746 conf &= (~ATMEL_PIO_IFEN_MASK);
747 conf &= (~ATMEL_PIO_IFSCEN_MASK);
750 * We don't care about the debounce value for several reasons:
751 * - can't have different debounce periods inside a same group,
752 * - the register to configure this period is a secure register.
753 * The debouncing filter can filter a pulse with a duration of less
754 * than 1/2 slow clock period.
756 conf |= ATMEL_PIO_IFEN_MASK;
757 conf |= ATMEL_PIO_IFSCEN_MASK;
760 case PIN_CONFIG_OUTPUT:
761 conf |= ATMEL_PIO_DIR_MASK;
762 bank = ATMEL_PIO_BANK(pin_id);
763 pin = ATMEL_PIO_LINE(pin_id);
767 writel_relaxed(mask, atmel_pioctrl->reg_base +
768 bank * ATMEL_PIO_BANK_OFFSET +
771 writel_relaxed(mask, atmel_pioctrl->reg_base +
772 bank * ATMEL_PIO_BANK_OFFSET +
777 dev_warn(pctldev->dev,
778 "unsupported configuration parameter: %u\n",
784 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
785 atmel_pin_config_write(pctldev, pin_id, conf);
790 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
791 struct seq_file *s, unsigned pin_id)
793 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
796 if (!atmel_pioctrl->pins[pin_id]->device)
799 if (atmel_pioctrl->pins[pin_id])
800 seq_printf(s, " (%s, ioset %u) ",
801 atmel_pioctrl->pins[pin_id]->device,
802 atmel_pioctrl->pins[pin_id]->ioset);
804 conf = atmel_pin_config_read(pctldev, pin_id);
805 if (conf & ATMEL_PIO_PUEN_MASK)
806 seq_printf(s, "%s ", "pull-up");
807 if (conf & ATMEL_PIO_PDEN_MASK)
808 seq_printf(s, "%s ", "pull-down");
809 if (conf & ATMEL_PIO_IFEN_MASK)
810 seq_printf(s, "%s ", "debounce");
811 if (conf & ATMEL_PIO_OPD_MASK)
812 seq_printf(s, "%s ", "open-drain");
813 if (conf & ATMEL_PIO_SCHMITT_MASK)
814 seq_printf(s, "%s ", "schmitt");
817 static const struct pinconf_ops atmel_confops = {
818 .pin_config_group_get = atmel_conf_pin_config_group_get,
819 .pin_config_group_set = atmel_conf_pin_config_group_set,
820 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
823 static struct pinctrl_desc atmel_pinctrl_desc = {
824 .name = "atmel_pinctrl",
825 .confops = &atmel_confops,
826 .pctlops = &atmel_pctlops,
827 .pmxops = &atmel_pmxops,
830 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
832 struct platform_device *pdev = to_platform_device(dev);
833 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
837 * For each bank, save IMR to restore it later and disable all GPIO
838 * interrupts excepting the ones marked as wakeup sources.
840 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
841 atmel_pioctrl->pm_suspend_backup[i].imr =
842 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
843 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
844 ~atmel_pioctrl->pm_wakeup_sources[i]);
845 atmel_pioctrl->pm_suspend_backup[i].odsr =
846 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
847 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
848 atmel_gpio_write(atmel_pioctrl, i,
849 ATMEL_PIO_MSKR, BIT(j));
850 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
851 atmel_gpio_read(atmel_pioctrl, i,
859 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
861 struct platform_device *pdev = to_platform_device(dev);
862 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
865 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
866 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
867 atmel_pioctrl->pm_suspend_backup[i].imr);
868 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
869 atmel_pioctrl->pm_suspend_backup[i].odsr);
870 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
871 atmel_gpio_write(atmel_pioctrl, i,
872 ATMEL_PIO_MSKR, BIT(j));
873 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
874 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
881 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
882 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
886 * The number of banks can be different from a SoC to another one.
887 * We can have up to 16 banks.
889 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
893 static const struct of_device_id atmel_pctrl_of_match[] = {
895 .compatible = "atmel,sama5d2-pinctrl",
896 .data = &atmel_sama5d2_pioctrl_data,
902 static int atmel_pinctrl_probe(struct platform_device *pdev)
904 struct device *dev = &pdev->dev;
905 struct pinctrl_pin_desc *pin_desc;
906 const char **group_names;
907 const struct of_device_id *match;
909 struct resource *res;
910 struct atmel_pioctrl *atmel_pioctrl;
911 struct atmel_pioctrl_data *atmel_pioctrl_data;
913 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
916 atmel_pioctrl->dev = dev;
917 atmel_pioctrl->node = dev->of_node;
918 platform_set_drvdata(pdev, atmel_pioctrl);
920 match = of_match_node(atmel_pctrl_of_match, dev->of_node);
922 dev_err(dev, "unknown compatible string\n");
925 atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data;
926 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
927 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
931 dev_err(dev, "unable to get atmel pinctrl resource\n");
934 atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
935 if (IS_ERR(atmel_pioctrl->reg_base))
938 atmel_pioctrl->clk = devm_clk_get(dev, NULL);
939 if (IS_ERR(atmel_pioctrl->clk)) {
940 dev_err(dev, "failed to get clock\n");
941 return PTR_ERR(atmel_pioctrl->clk);
944 atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins)
945 * atmel_pioctrl->npins, GFP_KERNEL);
946 if (!atmel_pioctrl->pins)
949 pin_desc = devm_kzalloc(dev, sizeof(*pin_desc)
950 * atmel_pioctrl->npins, GFP_KERNEL);
953 atmel_pinctrl_desc.pins = pin_desc;
954 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
956 /* One pin is one group since a pin can achieve all functions. */
957 group_names = devm_kzalloc(dev, sizeof(*group_names)
958 * atmel_pioctrl->npins, GFP_KERNEL);
961 atmel_pioctrl->group_names = group_names;
963 atmel_pioctrl->groups = devm_kzalloc(&pdev->dev,
964 sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins,
966 if (!atmel_pioctrl->groups)
968 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
969 struct atmel_group *group = atmel_pioctrl->groups + i;
970 unsigned bank = ATMEL_PIO_BANK(i);
971 unsigned line = ATMEL_PIO_LINE(i);
973 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
974 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
975 if (!atmel_pioctrl->pins[i])
978 atmel_pioctrl->pins[i]->pin_id = i;
979 atmel_pioctrl->pins[i]->bank = bank;
980 atmel_pioctrl->pins[i]->line = line;
982 pin_desc[i].number = i;
983 /* Pin naming convention: P(bank_name)(bank_pin_number). */
984 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
987 group->name = group_names[i] = pin_desc[i].name;
988 group->pin = pin_desc[i].number;
990 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
993 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
994 atmel_pioctrl->gpio_chip->of_node = dev->of_node;
995 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
996 atmel_pioctrl->gpio_chip->label = dev_name(dev);
997 atmel_pioctrl->gpio_chip->parent = dev;
998 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1000 atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev,
1001 sizeof(*atmel_pioctrl->pm_wakeup_sources)
1002 * atmel_pioctrl->nbanks, GFP_KERNEL);
1003 if (!atmel_pioctrl->pm_wakeup_sources)
1006 atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev,
1007 sizeof(*atmel_pioctrl->pm_suspend_backup)
1008 * atmel_pioctrl->nbanks, GFP_KERNEL);
1009 if (!atmel_pioctrl->pm_suspend_backup)
1012 atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs)
1013 * atmel_pioctrl->nbanks, GFP_KERNEL);
1014 if (!atmel_pioctrl->irqs)
1017 /* There is one controller but each bank has its own irq line. */
1018 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1019 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1021 dev_err(dev, "missing irq resource for group %c\n",
1025 atmel_pioctrl->irqs[i] = res->start;
1026 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1027 irq_set_handler_data(res->start, atmel_pioctrl);
1028 dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1031 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1032 atmel_pioctrl->gpio_chip->ngpio,
1033 &irq_domain_simple_ops, NULL);
1034 if (!atmel_pioctrl->irq_domain) {
1035 dev_err(dev, "can't add the irq domain\n");
1038 atmel_pioctrl->irq_domain->name = "atmel gpio";
1040 for (i = 0; i < atmel_pioctrl->npins; i++) {
1041 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1043 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1045 irq_set_chip_data(irq, atmel_pioctrl);
1047 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1051 ret = clk_prepare_enable(atmel_pioctrl->clk);
1053 dev_err(dev, "failed to prepare and enable clock\n");
1054 goto clk_prepare_enable_error;
1057 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1058 &atmel_pinctrl_desc,
1060 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1061 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1062 dev_err(dev, "pinctrl registration failed\n");
1066 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1068 dev_err(dev, "failed to add gpiochip\n");
1072 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1073 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1075 dev_err(dev, "failed to add gpio pin range\n");
1076 goto gpiochip_add_pin_range_error;
1079 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1083 gpiochip_add_pin_range_error:
1084 gpiochip_remove(atmel_pioctrl->gpio_chip);
1087 clk_disable_unprepare(atmel_pioctrl->clk);
1089 clk_prepare_enable_error:
1090 irq_domain_remove(atmel_pioctrl->irq_domain);
1095 static struct platform_driver atmel_pinctrl_driver = {
1097 .name = "pinctrl-at91-pio4",
1098 .of_match_table = atmel_pctrl_of_match,
1099 .pm = &atmel_pctrl_pm_ops,
1100 .suppress_bind_attrs = true,
1102 .probe = atmel_pinctrl_probe,
1104 builtin_platform_driver(atmel_pinctrl_driver);