drivers/pinctrl/pinctrl-amd.h

   1 /*
   2  * GPIO driver for AMD
   3  *
   4  * Copyright (c) 2014,2015 Ken Xue <Ken.Xue@amd.com>
   5  *              Jeff Wu <Jeff.Wu@amd.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  */
  12
  13 #ifndef _PINCTRL_AMD_H
  14 #define _PINCTRL_AMD_H
  15
  16 #define AMD_GPIO_PINS_PER_BANK  64
  17
  18 #define AMD_GPIO_PINS_BANK0     63
  19 #define AMD_GPIO_PINS_BANK1     64
  20 #define AMD_GPIO_PINS_BANK2     56
  21 #define AMD_GPIO_PINS_BANK3     32
  22
  23 #define WAKE_INT_MASTER_REG 0xfc
  24 #define INTERNAL_GPIO0_DEBOUNCE (1 << 15)
  25 #define EOI_MASK (1 << 29)
  26
  27 #define WAKE_INT_STATUS_REG0 0x2f8
  28 #define WAKE_INT_STATUS_REG1 0x2fc
  29
  30 #define DB_TMR_OUT_OFF                  0
  31 #define DB_TMR_OUT_UNIT_OFF             4
  32 #define DB_CNTRL_OFF                    5
  33 #define DB_TMR_LARGE_OFF                7
  34 #define LEVEL_TRIG_OFF                  8
  35 #define ACTIVE_LEVEL_OFF                9
  36 #define INTERRUPT_ENABLE_OFF            11
  37 #define INTERRUPT_MASK_OFF              12
  38 #define WAKE_CNTRL_OFF_S0I3             13
  39 #define WAKE_CNTRL_OFF_S3               14
  40 #define WAKE_CNTRL_OFF_S4               15
  41 #define PIN_STS_OFF                     16
  42 #define DRV_STRENGTH_SEL_OFF            17
  43 #define PULL_UP_SEL_OFF                 19
  44 #define PULL_UP_ENABLE_OFF              20
  45 #define PULL_DOWN_ENABLE_OFF            21
  46 #define OUTPUT_VALUE_OFF                22
  47 #define OUTPUT_ENABLE_OFF               23
  48 #define SW_CNTRL_IN_OFF                 24
  49 #define SW_CNTRL_EN_OFF                 25
  50 #define INTERRUPT_STS_OFF               28
  51 #define WAKE_STS_OFF                    29
  52
  53 #define DB_TMR_OUT_MASK 0xFUL
  54 #define DB_CNTRl_MASK   0x3UL
  55 #define ACTIVE_LEVEL_MASK       0x3UL
  56 #define DRV_STRENGTH_SEL_MASK   0x3UL
  57
  58 #define ACTIVE_LEVEL_HIGH       0x0UL
  59 #define ACTIVE_LEVEL_LOW        0x1UL
  60 #define ACTIVE_LEVEL_BOTH       0x2UL
  61
  62 #define DB_TYPE_NO_DEBOUNCE               0x0UL
  63 #define DB_TYPE_PRESERVE_LOW_GLITCH       0x1UL
  64 #define DB_TYPE_PRESERVE_HIGH_GLITCH      0x2UL
  65 #define DB_TYPE_REMOVE_GLITCH             0x3UL
  66
  67 #define EDGE_TRAGGER    0x0UL
  68 #define LEVEL_TRIGGER   0x1UL
  69
  70 #define ACTIVE_HIGH     0x0UL
  71 #define ACTIVE_LOW      0x1UL
  72 #define BOTH_EADGE      0x2UL
  73
  74 #define ENABLE_INTERRUPT        0x1UL
  75 #define DISABLE_INTERRUPT       0x0UL
  76
  77 #define ENABLE_INTERRUPT_MASK   0x0UL
  78 #define DISABLE_INTERRUPT_MASK  0x1UL
  79
  80 #define CLR_INTR_STAT   0x1UL
  81
  82 struct amd_pingroup {
  83         const char *name;
  84         const unsigned *pins;
  85         unsigned npins;
  86 };
  87
  88 struct amd_function {
  89         const char *name;
  90         const char * const *groups;
  91         unsigned ngroups;
  92 };
  93
  94 struct amd_gpio {
  95         raw_spinlock_t          lock;
  96         void __iomem            *base;
  97
  98         const struct amd_pingroup *groups;
  99         u32 ngroups;
 100         struct pinctrl_dev *pctrl;
 101         struct gpio_chip        gc;
 102         unsigned int            hwbank_num;
 103         struct resource         *res;
 104         struct platform_device  *pdev;
 105         u32                     *saved_regs;
 106 };
 107
 108 /*  KERNCZ configuration*/
 109 static const struct pinctrl_pin_desc kerncz_pins[] = {
 110         PINCTRL_PIN(0, "GPIO_0"),
 111         PINCTRL_PIN(1, "GPIO_1"),
 112         PINCTRL_PIN(2, "GPIO_2"),
 113         PINCTRL_PIN(3, "GPIO_3"),
 114         PINCTRL_PIN(4, "GPIO_4"),
 115         PINCTRL_PIN(5, "GPIO_5"),
 116         PINCTRL_PIN(6, "GPIO_6"),
 117         PINCTRL_PIN(7, "GPIO_7"),
 118         PINCTRL_PIN(8, "GPIO_8"),
 119         PINCTRL_PIN(9, "GPIO_9"),
 120         PINCTRL_PIN(10, "GPIO_10"),
 121         PINCTRL_PIN(11, "GPIO_11"),
 122         PINCTRL_PIN(12, "GPIO_12"),
 123         PINCTRL_PIN(13, "GPIO_13"),
 124         PINCTRL_PIN(14, "GPIO_14"),
 125         PINCTRL_PIN(15, "GPIO_15"),
 126         PINCTRL_PIN(16, "GPIO_16"),
 127         PINCTRL_PIN(17, "GPIO_17"),
 128         PINCTRL_PIN(18, "GPIO_18"),
 129         PINCTRL_PIN(19, "GPIO_19"),
 130         PINCTRL_PIN(20, "GPIO_20"),
 131         PINCTRL_PIN(23, "GPIO_23"),
 132         PINCTRL_PIN(24, "GPIO_24"),
 133         PINCTRL_PIN(25, "GPIO_25"),
 134         PINCTRL_PIN(26, "GPIO_26"),
 135         PINCTRL_PIN(39, "GPIO_39"),
 136         PINCTRL_PIN(40, "GPIO_40"),
 137         PINCTRL_PIN(43, "GPIO_42"),
 138         PINCTRL_PIN(46, "GPIO_46"),
 139         PINCTRL_PIN(47, "GPIO_47"),
 140         PINCTRL_PIN(48, "GPIO_48"),
 141         PINCTRL_PIN(49, "GPIO_49"),
 142         PINCTRL_PIN(50, "GPIO_50"),
 143         PINCTRL_PIN(51, "GPIO_51"),
 144         PINCTRL_PIN(52, "GPIO_52"),
 145         PINCTRL_PIN(53, "GPIO_53"),
 146         PINCTRL_PIN(54, "GPIO_54"),
 147         PINCTRL_PIN(55, "GPIO_55"),
 148         PINCTRL_PIN(56, "GPIO_56"),
 149         PINCTRL_PIN(57, "GPIO_57"),
 150         PINCTRL_PIN(58, "GPIO_58"),
 151         PINCTRL_PIN(59, "GPIO_59"),
 152         PINCTRL_PIN(60, "GPIO_60"),
 153         PINCTRL_PIN(61, "GPIO_61"),
 154         PINCTRL_PIN(62, "GPIO_62"),
 155         PINCTRL_PIN(64, "GPIO_64"),
 156         PINCTRL_PIN(65, "GPIO_65"),
 157         PINCTRL_PIN(66, "GPIO_66"),
 158         PINCTRL_PIN(68, "GPIO_68"),
 159         PINCTRL_PIN(69, "GPIO_69"),
 160         PINCTRL_PIN(70, "GPIO_70"),
 161         PINCTRL_PIN(71, "GPIO_71"),
 162         PINCTRL_PIN(72, "GPIO_72"),
 163         PINCTRL_PIN(74, "GPIO_74"),
 164         PINCTRL_PIN(75, "GPIO_75"),
 165         PINCTRL_PIN(76, "GPIO_76"),
 166         PINCTRL_PIN(84, "GPIO_84"),
 167         PINCTRL_PIN(85, "GPIO_85"),
 168         PINCTRL_PIN(86, "GPIO_86"),
 169         PINCTRL_PIN(87, "GPIO_87"),
 170         PINCTRL_PIN(88, "GPIO_88"),
 171         PINCTRL_PIN(89, "GPIO_89"),
 172         PINCTRL_PIN(90, "GPIO_90"),
 173         PINCTRL_PIN(91, "GPIO_91"),
 174         PINCTRL_PIN(92, "GPIO_92"),
 175         PINCTRL_PIN(93, "GPIO_93"),
 176         PINCTRL_PIN(95, "GPIO_95"),
 177         PINCTRL_PIN(96, "GPIO_96"),
 178         PINCTRL_PIN(97, "GPIO_97"),
 179         PINCTRL_PIN(98, "GPIO_98"),
 180         PINCTRL_PIN(99, "GPIO_99"),
 181         PINCTRL_PIN(100, "GPIO_100"),
 182         PINCTRL_PIN(101, "GPIO_101"),
 183         PINCTRL_PIN(102, "GPIO_102"),
 184         PINCTRL_PIN(113, "GPIO_113"),
 185         PINCTRL_PIN(114, "GPIO_114"),
 186         PINCTRL_PIN(115, "GPIO_115"),
 187         PINCTRL_PIN(116, "GPIO_116"),
 188         PINCTRL_PIN(117, "GPIO_117"),
 189         PINCTRL_PIN(118, "GPIO_118"),
 190         PINCTRL_PIN(119, "GPIO_119"),
 191         PINCTRL_PIN(120, "GPIO_120"),
 192         PINCTRL_PIN(121, "GPIO_121"),
 193         PINCTRL_PIN(122, "GPIO_122"),
 194         PINCTRL_PIN(126, "GPIO_126"),
 195         PINCTRL_PIN(129, "GPIO_129"),
 196         PINCTRL_PIN(130, "GPIO_130"),
 197         PINCTRL_PIN(131, "GPIO_131"),
 198         PINCTRL_PIN(132, "GPIO_132"),
 199         PINCTRL_PIN(133, "GPIO_133"),
 200         PINCTRL_PIN(135, "GPIO_135"),
 201         PINCTRL_PIN(136, "GPIO_136"),
 202         PINCTRL_PIN(137, "GPIO_137"),
 203         PINCTRL_PIN(138, "GPIO_138"),
 204         PINCTRL_PIN(139, "GPIO_139"),
 205         PINCTRL_PIN(140, "GPIO_140"),
 206         PINCTRL_PIN(141, "GPIO_141"),
 207         PINCTRL_PIN(142, "GPIO_142"),
 208         PINCTRL_PIN(143, "GPIO_143"),
 209         PINCTRL_PIN(144, "GPIO_144"),
 210         PINCTRL_PIN(145, "GPIO_145"),
 211         PINCTRL_PIN(146, "GPIO_146"),
 212         PINCTRL_PIN(147, "GPIO_147"),
 213         PINCTRL_PIN(148, "GPIO_148"),
 214         PINCTRL_PIN(166, "GPIO_166"),
 215         PINCTRL_PIN(167, "GPIO_167"),
 216         PINCTRL_PIN(168, "GPIO_168"),
 217         PINCTRL_PIN(169, "GPIO_169"),
 218         PINCTRL_PIN(170, "GPIO_170"),
 219         PINCTRL_PIN(171, "GPIO_171"),
 220         PINCTRL_PIN(172, "GPIO_172"),
 221         PINCTRL_PIN(173, "GPIO_173"),
 222         PINCTRL_PIN(174, "GPIO_174"),
 223         PINCTRL_PIN(175, "GPIO_175"),
 224         PINCTRL_PIN(176, "GPIO_176"),
 225         PINCTRL_PIN(177, "GPIO_177"),
 226 };
 227
 228 static const unsigned i2c0_pins[] = {145, 146};
 229 static const unsigned i2c1_pins[] = {147, 148};
 230 static const unsigned i2c2_pins[] = {113, 114};
 231 static const unsigned i2c3_pins[] = {19, 20};
 232
 233 static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
 234 static const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
 235
 236 static const struct amd_pingroup kerncz_groups[] = {
 237         {
 238                 .name = "i2c0",
 239                 .pins = i2c0_pins,
 240                 .npins = 2,
 241         },
 242         {
 243                 .name = "i2c1",
 244                 .pins = i2c1_pins,
 245                 .npins = 2,
 246         },
 247         {
 248                 .name = "i2c2",
 249                 .pins = i2c2_pins,
 250                 .npins = 2,
 251         },
 252         {
 253                 .name = "i2c3",
 254                 .pins = i2c3_pins,
 255                 .npins = 2,
 256         },
 257         {
 258                 .name = "uart0",
 259                 .pins = uart0_pins,
 260                 .npins = 5,
 261         },
 262         {
 263                 .name = "uart1",
 264                 .pins = uart1_pins,
 265                 .npins = 5,
 266         },
 267 };
 268
 269 #endif