4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
13 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
17 #include <linux/err.h>
18 #include <linux/bug.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/compiler.h>
23 #include <linux/types.h>
24 #include <linux/errno.h>
25 #include <linux/log2.h>
27 #include <linux/gpio.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/acpi.h>
32 #include <linux/seq_file.h>
33 #include <linux/interrupt.h>
34 #include <linux/list.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
40 #include "pinctrl-utils.h"
41 #include "pinctrl-amd.h"
43 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
47 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
49 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
50 pin_reg = readl(gpio_dev->base + offset * 4);
51 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
53 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
60 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
62 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
63 pin_reg = readl(gpio_dev->base + offset * 4);
64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
65 writel(pin_reg, gpio_dev->base + offset * 4);
66 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
76 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
78 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
79 pin_reg = readl(gpio_dev->base + offset * 4);
80 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
82 pin_reg |= BIT(OUTPUT_VALUE_OFF);
84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
85 writel(pin_reg, gpio_dev->base + offset * 4);
86 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
95 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
97 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
98 pin_reg = readl(gpio_dev->base + offset * 4);
99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
101 return !!(pin_reg & BIT(PIN_STS_OFF));
104 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
108 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
110 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
111 pin_reg = readl(gpio_dev->base + offset * 4);
113 pin_reg |= BIT(OUTPUT_VALUE_OFF);
115 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
116 writel(pin_reg, gpio_dev->base + offset * 4);
117 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
120 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
127 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
129 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
131 /* Use special handling for Pin0 debounce */
133 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
134 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
138 pin_reg = readl(gpio_dev->base + offset * 4);
141 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
142 pin_reg &= ~DB_TMR_OUT_MASK;
144 Debounce Debounce Timer Max
145 TmrLarge TmrOutUnit Unit Debounce
147 0 0 61 usec (2 RtcClk) 976 usec
148 0 1 244 usec (8 RtcClk) 3.9 msec
149 1 0 15.6 msec (512 RtcClk) 250 msec
150 1 1 62.5 msec (2048 RtcClk) 1 sec
155 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
157 } else if (debounce < 976) {
158 time = debounce / 61;
159 pin_reg |= time & DB_TMR_OUT_MASK;
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
161 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
162 } else if (debounce < 3900) {
163 time = debounce / 244;
164 pin_reg |= time & DB_TMR_OUT_MASK;
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
166 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
167 } else if (debounce < 250000) {
168 time = debounce / 15625;
169 pin_reg |= time & DB_TMR_OUT_MASK;
170 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
171 pin_reg |= BIT(DB_TMR_LARGE_OFF);
172 } else if (debounce < 1000000) {
173 time = debounce / 62500;
174 pin_reg |= time & DB_TMR_OUT_MASK;
175 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
176 pin_reg |= BIT(DB_TMR_LARGE_OFF);
178 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
182 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
183 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
184 pin_reg &= ~DB_TMR_OUT_MASK;
185 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
187 writel(pin_reg, gpio_dev->base + offset * 4);
188 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
193 #ifdef CONFIG_DEBUG_FS
194 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
198 unsigned int bank, i, pin_num;
199 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
203 char *interrupt_enable;
204 char *interrupt_mask;
210 char *pull_up_enable;
211 char *pull_down_enable;
215 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
216 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
217 seq_printf(s, "GPIO bank%d\t", bank);
222 pin_num = AMD_GPIO_PINS_BANK0;
226 pin_num = AMD_GPIO_PINS_BANK1 + i;
230 pin_num = AMD_GPIO_PINS_BANK2 + i;
234 pin_num = AMD_GPIO_PINS_BANK3 + i;
237 /* Illegal bank number, ignore */
240 for (; i < pin_num; i++) {
241 seq_printf(s, "pin%d\t", i);
242 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
243 pin_reg = readl(gpio_dev->base + i * 4);
244 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
246 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
247 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
249 interrupt_enable = "interrupt is enabled|";
251 if (level == ACTIVE_LEVEL_HIGH)
252 active_level = "Active high|";
253 else if (level == ACTIVE_LEVEL_LOW)
254 active_level = "Active low|";
255 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
256 level == ACTIVE_LEVEL_BOTH)
257 active_level = "Active on both|";
259 active_level = "Unknown Active level|";
261 if (pin_reg & BIT(LEVEL_TRIG_OFF))
262 level_trig = "Level trigger|";
264 level_trig = "Edge trigger|";
268 "interrupt is disabled|";
273 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
275 "interrupt is unmasked|";
278 "interrupt is masked|";
280 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
281 wake_cntrl0 = "enable wakeup in S0i3 state|";
283 wake_cntrl0 = "disable wakeup in S0i3 state|";
285 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
286 wake_cntrl1 = "enable wakeup in S3 state|";
288 wake_cntrl1 = "disable wakeup in S3 state|";
290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
291 wake_cntrl2 = "enable wakeup in S4/S5 state|";
293 wake_cntrl2 = "disable wakeup in S4/S5 state|";
295 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
296 pull_up_enable = "pull-up is enabled|";
297 if (pin_reg & BIT(PULL_UP_SEL_OFF))
298 pull_up_sel = "8k pull-up|";
300 pull_up_sel = "4k pull-up|";
302 pull_up_enable = "pull-up is disabled|";
306 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
307 pull_down_enable = "pull-down is enabled|";
309 pull_down_enable = "Pull-down is disabled|";
311 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
313 output_enable = "output is enabled|";
314 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
315 output_value = "output is high|";
317 output_value = "output is low|";
319 output_enable = "output is disabled|";
322 if (pin_reg & BIT(PIN_STS_OFF))
323 pin_sts = "input is high|";
325 pin_sts = "input is low|";
328 seq_printf(s, "%s %s %s %s %s %s\n"
329 " %s %s %s %s %s %s %s 0x%x\n",
330 level_trig, active_level, interrupt_enable,
331 interrupt_mask, wake_cntrl0, wake_cntrl1,
332 wake_cntrl2, pin_sts, pull_up_sel,
333 pull_up_enable, pull_down_enable,
334 output_value, output_enable, pin_reg);
339 #define amd_gpio_dbg_show NULL
342 static void amd_gpio_irq_enable(struct irq_data *d)
346 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
347 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
349 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
350 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
351 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
352 pin_reg |= BIT(INTERRUPT_MASK_OFF);
353 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
354 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
357 static void amd_gpio_irq_disable(struct irq_data *d)
361 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
362 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
364 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
365 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
366 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
367 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
368 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
369 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
372 static void amd_gpio_irq_mask(struct irq_data *d)
376 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
377 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
379 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
380 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
381 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
382 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
383 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
386 static void amd_gpio_irq_unmask(struct irq_data *d)
390 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
391 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
393 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
394 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
395 pin_reg |= BIT(INTERRUPT_MASK_OFF);
396 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
397 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
400 static void amd_gpio_irq_eoi(struct irq_data *d)
404 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
405 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
407 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
408 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
410 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
411 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
414 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
417 u32 pin_reg, pin_reg_irq_en, mask;
418 unsigned long flags, irq_flags;
419 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
420 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
422 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
423 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
425 /* Ignore the settings coming from the client and
426 * read the values from the ACPI tables
427 * while setting the trigger type
430 irq_flags = irq_get_trigger_type(d->irq);
431 if (irq_flags != IRQ_TYPE_NONE)
434 switch (type & IRQ_TYPE_SENSE_MASK) {
435 case IRQ_TYPE_EDGE_RISING:
436 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
437 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
438 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
439 irq_set_handler_locked(d, handle_edge_irq);
442 case IRQ_TYPE_EDGE_FALLING:
443 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
444 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
445 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
446 irq_set_handler_locked(d, handle_edge_irq);
449 case IRQ_TYPE_EDGE_BOTH:
450 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
451 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
452 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
453 irq_set_handler_locked(d, handle_edge_irq);
456 case IRQ_TYPE_LEVEL_HIGH:
457 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
458 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
459 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
460 irq_set_handler_locked(d, handle_level_irq);
463 case IRQ_TYPE_LEVEL_LOW:
464 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
465 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
466 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
467 irq_set_handler_locked(d, handle_level_irq);
474 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
478 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
480 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
481 * debounce registers of any GPIO will block wake/interrupt status
482 * generation for *all* GPIOs for a lenght of time that depends on
483 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
484 * INTERRUPT_ENABLE bit will read as 0.
486 * We temporarily enable irq for the GPIO whose configuration is
487 * changing, and then wait for it to read back as 1 to know when
488 * debounce has settled and then disable the irq again.
489 * We do this polling with the spinlock held to ensure other GPIO
490 * access routines do not read an incorrect value for the irq enable
491 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
492 * spurious irqs, and disable the irq again after polling.
494 mask = BIT(INTERRUPT_ENABLE_OFF);
495 pin_reg_irq_en = pin_reg;
496 pin_reg_irq_en |= mask;
497 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
498 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
499 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
501 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
502 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
507 static void amd_irq_ack(struct irq_data *d)
510 * based on HW design,there is no need to ack HW
511 * before handle current irq. But this routine is
512 * necessary for handle_edge_irq
516 static struct irq_chip amd_gpio_irqchip = {
518 .irq_ack = amd_irq_ack,
519 .irq_enable = amd_gpio_irq_enable,
520 .irq_disable = amd_gpio_irq_disable,
521 .irq_mask = amd_gpio_irq_mask,
522 .irq_unmask = amd_gpio_irq_unmask,
523 .irq_eoi = amd_gpio_irq_eoi,
524 .irq_set_type = amd_gpio_irq_set_type,
525 .flags = IRQCHIP_SKIP_SET_WAKE,
528 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
530 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
532 struct amd_gpio *gpio_dev = dev_id;
533 struct gpio_chip *gc = &gpio_dev->gc;
534 irqreturn_t ret = IRQ_NONE;
535 unsigned int i, irqnr;
541 /* Read the wake status */
542 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
543 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
545 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
546 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
548 /* Bit 0-45 contain the relevant status bits */
549 status &= (1ULL << 46) - 1;
550 regs = gpio_dev->base;
551 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
552 if (!(status & mask))
556 /* Each status bit covers four pins */
557 for (i = 0; i < 4; i++) {
558 regval = readl(regs + i);
559 if (!(regval & PIN_IRQ_PENDING) ||
560 !(regval & BIT(INTERRUPT_MASK_OFF)))
562 irq = irq_find_mapping(gc->irq.domain, irqnr + i);
564 generic_handle_irq(irq);
567 * We must read the pin register again, in case the
568 * value was changed while executing
569 * generic_handle_irq() above.
570 * If we didn't find a mapping for the interrupt,
571 * disable it in order to avoid a system hang caused
572 * by an interrupt storm.
574 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
575 regval = readl(regs + i);
577 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
578 dev_dbg(&gpio_dev->pdev->dev,
579 "Disabling spurious GPIO IRQ %d\n",
582 writel(regval, regs + i);
583 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
588 /* Signal EOI to the GPIO unit */
589 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
590 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
592 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
593 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
598 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
600 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
602 return gpio_dev->ngroups;
605 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
608 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
610 return gpio_dev->groups[group].name;
613 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
615 const unsigned **pins,
618 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
620 *pins = gpio_dev->groups[group].pins;
621 *num_pins = gpio_dev->groups[group].npins;
625 static const struct pinctrl_ops amd_pinctrl_ops = {
626 .get_groups_count = amd_get_groups_count,
627 .get_group_name = amd_get_group_name,
628 .get_group_pins = amd_get_group_pins,
630 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
631 .dt_free_map = pinctrl_utils_free_map,
635 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
637 unsigned long *config)
642 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
643 enum pin_config_param param = pinconf_to_config_param(*config);
645 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
646 pin_reg = readl(gpio_dev->base + pin*4);
647 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
649 case PIN_CONFIG_INPUT_DEBOUNCE:
650 arg = pin_reg & DB_TMR_OUT_MASK;
653 case PIN_CONFIG_BIAS_PULL_DOWN:
654 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
657 case PIN_CONFIG_BIAS_PULL_UP:
658 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
661 case PIN_CONFIG_DRIVE_STRENGTH:
662 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
666 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
671 *config = pinconf_to_config_packed(param, arg);
676 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
677 unsigned long *configs, unsigned int num_configs)
684 enum pin_config_param param;
685 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
687 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
688 for (i = 0; i < num_configs; i++) {
689 param = pinconf_to_config_param(configs[i]);
690 arg = pinconf_to_config_argument(configs[i]);
691 pin_reg = readl(gpio_dev->base + pin*4);
694 case PIN_CONFIG_INPUT_DEBOUNCE:
695 pin_reg &= ~DB_TMR_OUT_MASK;
696 pin_reg |= arg & DB_TMR_OUT_MASK;
699 case PIN_CONFIG_BIAS_PULL_DOWN:
700 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
701 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
704 case PIN_CONFIG_BIAS_PULL_UP:
705 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
706 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
707 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
708 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
711 case PIN_CONFIG_DRIVE_STRENGTH:
712 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
713 << DRV_STRENGTH_SEL_OFF);
714 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
715 << DRV_STRENGTH_SEL_OFF;
719 dev_dbg(&gpio_dev->pdev->dev,
720 "Invalid config param %04x\n", param);
724 writel(pin_reg, gpio_dev->base + pin*4);
726 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
731 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
733 unsigned long *config)
735 const unsigned *pins;
739 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
743 if (amd_pinconf_get(pctldev, pins[0], config))
749 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
750 unsigned group, unsigned long *configs,
751 unsigned num_configs)
753 const unsigned *pins;
757 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
760 for (i = 0; i < npins; i++) {
761 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
767 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
768 unsigned long config)
770 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
772 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
773 u32 debounce = pinconf_to_config_argument(config);
775 return amd_gpio_set_debounce(gc, pin, debounce);
778 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
781 static const struct pinconf_ops amd_pinconf_ops = {
782 .pin_config_get = amd_pinconf_get,
783 .pin_config_set = amd_pinconf_set,
784 .pin_config_group_get = amd_pinconf_group_get,
785 .pin_config_group_set = amd_pinconf_group_set,
788 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
790 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
795 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
796 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
797 BIT(WAKE_CNTRL_OFF_S4);
799 for (i = 0; i < desc->npins; i++) {
800 int pin = desc->pins[i].number;
801 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
806 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
808 pin_reg = readl(gpio_dev->base + pin * 4);
810 writel(pin_reg, gpio_dev->base + pin * 4);
812 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
816 #ifdef CONFIG_PM_SLEEP
817 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
819 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
825 * Only restore the pin if it is actually in use by the kernel (or
828 if (pd->mux_owner || pd->gpio_owner ||
829 gpiochip_line_is_irq(&gpio_dev->gc, pin))
835 static int amd_gpio_suspend(struct device *dev)
837 struct platform_device *pdev = to_platform_device(dev);
838 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
839 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
843 for (i = 0; i < desc->npins; i++) {
844 int pin = desc->pins[i].number;
846 if (!amd_gpio_should_save(gpio_dev, pin))
849 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
850 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
851 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
857 static int amd_gpio_resume(struct device *dev)
859 struct platform_device *pdev = to_platform_device(dev);
860 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
861 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
865 for (i = 0; i < desc->npins; i++) {
866 int pin = desc->pins[i].number;
868 if (!amd_gpio_should_save(gpio_dev, pin))
871 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
872 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
873 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
874 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
880 static const struct dev_pm_ops amd_gpio_pm_ops = {
881 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
886 static struct pinctrl_desc amd_pinctrl_desc = {
888 .npins = ARRAY_SIZE(kerncz_pins),
889 .pctlops = &amd_pinctrl_ops,
890 .confops = &amd_pinconf_ops,
891 .owner = THIS_MODULE,
894 static int amd_gpio_probe(struct platform_device *pdev)
898 struct resource *res;
899 struct amd_gpio *gpio_dev;
900 struct gpio_irq_chip *girq;
902 gpio_dev = devm_kzalloc(&pdev->dev,
903 sizeof(struct amd_gpio), GFP_KERNEL);
907 raw_spin_lock_init(&gpio_dev->lock);
909 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
911 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
915 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
920 irq_base = platform_get_irq(pdev, 0);
922 dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
926 #ifdef CONFIG_PM_SLEEP
927 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
928 sizeof(*gpio_dev->saved_regs),
930 if (!gpio_dev->saved_regs)
934 gpio_dev->pdev = pdev;
935 gpio_dev->gc.get_direction = amd_gpio_get_direction;
936 gpio_dev->gc.direction_input = amd_gpio_direction_input;
937 gpio_dev->gc.direction_output = amd_gpio_direction_output;
938 gpio_dev->gc.get = amd_gpio_get_value;
939 gpio_dev->gc.set = amd_gpio_set_value;
940 gpio_dev->gc.set_config = amd_gpio_set_config;
941 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
943 gpio_dev->gc.base = -1;
944 gpio_dev->gc.label = pdev->name;
945 gpio_dev->gc.owner = THIS_MODULE;
946 gpio_dev->gc.parent = &pdev->dev;
947 gpio_dev->gc.ngpio = resource_size(res) / 4;
948 #if defined(CONFIG_OF_GPIO)
949 gpio_dev->gc.of_node = pdev->dev.of_node;
952 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
953 gpio_dev->groups = kerncz_groups;
954 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
956 amd_pinctrl_desc.name = dev_name(&pdev->dev);
957 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
959 if (IS_ERR(gpio_dev->pctrl)) {
960 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
961 return PTR_ERR(gpio_dev->pctrl);
964 /* Disable and mask interrupts */
965 amd_gpio_irq_init(gpio_dev);
967 girq = &gpio_dev->gc.irq;
968 girq->chip = &amd_gpio_irqchip;
969 /* This will let us handle the parent IRQ in the driver */
970 girq->parent_handler = NULL;
971 girq->num_parents = 0;
972 girq->parents = NULL;
973 girq->default_type = IRQ_TYPE_NONE;
974 girq->handler = handle_simple_irq;
976 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
980 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
981 0, 0, gpio_dev->gc.ngpio);
983 dev_err(&pdev->dev, "Failed to add pin range\n");
987 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
988 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
992 platform_set_drvdata(pdev, gpio_dev);
994 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
998 gpiochip_remove(&gpio_dev->gc);
1003 static int amd_gpio_remove(struct platform_device *pdev)
1005 struct amd_gpio *gpio_dev;
1007 gpio_dev = platform_get_drvdata(pdev);
1009 gpiochip_remove(&gpio_dev->gc);
1014 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1020 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1022 static struct platform_driver amd_gpio_driver = {
1025 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1026 #ifdef CONFIG_PM_SLEEP
1027 .pm = &amd_gpio_pm_ops,
1030 .probe = amd_gpio_probe,
1031 .remove = amd_gpio_remove,
1034 module_platform_driver(amd_gpio_driver);
1036 MODULE_LICENSE("GPL v2");
1037 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1038 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");