4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
39 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
45 spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
48 writel(pin_reg, gpio_dev->base + offset * 4);
49 spin_unlock_irqrestore(&gpio_dev->lock, flags);
54 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
61 spin_lock_irqsave(&gpio_dev->lock, flags);
62 pin_reg = readl(gpio_dev->base + offset * 4);
63 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
65 pin_reg |= BIT(OUTPUT_VALUE_OFF);
67 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
68 writel(pin_reg, gpio_dev->base + offset * 4);
69 spin_unlock_irqrestore(&gpio_dev->lock, flags);
74 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
78 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
80 spin_lock_irqsave(&gpio_dev->lock, flags);
81 pin_reg = readl(gpio_dev->base + offset * 4);
82 spin_unlock_irqrestore(&gpio_dev->lock, flags);
84 return !!(pin_reg & BIT(PIN_STS_OFF));
87 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
91 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
93 spin_lock_irqsave(&gpio_dev->lock, flags);
94 pin_reg = readl(gpio_dev->base + offset * 4);
96 pin_reg |= BIT(OUTPUT_VALUE_OFF);
98 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
99 writel(pin_reg, gpio_dev->base + offset * 4);
100 spin_unlock_irqrestore(&gpio_dev->lock, flags);
103 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
110 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
112 spin_lock_irqsave(&gpio_dev->lock, flags);
113 pin_reg = readl(gpio_dev->base + offset * 4);
116 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
117 pin_reg &= ~DB_TMR_OUT_MASK;
119 Debounce Debounce Timer Max
120 TmrLarge TmrOutUnit Unit Debounce
122 0 0 61 usec (2 RtcClk) 976 usec
123 0 1 244 usec (8 RtcClk) 3.9 msec
124 1 0 15.6 msec (512 RtcClk) 250 msec
125 1 1 62.5 msec (2048 RtcClk) 1 sec
130 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
131 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
132 } else if (debounce < 976) {
133 time = debounce / 61;
134 pin_reg |= time & DB_TMR_OUT_MASK;
135 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
136 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
137 } else if (debounce < 3900) {
138 time = debounce / 244;
139 pin_reg |= time & DB_TMR_OUT_MASK;
140 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
141 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
142 } else if (debounce < 250000) {
143 time = debounce / 15625;
144 pin_reg |= time & DB_TMR_OUT_MASK;
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
146 pin_reg |= BIT(DB_TMR_LARGE_OFF);
147 } else if (debounce < 1000000) {
148 time = debounce / 62500;
149 pin_reg |= time & DB_TMR_OUT_MASK;
150 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
151 pin_reg |= BIT(DB_TMR_LARGE_OFF);
153 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
157 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 pin_reg &= ~DB_TMR_OUT_MASK;
160 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
162 writel(pin_reg, gpio_dev->base + offset * 4);
163 spin_unlock_irqrestore(&gpio_dev->lock, flags);
168 #ifdef CONFIG_DEBUG_FS
169 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
173 unsigned int bank, i, pin_num;
174 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
178 char *interrupt_enable;
179 char *interrupt_mask;
185 char *pull_up_enable;
186 char *pull_down_enable;
190 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
191 seq_printf(s, "GPIO bank%d\t", bank);
196 pin_num = AMD_GPIO_PINS_BANK0;
200 pin_num = AMD_GPIO_PINS_BANK1 + i;
204 pin_num = AMD_GPIO_PINS_BANK2 + i;
208 for (; i < pin_num; i++) {
209 seq_printf(s, "pin%d\t", i);
210 spin_lock_irqsave(&gpio_dev->lock, flags);
211 pin_reg = readl(gpio_dev->base + i * 4);
212 spin_unlock_irqrestore(&gpio_dev->lock, flags);
214 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
215 interrupt_enable = "interrupt is enabled|";
217 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
218 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
219 active_level = "Active low|";
220 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
221 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
222 active_level = "Active high|";
223 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
224 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
225 active_level = "Active on both|";
227 active_level = "Unknow Active level|";
229 if (pin_reg & BIT(LEVEL_TRIG_OFF))
230 level_trig = "Level trigger|";
232 level_trig = "Edge trigger|";
236 "interrupt is disabled|";
241 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
243 "interrupt is unmasked|";
246 "interrupt is masked|";
248 if (pin_reg & BIT(WAKE_CNTRL_OFF))
249 wake_cntrl0 = "enable wakeup in S0i3 state|";
251 wake_cntrl0 = "disable wakeup in S0i3 state|";
253 if (pin_reg & BIT(WAKE_CNTRL_OFF))
254 wake_cntrl1 = "enable wakeup in S3 state|";
256 wake_cntrl1 = "disable wakeup in S3 state|";
258 if (pin_reg & BIT(WAKE_CNTRL_OFF))
259 wake_cntrl2 = "enable wakeup in S4/S5 state|";
261 wake_cntrl2 = "disable wakeup in S4/S5 state|";
263 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
264 pull_up_enable = "pull-up is enabled|";
265 if (pin_reg & BIT(PULL_UP_SEL_OFF))
266 pull_up_sel = "8k pull-up|";
268 pull_up_sel = "4k pull-up|";
270 pull_up_enable = "pull-up is disabled|";
274 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
275 pull_down_enable = "pull-down is enabled|";
277 pull_down_enable = "Pull-down is disabled|";
279 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
281 output_enable = "output is enabled|";
282 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
283 output_value = "output is high|";
285 output_value = "output is low|";
287 output_enable = "output is disabled|";
290 if (pin_reg & BIT(PIN_STS_OFF))
291 pin_sts = "input is high|";
293 pin_sts = "input is low|";
296 seq_printf(s, "%s %s %s %s %s %s\n"
297 " %s %s %s %s %s %s %s 0x%x\n",
298 level_trig, active_level, interrupt_enable,
299 interrupt_mask, wake_cntrl0, wake_cntrl1,
300 wake_cntrl2, pin_sts, pull_up_sel,
301 pull_up_enable, pull_down_enable,
302 output_value, output_enable, pin_reg);
307 #define amd_gpio_dbg_show NULL
310 static void amd_gpio_irq_enable(struct irq_data *d)
314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
315 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
317 spin_lock_irqsave(&gpio_dev->lock, flags);
318 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
319 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
320 pin_reg |= BIT(INTERRUPT_MASK_OFF);
321 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
322 spin_unlock_irqrestore(&gpio_dev->lock, flags);
325 static void amd_gpio_irq_disable(struct irq_data *d)
329 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
330 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
332 spin_lock_irqsave(&gpio_dev->lock, flags);
333 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
334 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
335 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
336 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
337 spin_unlock_irqrestore(&gpio_dev->lock, flags);
340 static void amd_gpio_irq_mask(struct irq_data *d)
344 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
345 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
347 spin_lock_irqsave(&gpio_dev->lock, flags);
348 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
349 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
350 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
351 spin_unlock_irqrestore(&gpio_dev->lock, flags);
354 static void amd_gpio_irq_unmask(struct irq_data *d)
358 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
359 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
361 spin_lock_irqsave(&gpio_dev->lock, flags);
362 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
363 pin_reg |= BIT(INTERRUPT_MASK_OFF);
364 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
365 spin_unlock_irqrestore(&gpio_dev->lock, flags);
368 static void amd_gpio_irq_eoi(struct irq_data *d)
372 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
373 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
375 spin_lock_irqsave(&gpio_dev->lock, flags);
376 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
378 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
379 spin_unlock_irqrestore(&gpio_dev->lock, flags);
382 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
386 unsigned long flags, irq_flags;
387 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
388 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
390 spin_lock_irqsave(&gpio_dev->lock, flags);
391 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
393 /* Ignore the settings coming from the client and
394 * read the values from the ACPI tables
395 * while setting the trigger type
398 irq_flags = irq_get_trigger_type(d->irq);
399 if (irq_flags != IRQ_TYPE_NONE)
402 switch (type & IRQ_TYPE_SENSE_MASK) {
403 case IRQ_TYPE_EDGE_RISING:
404 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
405 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
406 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
407 irq_set_handler_locked(d, handle_edge_irq);
410 case IRQ_TYPE_EDGE_FALLING:
411 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
412 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
413 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
414 irq_set_handler_locked(d, handle_edge_irq);
417 case IRQ_TYPE_EDGE_BOTH:
418 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
419 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
420 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
421 irq_set_handler_locked(d, handle_edge_irq);
424 case IRQ_TYPE_LEVEL_HIGH:
425 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
426 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
427 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
428 irq_set_handler_locked(d, handle_level_irq);
431 case IRQ_TYPE_LEVEL_LOW:
432 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
433 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
434 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
435 irq_set_handler_locked(d, handle_level_irq);
442 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
446 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
447 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
448 spin_unlock_irqrestore(&gpio_dev->lock, flags);
453 static void amd_irq_ack(struct irq_data *d)
456 * based on HW design,there is no need to ack HW
457 * before handle current irq. But this routine is
458 * necessary for handle_edge_irq
462 static struct irq_chip amd_gpio_irqchip = {
464 .irq_ack = amd_irq_ack,
465 .irq_enable = amd_gpio_irq_enable,
466 .irq_disable = amd_gpio_irq_disable,
467 .irq_mask = amd_gpio_irq_mask,
468 .irq_unmask = amd_gpio_irq_unmask,
469 .irq_eoi = amd_gpio_irq_eoi,
470 .irq_set_type = amd_gpio_irq_set_type,
473 static void amd_gpio_irq_handler(struct irq_desc *desc)
483 struct irq_chip *chip = irq_desc_get_chip(desc);
484 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
485 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
487 chained_irq_enter(chip, desc);
488 /*enable GPIO interrupt again*/
489 spin_lock_irqsave(&gpio_dev->lock, flags);
490 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
494 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
496 spin_unlock_irqrestore(&gpio_dev->lock, flags);
499 * first 46 bits indicates interrupt status.
500 * one bit represents four interrupt sources.
502 for (off = 0; off < 46 ; off++) {
503 if (reg64 & BIT(off)) {
504 for (i = 0; i < 4; i++) {
505 pin_reg = readl(gpio_dev->base +
507 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
508 (pin_reg & BIT(WAKE_STS_OFF))) {
509 irq = irq_find_mapping(gc->irqdomain,
511 generic_handle_irq(irq);
514 + (off * 4 + i) * 4);
522 handle_bad_irq(desc);
524 spin_lock_irqsave(&gpio_dev->lock, flags);
525 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
527 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
528 spin_unlock_irqrestore(&gpio_dev->lock, flags);
530 chained_irq_exit(chip, desc);
533 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
535 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
537 return gpio_dev->ngroups;
540 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
543 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
545 return gpio_dev->groups[group].name;
548 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
550 const unsigned **pins,
553 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
555 *pins = gpio_dev->groups[group].pins;
556 *num_pins = gpio_dev->groups[group].npins;
560 static const struct pinctrl_ops amd_pinctrl_ops = {
561 .get_groups_count = amd_get_groups_count,
562 .get_group_name = amd_get_group_name,
563 .get_group_pins = amd_get_group_pins,
565 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
566 .dt_free_map = pinctrl_utils_free_map,
570 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
572 unsigned long *config)
577 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
578 enum pin_config_param param = pinconf_to_config_param(*config);
580 spin_lock_irqsave(&gpio_dev->lock, flags);
581 pin_reg = readl(gpio_dev->base + pin*4);
582 spin_unlock_irqrestore(&gpio_dev->lock, flags);
584 case PIN_CONFIG_INPUT_DEBOUNCE:
585 arg = pin_reg & DB_TMR_OUT_MASK;
588 case PIN_CONFIG_BIAS_PULL_DOWN:
589 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
592 case PIN_CONFIG_BIAS_PULL_UP:
593 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
596 case PIN_CONFIG_DRIVE_STRENGTH:
597 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
601 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
606 *config = pinconf_to_config_packed(param, arg);
611 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
612 unsigned long *configs, unsigned num_configs)
619 enum pin_config_param param;
620 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
622 spin_lock_irqsave(&gpio_dev->lock, flags);
623 for (i = 0; i < num_configs; i++) {
624 param = pinconf_to_config_param(configs[i]);
625 arg = pinconf_to_config_argument(configs[i]);
626 pin_reg = readl(gpio_dev->base + pin*4);
629 case PIN_CONFIG_INPUT_DEBOUNCE:
630 pin_reg &= ~DB_TMR_OUT_MASK;
631 pin_reg |= arg & DB_TMR_OUT_MASK;
634 case PIN_CONFIG_BIAS_PULL_DOWN:
635 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
636 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
639 case PIN_CONFIG_BIAS_PULL_UP:
640 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
641 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
642 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
643 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
646 case PIN_CONFIG_DRIVE_STRENGTH:
647 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
648 << DRV_STRENGTH_SEL_OFF);
649 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
650 << DRV_STRENGTH_SEL_OFF;
654 dev_err(&gpio_dev->pdev->dev,
655 "Invalid config param %04x\n", param);
659 writel(pin_reg, gpio_dev->base + pin*4);
661 spin_unlock_irqrestore(&gpio_dev->lock, flags);
666 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
668 unsigned long *config)
670 const unsigned *pins;
674 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
678 if (amd_pinconf_get(pctldev, pins[0], config))
684 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
685 unsigned group, unsigned long *configs,
686 unsigned num_configs)
688 const unsigned *pins;
692 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
695 for (i = 0; i < npins; i++) {
696 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
702 static const struct pinconf_ops amd_pinconf_ops = {
703 .pin_config_get = amd_pinconf_get,
704 .pin_config_set = amd_pinconf_set,
705 .pin_config_group_get = amd_pinconf_group_get,
706 .pin_config_group_set = amd_pinconf_group_set,
709 #ifdef CONFIG_PM_SLEEP
710 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
712 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
718 * Only restore the pin if it is actually in use by the kernel (or
721 if (pd->mux_owner || pd->gpio_owner ||
722 gpiochip_line_is_irq(&gpio_dev->gc, pin))
728 int amd_gpio_suspend(struct device *dev)
730 struct platform_device *pdev = to_platform_device(dev);
731 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
732 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
735 for (i = 0; i < desc->npins; i++) {
736 int pin = desc->pins[i].number;
738 if (!amd_gpio_should_save(gpio_dev, pin))
741 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
747 int amd_gpio_resume(struct device *dev)
749 struct platform_device *pdev = to_platform_device(dev);
750 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
751 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
754 for (i = 0; i < desc->npins; i++) {
755 int pin = desc->pins[i].number;
757 if (!amd_gpio_should_save(gpio_dev, pin))
760 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
766 static const struct dev_pm_ops amd_gpio_pm_ops = {
767 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
772 static struct pinctrl_desc amd_pinctrl_desc = {
774 .npins = ARRAY_SIZE(kerncz_pins),
775 .pctlops = &amd_pinctrl_ops,
776 .confops = &amd_pinconf_ops,
777 .owner = THIS_MODULE,
780 static int amd_gpio_probe(struct platform_device *pdev)
784 struct resource *res;
785 struct amd_gpio *gpio_dev;
787 gpio_dev = devm_kzalloc(&pdev->dev,
788 sizeof(struct amd_gpio), GFP_KERNEL);
792 spin_lock_init(&gpio_dev->lock);
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
796 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
800 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
805 irq_base = platform_get_irq(pdev, 0);
807 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
811 #ifdef CONFIG_PM_SLEEP
812 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
813 sizeof(*gpio_dev->saved_regs),
815 if (!gpio_dev->saved_regs)
819 gpio_dev->pdev = pdev;
820 gpio_dev->gc.direction_input = amd_gpio_direction_input;
821 gpio_dev->gc.direction_output = amd_gpio_direction_output;
822 gpio_dev->gc.get = amd_gpio_get_value;
823 gpio_dev->gc.set = amd_gpio_set_value;
824 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
825 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
827 gpio_dev->gc.base = 0;
828 gpio_dev->gc.label = pdev->name;
829 gpio_dev->gc.owner = THIS_MODULE;
830 gpio_dev->gc.parent = &pdev->dev;
831 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
832 #if defined(CONFIG_OF_GPIO)
833 gpio_dev->gc.of_node = pdev->dev.of_node;
836 gpio_dev->groups = kerncz_groups;
837 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
839 amd_pinctrl_desc.name = dev_name(&pdev->dev);
840 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
842 if (IS_ERR(gpio_dev->pctrl)) {
843 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
844 return PTR_ERR(gpio_dev->pctrl);
847 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
851 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
852 0, 0, TOTAL_NUMBER_OF_PINS);
854 dev_err(&pdev->dev, "Failed to add pin range\n");
858 ret = gpiochip_irqchip_add(&gpio_dev->gc,
864 dev_err(&pdev->dev, "could not add irqchip\n");
869 gpiochip_set_chained_irqchip(&gpio_dev->gc,
872 amd_gpio_irq_handler);
874 platform_set_drvdata(pdev, gpio_dev);
876 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
880 gpiochip_remove(&gpio_dev->gc);
885 static int amd_gpio_remove(struct platform_device *pdev)
887 struct amd_gpio *gpio_dev;
889 gpio_dev = platform_get_drvdata(pdev);
891 gpiochip_remove(&gpio_dev->gc);
896 static const struct acpi_device_id amd_gpio_acpi_match[] = {
902 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
904 static struct platform_driver amd_gpio_driver = {
907 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
908 #ifdef CONFIG_PM_SLEEP
909 .pm = &amd_gpio_pm_ops,
912 .probe = amd_gpio_probe,
913 .remove = amd_gpio_remove,
916 module_platform_driver(amd_gpio_driver);
918 MODULE_LICENSE("GPL v2");
919 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
920 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");