4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
13 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
17 #include <linux/err.h>
18 #include <linux/bug.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/compiler.h>
23 #include <linux/types.h>
24 #include <linux/errno.h>
25 #include <linux/log2.h>
27 #include <linux/gpio.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/acpi.h>
32 #include <linux/seq_file.h>
33 #include <linux/interrupt.h>
34 #include <linux/list.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
40 #include "pinctrl-utils.h"
41 #include "pinctrl-amd.h"
43 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
47 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
49 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
50 pin_reg = readl(gpio_dev->base + offset * 4);
51 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
53 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
60 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
62 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
63 pin_reg = readl(gpio_dev->base + offset * 4);
64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
65 writel(pin_reg, gpio_dev->base + offset * 4);
66 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
76 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
78 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
79 pin_reg = readl(gpio_dev->base + offset * 4);
80 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
82 pin_reg |= BIT(OUTPUT_VALUE_OFF);
84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
85 writel(pin_reg, gpio_dev->base + offset * 4);
86 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
95 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
97 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
98 pin_reg = readl(gpio_dev->base + offset * 4);
99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
101 return !!(pin_reg & BIT(PIN_STS_OFF));
104 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
108 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
110 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
111 pin_reg = readl(gpio_dev->base + offset * 4);
113 pin_reg |= BIT(OUTPUT_VALUE_OFF);
115 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
116 writel(pin_reg, gpio_dev->base + offset * 4);
117 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
120 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
127 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
129 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
130 pin_reg = readl(gpio_dev->base + offset * 4);
133 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
134 pin_reg &= ~DB_TMR_OUT_MASK;
136 Debounce Debounce Timer Max
137 TmrLarge TmrOutUnit Unit Debounce
139 0 0 61 usec (2 RtcClk) 976 usec
140 0 1 244 usec (8 RtcClk) 3.9 msec
141 1 0 15.6 msec (512 RtcClk) 250 msec
142 1 1 62.5 msec (2048 RtcClk) 1 sec
147 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
148 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
149 } else if (debounce < 976) {
150 time = debounce / 61;
151 pin_reg |= time & DB_TMR_OUT_MASK;
152 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
153 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
154 } else if (debounce < 3900) {
155 time = debounce / 244;
156 pin_reg |= time & DB_TMR_OUT_MASK;
157 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 } else if (debounce < 250000) {
160 time = debounce / 15625;
161 pin_reg |= time & DB_TMR_OUT_MASK;
162 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
163 pin_reg |= BIT(DB_TMR_LARGE_OFF);
164 } else if (debounce < 1000000) {
165 time = debounce / 62500;
166 pin_reg |= time & DB_TMR_OUT_MASK;
167 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
168 pin_reg |= BIT(DB_TMR_LARGE_OFF);
170 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
174 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
175 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
176 pin_reg &= ~DB_TMR_OUT_MASK;
177 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
179 writel(pin_reg, gpio_dev->base + offset * 4);
180 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
185 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
186 unsigned long config)
190 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
193 debounce = pinconf_to_config_argument(config);
194 return amd_gpio_set_debounce(gc, offset, debounce);
197 #ifdef CONFIG_DEBUG_FS
198 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
202 unsigned int bank, i, pin_num;
203 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
207 char *interrupt_enable;
208 char *interrupt_mask;
214 char *pull_up_enable;
215 char *pull_down_enable;
219 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
220 seq_printf(s, "GPIO bank%d\t", bank);
225 pin_num = AMD_GPIO_PINS_BANK0;
229 pin_num = AMD_GPIO_PINS_BANK1 + i;
233 pin_num = AMD_GPIO_PINS_BANK2 + i;
237 pin_num = AMD_GPIO_PINS_BANK3 + i;
240 /* Illegal bank number, ignore */
243 for (; i < pin_num; i++) {
244 seq_printf(s, "pin%d\t", i);
245 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
246 pin_reg = readl(gpio_dev->base + i * 4);
247 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
249 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
250 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
252 interrupt_enable = "interrupt is enabled|";
254 if (level == ACTIVE_LEVEL_HIGH)
255 active_level = "Active high|";
256 else if (level == ACTIVE_LEVEL_LOW)
257 active_level = "Active low|";
258 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
259 level == ACTIVE_LEVEL_BOTH)
260 active_level = "Active on both|";
262 active_level = "Unknown Active level|";
264 if (pin_reg & BIT(LEVEL_TRIG_OFF))
265 level_trig = "Level trigger|";
267 level_trig = "Edge trigger|";
271 "interrupt is disabled|";
276 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
278 "interrupt is unmasked|";
281 "interrupt is masked|";
283 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
284 wake_cntrl0 = "enable wakeup in S0i3 state|";
286 wake_cntrl0 = "disable wakeup in S0i3 state|";
288 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
289 wake_cntrl1 = "enable wakeup in S3 state|";
291 wake_cntrl1 = "disable wakeup in S3 state|";
293 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
294 wake_cntrl2 = "enable wakeup in S4/S5 state|";
296 wake_cntrl2 = "disable wakeup in S4/S5 state|";
298 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
299 pull_up_enable = "pull-up is enabled|";
300 if (pin_reg & BIT(PULL_UP_SEL_OFF))
301 pull_up_sel = "8k pull-up|";
303 pull_up_sel = "4k pull-up|";
305 pull_up_enable = "pull-up is disabled|";
309 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
310 pull_down_enable = "pull-down is enabled|";
312 pull_down_enable = "Pull-down is disabled|";
314 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
316 output_enable = "output is enabled|";
317 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
318 output_value = "output is high|";
320 output_value = "output is low|";
322 output_enable = "output is disabled|";
325 if (pin_reg & BIT(PIN_STS_OFF))
326 pin_sts = "input is high|";
328 pin_sts = "input is low|";
331 seq_printf(s, "%s %s %s %s %s %s\n"
332 " %s %s %s %s %s %s %s 0x%x\n",
333 level_trig, active_level, interrupt_enable,
334 interrupt_mask, wake_cntrl0, wake_cntrl1,
335 wake_cntrl2, pin_sts, pull_up_sel,
336 pull_up_enable, pull_down_enable,
337 output_value, output_enable, pin_reg);
342 #define amd_gpio_dbg_show NULL
345 static void amd_gpio_irq_enable(struct irq_data *d)
349 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
350 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
352 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
353 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
354 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
355 pin_reg |= BIT(INTERRUPT_MASK_OFF);
356 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
357 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
360 static void amd_gpio_irq_disable(struct irq_data *d)
364 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
367 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
368 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
369 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
370 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
371 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
372 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
375 static void amd_gpio_irq_mask(struct irq_data *d)
379 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
380 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
382 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
383 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
384 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
385 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
386 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
389 static void amd_gpio_irq_unmask(struct irq_data *d)
393 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
394 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
396 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
397 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
398 pin_reg |= BIT(INTERRUPT_MASK_OFF);
399 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
400 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
403 static void amd_gpio_irq_eoi(struct irq_data *d)
407 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
408 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
410 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
411 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
413 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
414 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
417 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
420 u32 pin_reg, pin_reg_irq_en, mask;
421 unsigned long flags, irq_flags;
422 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
425 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
426 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
428 /* Ignore the settings coming from the client and
429 * read the values from the ACPI tables
430 * while setting the trigger type
433 irq_flags = irq_get_trigger_type(d->irq);
434 if (irq_flags != IRQ_TYPE_NONE)
437 switch (type & IRQ_TYPE_SENSE_MASK) {
438 case IRQ_TYPE_EDGE_RISING:
439 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
440 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
441 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
442 irq_set_handler_locked(d, handle_edge_irq);
445 case IRQ_TYPE_EDGE_FALLING:
446 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
447 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
448 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
449 irq_set_handler_locked(d, handle_edge_irq);
452 case IRQ_TYPE_EDGE_BOTH:
453 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
454 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
455 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
456 irq_set_handler_locked(d, handle_edge_irq);
459 case IRQ_TYPE_LEVEL_HIGH:
460 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
461 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
462 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
463 irq_set_handler_locked(d, handle_level_irq);
466 case IRQ_TYPE_LEVEL_LOW:
467 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
468 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
469 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
470 irq_set_handler_locked(d, handle_level_irq);
477 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
481 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
483 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
484 * debounce registers of any GPIO will block wake/interrupt status
485 * generation for *all* GPIOs for a lenght of time that depends on
486 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
487 * INTERRUPT_ENABLE bit will read as 0.
489 * We temporarily enable irq for the GPIO whose configuration is
490 * changing, and then wait for it to read back as 1 to know when
491 * debounce has settled and then disable the irq again.
492 * We do this polling with the spinlock held to ensure other GPIO
493 * access routines do not read an incorrect value for the irq enable
494 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
495 * spurious irqs, and disable the irq again after polling.
497 mask = BIT(INTERRUPT_ENABLE_OFF);
498 pin_reg_irq_en = pin_reg;
499 pin_reg_irq_en |= mask;
500 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
501 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
502 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
504 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
505 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
510 static void amd_irq_ack(struct irq_data *d)
513 * based on HW design,there is no need to ack HW
514 * before handle current irq. But this routine is
515 * necessary for handle_edge_irq
519 static struct irq_chip amd_gpio_irqchip = {
521 .irq_ack = amd_irq_ack,
522 .irq_enable = amd_gpio_irq_enable,
523 .irq_disable = amd_gpio_irq_disable,
524 .irq_mask = amd_gpio_irq_mask,
525 .irq_unmask = amd_gpio_irq_unmask,
526 .irq_eoi = amd_gpio_irq_eoi,
527 .irq_set_type = amd_gpio_irq_set_type,
528 .flags = IRQCHIP_SKIP_SET_WAKE,
531 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
533 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
535 struct amd_gpio *gpio_dev = dev_id;
536 struct gpio_chip *gc = &gpio_dev->gc;
537 irqreturn_t ret = IRQ_NONE;
538 unsigned int i, irqnr;
544 /* Read the wake status */
545 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
546 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
548 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
549 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
551 /* Bit 0-45 contain the relevant status bits */
552 status &= (1ULL << 46) - 1;
553 regs = gpio_dev->base;
554 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
555 if (!(status & mask))
559 /* Each status bit covers four pins */
560 for (i = 0; i < 4; i++) {
561 regval = readl(regs + i);
562 if (!(regval & PIN_IRQ_PENDING) ||
563 !(regval & BIT(INTERRUPT_MASK_OFF)))
565 irq = irq_find_mapping(gc->irq.domain, irqnr + i);
567 generic_handle_irq(irq);
570 * We must read the pin register again, in case the
571 * value was changed while executing
572 * generic_handle_irq() above.
573 * If we didn't find a mapping for the interrupt,
574 * disable it in order to avoid a system hang caused
575 * by an interrupt storm.
577 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
578 regval = readl(regs + i);
580 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
581 dev_dbg(&gpio_dev->pdev->dev,
582 "Disabling spurious GPIO IRQ %d\n",
585 writel(regval, regs + i);
586 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
591 /* Signal EOI to the GPIO unit */
592 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
593 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
595 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
596 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
601 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
603 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
605 return gpio_dev->ngroups;
608 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
611 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
613 return gpio_dev->groups[group].name;
616 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
618 const unsigned **pins,
621 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
623 *pins = gpio_dev->groups[group].pins;
624 *num_pins = gpio_dev->groups[group].npins;
628 static const struct pinctrl_ops amd_pinctrl_ops = {
629 .get_groups_count = amd_get_groups_count,
630 .get_group_name = amd_get_group_name,
631 .get_group_pins = amd_get_group_pins,
633 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
634 .dt_free_map = pinctrl_utils_free_map,
638 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
640 unsigned long *config)
645 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
646 enum pin_config_param param = pinconf_to_config_param(*config);
648 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
649 pin_reg = readl(gpio_dev->base + pin*4);
650 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
652 case PIN_CONFIG_INPUT_DEBOUNCE:
653 arg = pin_reg & DB_TMR_OUT_MASK;
656 case PIN_CONFIG_BIAS_PULL_DOWN:
657 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
660 case PIN_CONFIG_BIAS_PULL_UP:
661 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
664 case PIN_CONFIG_DRIVE_STRENGTH:
665 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
669 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
674 *config = pinconf_to_config_packed(param, arg);
679 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
680 unsigned long *configs, unsigned num_configs)
687 enum pin_config_param param;
688 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
690 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
691 for (i = 0; i < num_configs; i++) {
692 param = pinconf_to_config_param(configs[i]);
693 arg = pinconf_to_config_argument(configs[i]);
694 pin_reg = readl(gpio_dev->base + pin*4);
697 case PIN_CONFIG_INPUT_DEBOUNCE:
698 pin_reg &= ~DB_TMR_OUT_MASK;
699 pin_reg |= arg & DB_TMR_OUT_MASK;
702 case PIN_CONFIG_BIAS_PULL_DOWN:
703 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
704 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
707 case PIN_CONFIG_BIAS_PULL_UP:
708 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
709 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
710 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
711 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
714 case PIN_CONFIG_DRIVE_STRENGTH:
715 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
716 << DRV_STRENGTH_SEL_OFF);
717 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
718 << DRV_STRENGTH_SEL_OFF;
722 dev_err(&gpio_dev->pdev->dev,
723 "Invalid config param %04x\n", param);
727 writel(pin_reg, gpio_dev->base + pin*4);
729 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
734 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
736 unsigned long *config)
738 const unsigned *pins;
742 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
746 if (amd_pinconf_get(pctldev, pins[0], config))
752 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
753 unsigned group, unsigned long *configs,
754 unsigned num_configs)
756 const unsigned *pins;
760 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
763 for (i = 0; i < npins; i++) {
764 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
770 static const struct pinconf_ops amd_pinconf_ops = {
771 .pin_config_get = amd_pinconf_get,
772 .pin_config_set = amd_pinconf_set,
773 .pin_config_group_get = amd_pinconf_group_get,
774 .pin_config_group_set = amd_pinconf_group_set,
777 #ifdef CONFIG_PM_SLEEP
778 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
780 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
786 * Only restore the pin if it is actually in use by the kernel (or
789 if (pd->mux_owner || pd->gpio_owner ||
790 gpiochip_line_is_irq(&gpio_dev->gc, pin))
796 static int amd_gpio_suspend(struct device *dev)
798 struct platform_device *pdev = to_platform_device(dev);
799 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
800 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
803 for (i = 0; i < desc->npins; i++) {
804 int pin = desc->pins[i].number;
806 if (!amd_gpio_should_save(gpio_dev, pin))
809 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
815 static int amd_gpio_resume(struct device *dev)
817 struct platform_device *pdev = to_platform_device(dev);
818 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
819 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
822 for (i = 0; i < desc->npins; i++) {
823 int pin = desc->pins[i].number;
825 if (!amd_gpio_should_save(gpio_dev, pin))
828 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
834 static const struct dev_pm_ops amd_gpio_pm_ops = {
835 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
840 static struct pinctrl_desc amd_pinctrl_desc = {
842 .npins = ARRAY_SIZE(kerncz_pins),
843 .pctlops = &amd_pinctrl_ops,
844 .confops = &amd_pinconf_ops,
845 .owner = THIS_MODULE,
848 static int amd_gpio_probe(struct platform_device *pdev)
852 struct resource *res;
853 struct amd_gpio *gpio_dev;
855 gpio_dev = devm_kzalloc(&pdev->dev,
856 sizeof(struct amd_gpio), GFP_KERNEL);
860 raw_spin_lock_init(&gpio_dev->lock);
862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
864 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
868 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
873 irq_base = platform_get_irq(pdev, 0);
875 dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
879 #ifdef CONFIG_PM_SLEEP
880 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
881 sizeof(*gpio_dev->saved_regs),
883 if (!gpio_dev->saved_regs)
887 gpio_dev->pdev = pdev;
888 gpio_dev->gc.get_direction = amd_gpio_get_direction;
889 gpio_dev->gc.direction_input = amd_gpio_direction_input;
890 gpio_dev->gc.direction_output = amd_gpio_direction_output;
891 gpio_dev->gc.get = amd_gpio_get_value;
892 gpio_dev->gc.set = amd_gpio_set_value;
893 gpio_dev->gc.set_config = amd_gpio_set_config;
894 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
896 gpio_dev->gc.base = -1;
897 gpio_dev->gc.label = pdev->name;
898 gpio_dev->gc.owner = THIS_MODULE;
899 gpio_dev->gc.parent = &pdev->dev;
900 gpio_dev->gc.ngpio = resource_size(res) / 4;
901 #if defined(CONFIG_OF_GPIO)
902 gpio_dev->gc.of_node = pdev->dev.of_node;
905 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
906 gpio_dev->groups = kerncz_groups;
907 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
909 amd_pinctrl_desc.name = dev_name(&pdev->dev);
910 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
912 if (IS_ERR(gpio_dev->pctrl)) {
913 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
914 return PTR_ERR(gpio_dev->pctrl);
917 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
921 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
922 0, 0, gpio_dev->gc.ngpio);
924 dev_err(&pdev->dev, "Failed to add pin range\n");
928 ret = gpiochip_irqchip_add(&gpio_dev->gc,
934 dev_err(&pdev->dev, "could not add irqchip\n");
939 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
940 KBUILD_MODNAME, gpio_dev);
944 platform_set_drvdata(pdev, gpio_dev);
946 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
950 gpiochip_remove(&gpio_dev->gc);
955 static int amd_gpio_remove(struct platform_device *pdev)
957 struct amd_gpio *gpio_dev;
959 gpio_dev = platform_get_drvdata(pdev);
961 gpiochip_remove(&gpio_dev->gc);
966 static const struct acpi_device_id amd_gpio_acpi_match[] = {
972 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
974 static struct platform_driver amd_gpio_driver = {
977 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
978 #ifdef CONFIG_PM_SLEEP
979 .pm = &amd_gpio_pm_ops,
982 .probe = amd_gpio_probe,
983 .remove = amd_gpio_remove,
986 module_platform_driver(amd_gpio_driver);
988 MODULE_LICENSE("GPL v2");
989 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
990 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");