1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2013
5 * Author: Patrice Chotard <patrice.chotard@st.com>
7 * Driver allows to use AxB5xx unused pins to be used as GPIO
10 #include <linux/bitops.h>
11 #include <linux/cleanup.h>
12 #include <linux/err.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 #include <linux/seq_file.h>
24 #include <linux/slab.h>
25 #include <linux/types.h>
27 #include <linux/mfd/abx500.h>
28 #include <linux/mfd/abx500/ab8500.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinconf.h>
34 #include <linux/pinctrl/pinctrl.h>
35 #include <linux/pinctrl/pinmux.h>
38 #include "../pinconf.h"
39 #include "../pinctrl-utils.h"
41 #include "pinctrl-abx500.h"
44 * GPIO registers offset
47 #define AB8500_GPIO_SEL1_REG 0x00
48 #define AB8500_GPIO_SEL2_REG 0x01
49 #define AB8500_GPIO_SEL3_REG 0x02
50 #define AB8500_GPIO_SEL4_REG 0x03
51 #define AB8500_GPIO_SEL5_REG 0x04
52 #define AB8500_GPIO_SEL6_REG 0x05
54 #define AB8500_GPIO_DIR1_REG 0x10
55 #define AB8500_GPIO_DIR2_REG 0x11
56 #define AB8500_GPIO_DIR3_REG 0x12
57 #define AB8500_GPIO_DIR4_REG 0x13
58 #define AB8500_GPIO_DIR5_REG 0x14
59 #define AB8500_GPIO_DIR6_REG 0x15
61 #define AB8500_GPIO_OUT1_REG 0x20
62 #define AB8500_GPIO_OUT2_REG 0x21
63 #define AB8500_GPIO_OUT3_REG 0x22
64 #define AB8500_GPIO_OUT4_REG 0x23
65 #define AB8500_GPIO_OUT5_REG 0x24
66 #define AB8500_GPIO_OUT6_REG 0x25
68 #define AB8500_GPIO_PUD1_REG 0x30
69 #define AB8500_GPIO_PUD2_REG 0x31
70 #define AB8500_GPIO_PUD3_REG 0x32
71 #define AB8500_GPIO_PUD4_REG 0x33
72 #define AB8500_GPIO_PUD5_REG 0x34
73 #define AB8500_GPIO_PUD6_REG 0x35
75 #define AB8500_GPIO_IN1_REG 0x40
76 #define AB8500_GPIO_IN2_REG 0x41
77 #define AB8500_GPIO_IN3_REG 0x42
78 #define AB8500_GPIO_IN4_REG 0x43
79 #define AB8500_GPIO_IN5_REG 0x44
80 #define AB8500_GPIO_IN6_REG 0x45
81 #define AB8500_GPIO_ALTFUN_REG 0x50
83 #define ABX500_GPIO_INPUT 0
84 #define ABX500_GPIO_OUTPUT 1
86 struct abx500_pinctrl {
88 struct pinctrl_dev *pctldev;
89 struct abx500_pinctrl_soc_data *soc;
90 struct gpio_chip chip;
91 struct ab8500 *parent;
92 struct abx500_gpio_irq_cluster *irq_cluster;
96 static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
97 unsigned offset, bool *bit)
99 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
105 ret = abx500_get_register_interruptible(pct->dev,
106 AB8500_MISC, reg, &val);
109 "%s read reg =%x, offset=%x failed (%d)\n",
110 __func__, reg, offset, ret);
114 *bit = !!(val & BIT(pos));
119 static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
120 unsigned offset, int val)
122 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
127 ret = abx500_mask_and_set_register_interruptible(pct->dev,
128 AB8500_MISC, reg, BIT(pos), val << pos);
130 dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n",
131 __func__, reg, offset, ret);
137 * abx500_gpio_get() - Get the particular GPIO value
139 * @offset: GPIO number to read
141 static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
143 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
146 u8 gpio_offset = offset - 1;
149 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
150 gpio_offset, &is_out);
155 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
158 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
162 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
169 static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
171 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
174 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
176 dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
179 static int abx500_gpio_direction_output(struct gpio_chip *chip,
183 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
186 /* set direction as output */
187 ret = abx500_gpio_set_bits(chip,
188 AB8500_GPIO_DIR1_REG,
194 /* disable pull down */
195 ret = abx500_gpio_set_bits(chip,
196 AB8500_GPIO_PUD1_REG,
198 ABX500_GPIO_PULL_NONE);
202 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
206 /* set the output as 1 or 0 */
207 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
210 static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
212 /* set the register as input */
213 return abx500_gpio_set_bits(chip,
214 AB8500_GPIO_DIR1_REG,
219 static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
221 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
222 /* The AB8500 GPIO numbers are off by one */
223 int gpio = offset + 1;
227 for (i = 0; i < pct->irq_cluster_size; i++) {
228 struct abx500_gpio_irq_cluster *cluster =
229 &pct->irq_cluster[i];
231 if (gpio >= cluster->start && gpio <= cluster->end) {
233 * The ABx500 GPIO's associated IRQs are clustered together
234 * throughout the interrupt numbers at irregular intervals.
235 * To solve this quandry, we have placed the read-in values
236 * into the cluster information table.
238 hwirq = gpio - cluster->start + cluster->to_irq;
239 return irq_create_mapping(pct->parent->domain, hwirq);
246 static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
247 unsigned gpio, int alt_setting)
249 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
250 struct alternate_functions af = pct->soc->alternate_functions[gpio];
255 const char *modes[] = {
256 [ABX500_DEFAULT] = "default",
257 [ABX500_ALT_A] = "altA",
258 [ABX500_ALT_B] = "altB",
259 [ABX500_ALT_C] = "altC",
263 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
264 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
265 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
266 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
271 /* on ABx5xx, there is no GPIO0, so adjust the offset */
274 switch (alt_setting) {
277 * for ABx5xx family, default mode is always selected by
278 * writing 0 to GPIOSELx register, except for pins which
279 * support at least ALT_B mode, default mode is selected
280 * by writing 1 to GPIOSELx register
283 if (af.alt_bit1 != UNUSED)
286 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
292 * for ABx5xx family, alt_a mode is always selected by
293 * writing 1 to GPIOSELx register, except for pins which
294 * support at least ALT_B mode, alt_a mode is selected
295 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
298 if (af.alt_bit1 != UNUSED) {
299 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
304 ret = abx500_gpio_set_bits(chip,
305 AB8500_GPIO_ALTFUN_REG,
307 !!(af.alta_val & BIT(0)));
311 if (af.alt_bit2 != UNUSED)
312 ret = abx500_gpio_set_bits(chip,
313 AB8500_GPIO_ALTFUN_REG,
315 !!(af.alta_val & BIT(1)));
317 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
322 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
327 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
328 af.alt_bit1, !!(af.altb_val & BIT(0)));
332 if (af.alt_bit2 != UNUSED)
333 ret = abx500_gpio_set_bits(chip,
334 AB8500_GPIO_ALTFUN_REG,
336 !!(af.altb_val & BIT(1)));
340 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
345 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
346 af.alt_bit2, !!(af.altc_val & BIT(0)));
350 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
351 af.alt_bit2, !!(af.altc_val & BIT(1)));
355 dev_dbg(pct->dev, "unknown alt_setting %d\n", alt_setting);
361 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
366 #ifdef CONFIG_DEBUG_FS
367 static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
374 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
375 struct alternate_functions af = pct->soc->alternate_functions[gpio];
376 /* on ABx5xx, there is no GPIO0, so adjust the offset */
377 unsigned offset = gpio - 1;
381 * if gpiosel_bit is set to unused,
382 * it means no GPIO or special case
384 if (af.gpiosel_bit == UNUSED)
385 return ABX500_DEFAULT;
387 /* read GpioSelx register */
388 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
389 af.gpiosel_bit, &bit_mode);
396 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
397 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
399 "alt_bitX value not in correct range (-1 to 7)\n");
403 /* if alt_bit2 is used, alt_bit1 must be used too */
404 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
406 "if alt_bit2 is used, alt_bit1 can't be unused\n");
410 /* check if pin use AlternateFunction register */
411 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
414 * if pin GPIOSEL bit is set and pin supports alternate function,
415 * it means DEFAULT mode
418 return ABX500_DEFAULT;
421 * pin use the AlternatFunction register
422 * read alt_bit1 value
424 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
425 af.alt_bit1, &alt_bit1);
429 if (af.alt_bit2 != UNUSED) {
430 /* read alt_bit2 value */
431 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
439 mode = (alt_bit2 << 1) + alt_bit1;
440 if (mode == af.alta_val)
442 else if (mode == af.altb_val)
448 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
452 static void abx500_gpio_dbg_show_one(struct seq_file *s,
453 struct pinctrl_dev *pctldev,
454 struct gpio_chip *chip,
455 unsigned offset, unsigned gpio)
457 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
458 u8 gpio_offset = offset - 1;
464 const char *modes[] = {
465 [ABX500_DEFAULT] = "default",
466 [ABX500_ALT_A] = "altA",
467 [ABX500_ALT_B] = "altB",
468 [ABX500_ALT_C] = "altC",
471 const char *pull_up_down[] = {
472 [ABX500_GPIO_PULL_DOWN] = "pull down",
473 [ABX500_GPIO_PULL_NONE] = "pull none",
474 [ABX500_GPIO_PULL_NONE + 1] = "pull none",
475 [ABX500_GPIO_PULL_UP] = "pull up",
478 char *label __free(kfree) = gpiochip_dup_line_label(chip, offset - 1);
482 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
483 gpio_offset, &is_out);
487 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
488 gpio, label ?: "(none)",
489 is_out ? "out" : "in ");
492 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
497 seq_printf(s, " %-9s", pull_up_down[pd]);
499 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
501 mode = abx500_get_mode(pctldev, chip, offset);
503 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
507 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
510 static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
513 unsigned gpio = chip->base;
514 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
515 struct pinctrl_dev *pctldev = pct->pctldev;
517 for (i = 0; i < chip->ngpio; i++, gpio++) {
518 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
519 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
525 static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
526 struct pinctrl_dev *pctldev,
527 struct gpio_chip *chip,
528 unsigned offset, unsigned gpio)
531 #define abx500_gpio_dbg_show NULL
534 static const struct gpio_chip abx500gpio_chip = {
535 .label = "abx500-gpio",
536 .owner = THIS_MODULE,
537 .request = gpiochip_generic_request,
538 .free = gpiochip_generic_free,
539 .direction_input = abx500_gpio_direction_input,
540 .get = abx500_gpio_get,
541 .direction_output = abx500_gpio_direction_output,
542 .set = abx500_gpio_set,
543 .to_irq = abx500_gpio_to_irq,
544 .dbg_show = abx500_gpio_dbg_show,
547 static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
549 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
551 return pct->soc->nfunctions;
554 static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
557 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
559 return pct->soc->functions[function].name;
562 static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
564 const char * const **groups,
565 unsigned * const num_groups)
567 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
569 *groups = pct->soc->functions[function].groups;
570 *num_groups = pct->soc->functions[function].ngroups;
575 static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
578 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
579 struct gpio_chip *chip = &pct->chip;
580 const struct abx500_pingroup *g;
584 g = &pct->soc->groups[group];
585 if (g->altsetting < 0)
588 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
590 for (i = 0; i < g->npins; i++) {
591 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
592 g->pins[i], g->altsetting);
594 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
598 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
603 static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
604 struct pinctrl_gpio_range *range,
607 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
608 const struct abx500_pinrange *p;
613 * Different ranges have different ways to enable GPIO function on a
614 * pin, so refer back to our local range type, where we handily define
615 * what altfunc enables GPIO for a certain pin.
617 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
618 p = &pct->soc->gpio_ranges[i];
619 if ((offset >= p->offset) &&
620 (offset < (p->offset + p->npins)))
624 if (i == pct->soc->gpio_num_ranges) {
625 dev_err(pct->dev, "%s failed to locate range\n", __func__);
629 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
632 ret = abx500_set_mode(pct->pctldev, &pct->chip,
635 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
640 static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
641 struct pinctrl_gpio_range *range,
646 static const struct pinmux_ops abx500_pinmux_ops = {
647 .get_functions_count = abx500_pmx_get_funcs_cnt,
648 .get_function_name = abx500_pmx_get_func_name,
649 .get_function_groups = abx500_pmx_get_func_groups,
650 .set_mux = abx500_pmx_set,
651 .gpio_request_enable = abx500_gpio_request_enable,
652 .gpio_disable_free = abx500_gpio_disable_free,
655 static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
657 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
659 return pct->soc->ngroups;
662 static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
665 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
667 return pct->soc->groups[selector].name;
670 static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
672 const unsigned **pins,
675 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
677 *pins = pct->soc->groups[selector].pins;
678 *num_pins = pct->soc->groups[selector].npins;
683 static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
684 struct seq_file *s, unsigned offset)
686 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
687 struct gpio_chip *chip = &pct->chip;
689 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
690 chip->base + offset - 1);
693 static int abx500_dt_add_map_mux(struct pinctrl_map **map,
694 unsigned *reserved_maps,
695 unsigned *num_maps, const char *group,
696 const char *function)
698 if (*num_maps == *reserved_maps)
701 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
702 (*map)[*num_maps].data.mux.group = group;
703 (*map)[*num_maps].data.mux.function = function;
709 static int abx500_dt_add_map_configs(struct pinctrl_map **map,
710 unsigned *reserved_maps,
711 unsigned *num_maps, const char *group,
712 unsigned long *configs, unsigned num_configs)
714 unsigned long *dup_configs;
716 if (*num_maps == *reserved_maps)
719 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
724 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
726 (*map)[*num_maps].data.configs.group_or_pin = group;
727 (*map)[*num_maps].data.configs.configs = dup_configs;
728 (*map)[*num_maps].data.configs.num_configs = num_configs;
734 static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
735 const char *pin_name)
738 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
740 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
741 for (i = 0; i < npct->soc->npins; i++)
742 if (npct->soc->pins[i].number == pin_number)
743 return npct->soc->pins[i].name;
747 static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
748 struct device_node *np,
749 struct pinctrl_map **map,
750 unsigned *reserved_maps,
754 const char *function = NULL;
755 unsigned long *configs;
756 unsigned int nconfigs = 0;
757 struct property *prop;
759 ret = of_property_read_string(np, "function", &function);
763 ret = of_property_count_strings(np, "groups");
767 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
772 of_property_for_each_string(np, "groups", prop, group) {
773 ret = abx500_dt_add_map_mux(map, reserved_maps,
774 num_maps, group, function);
780 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs);
782 const char *gpio_name;
785 ret = of_property_count_strings(np, "pins");
789 ret = pinctrl_utils_reserve_map(pctldev, map,
795 of_property_for_each_string(np, "pins", prop, pin) {
796 gpio_name = abx500_find_pin_name(pctldev, pin);
798 ret = abx500_dt_add_map_configs(map, reserved_maps,
799 num_maps, gpio_name, configs, 1);
809 static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
810 struct device_node *np_config,
811 struct pinctrl_map **map, unsigned *num_maps)
813 unsigned reserved_maps;
814 struct device_node *np;
821 for_each_child_of_node(np_config, np) {
822 ret = abx500_dt_subnode_to_map(pctldev, np, map,
823 &reserved_maps, num_maps);
825 pinctrl_utils_free_map(pctldev, *map, *num_maps);
834 static const struct pinctrl_ops abx500_pinctrl_ops = {
835 .get_groups_count = abx500_get_groups_cnt,
836 .get_group_name = abx500_get_group_name,
837 .get_group_pins = abx500_get_group_pins,
838 .pin_dbg_show = abx500_pin_dbg_show,
839 .dt_node_to_map = abx500_dt_node_to_map,
840 .dt_free_map = pinctrl_utils_free_map,
843 static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
845 unsigned long *config)
850 static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
852 unsigned long *configs,
853 unsigned num_configs)
855 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
856 struct gpio_chip *chip = &pct->chip;
860 enum pin_config_param param;
861 enum pin_config_param argument;
863 for (i = 0; i < num_configs; i++) {
864 param = pinconf_to_config_param(configs[i]);
865 argument = pinconf_to_config_argument(configs[i]);
867 dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
869 (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
870 (param == PIN_CONFIG_OUTPUT) ?
871 (argument ? "high" : "low") :
872 (argument ? "pull up" : "pull down"));
874 /* on ABx500, there is no GPIO0, so adjust the offset */
878 case PIN_CONFIG_BIAS_DISABLE:
879 ret = abx500_gpio_direction_input(chip, offset);
883 /* Chip only supports pull down */
884 ret = abx500_gpio_set_bits(chip,
885 AB8500_GPIO_PUD1_REG, offset,
886 ABX500_GPIO_PULL_NONE);
889 case PIN_CONFIG_BIAS_PULL_DOWN:
890 ret = abx500_gpio_direction_input(chip, offset);
894 * if argument = 1 set the pull down
895 * else clear the pull down
896 * Chip only supports pull down
898 ret = abx500_gpio_set_bits(chip,
899 AB8500_GPIO_PUD1_REG,
901 argument ? ABX500_GPIO_PULL_DOWN :
902 ABX500_GPIO_PULL_NONE);
905 case PIN_CONFIG_BIAS_PULL_UP:
906 ret = abx500_gpio_direction_input(chip, offset);
910 * if argument = 1 set the pull up
911 * else clear the pull up
913 ret = abx500_gpio_direction_input(chip, offset);
916 case PIN_CONFIG_OUTPUT:
917 ret = abx500_gpio_direction_output(chip, offset,
922 dev_err(chip->parent,
923 "illegal configuration requested\n");
925 } /* for each config */
928 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
933 static const struct pinconf_ops abx500_pinconf_ops = {
934 .pin_config_get = abx500_pin_config_get,
935 .pin_config_set = abx500_pin_config_set,
939 static struct pinctrl_desc abx500_pinctrl_desc = {
940 .name = "pinctrl-abx500",
941 .pctlops = &abx500_pinctrl_ops,
942 .pmxops = &abx500_pinmux_ops,
943 .confops = &abx500_pinconf_ops,
944 .owner = THIS_MODULE,
947 static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
949 unsigned int lowest = 0;
950 unsigned int highest = 0;
951 unsigned int npins = 0;
955 * Compute number of GPIOs from the last SoC gpio range descriptors
956 * These ranges may include "holes" but the GPIO number space shall
957 * still be homogeneous, so we need to detect and account for any
958 * such holes so that these are included in the number of GPIO pins.
960 for (i = 0; i < soc->gpio_num_ranges; i++) {
963 const struct abx500_pinrange *p;
965 p = &soc->gpio_ranges[i];
967 gend = p->offset + p->npins - 1;
970 /* First iteration, set start values */
980 /* this gives the absolute number of pins */
981 npins = highest - lowest + 1;
985 static const struct of_device_id abx500_gpio_match[] = {
986 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
987 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
991 static int abx500_gpio_probe(struct platform_device *pdev)
993 struct device_node *np = pdev->dev.of_node;
994 struct abx500_pinctrl *pct;
995 unsigned int id = -1;
1000 dev_err(&pdev->dev, "gpio dt node missing\n");
1004 pct = devm_kzalloc(&pdev->dev, sizeof(*pct), GFP_KERNEL);
1008 pct->dev = &pdev->dev;
1009 pct->parent = dev_get_drvdata(pdev->dev.parent);
1010 pct->chip = abx500gpio_chip;
1011 pct->chip.parent = &pdev->dev;
1012 pct->chip.base = -1; /* Dynamic allocation */
1014 id = (unsigned long)device_get_match_data(&pdev->dev);
1016 /* Poke in other ASIC variants here */
1018 case PINCTRL_AB8500:
1019 abx500_pinctrl_ab8500_init(&pct->soc);
1021 case PINCTRL_AB8505:
1022 abx500_pinctrl_ab8505_init(&pct->soc);
1025 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
1030 dev_err(&pdev->dev, "Invalid SOC data\n");
1034 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1035 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1036 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
1038 ret = gpiochip_add_data(&pct->chip, pct);
1040 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
1043 dev_info(&pdev->dev, "added gpiochip\n");
1045 abx500_pinctrl_desc.pins = pct->soc->pins;
1046 abx500_pinctrl_desc.npins = pct->soc->npins;
1047 pct->pctldev = devm_pinctrl_register(&pdev->dev, &abx500_pinctrl_desc,
1049 if (IS_ERR(pct->pctldev)) {
1051 "could not register abx500 pinctrl driver\n");
1052 ret = PTR_ERR(pct->pctldev);
1055 dev_info(&pdev->dev, "registered pin controller\n");
1057 /* We will handle a range of GPIO pins */
1058 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1059 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1061 ret = gpiochip_add_pin_range(&pct->chip,
1062 dev_name(&pdev->dev),
1063 p->offset - 1, p->offset, p->npins);
1068 platform_set_drvdata(pdev, pct);
1069 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1074 gpiochip_remove(&pct->chip);
1079 * abx500_gpio_remove() - remove Ab8500-gpio driver
1080 * @pdev: Platform device registered
1082 static void abx500_gpio_remove(struct platform_device *pdev)
1084 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1086 gpiochip_remove(&pct->chip);
1089 static struct platform_driver abx500_gpio_driver = {
1091 .name = "abx500-gpio",
1092 .of_match_table = abx500_gpio_match,
1094 .probe = abx500_gpio_probe,
1095 .remove_new = abx500_gpio_remove,
1098 static int __init abx500_gpio_init(void)
1100 return platform_driver_register(&abx500_gpio_driver);
1102 core_initcall(abx500_gpio_init);