2 * Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "../pinctrl-utils.h"
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
37 #define IRQ_STATUS 0x10
41 #define GPIO_PER_REG 32
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
58 struct armada_37xx_pin_group {
60 unsigned int start_pin;
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
70 struct armada_37xx_pin_data {
73 struct armada_37xx_pin_group *groups;
77 struct armada_37xx_pmx_func {
83 struct armada_37xx_pinctrl {
84 struct regmap *regmap;
86 const struct armada_37xx_pin_data *data;
88 struct gpio_chip gpio_chip;
89 struct irq_chip irq_chip;
91 struct pinctrl_desc pctl;
92 struct pinctrl_dev *pctl_dev;
93 struct armada_37xx_pin_group *groups;
95 struct armada_37xx_pmx_func *funcs;
99 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
102 .start_pin = _start, \
106 .funcs = {_func1, _func2} \
109 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
112 .start_pin = _start, \
116 .funcs = {_func1, "gpio"} \
119 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
122 .start_pin = _start, \
125 .val = {_val1, _val2}, \
126 .funcs = {_func1, "gpio"} \
129 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
132 .start_pin = _start, \
135 .val = {_v1, _v2, _v3}, \
136 .funcs = {_f1, _f2, "gpio"} \
139 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
143 .start_pin = _start, \
147 .extra_pin = _start2, \
148 .extra_npins = _nr2, \
149 .funcs = {_f1, _f2} \
152 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
153 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
154 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
155 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
156 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
158 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
160 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
162 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
164 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
165 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
166 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
167 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
168 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
169 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
170 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
171 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
172 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
173 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
174 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
175 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
176 18, 2, "gpio", "uart"),
179 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
180 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
181 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
182 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
183 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
184 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
185 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
186 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
187 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
188 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
189 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
190 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
191 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
195 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
198 .groups = armada_37xx_nb_groups,
199 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
202 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
205 .groups = armada_37xx_sb_groups,
206 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
209 static inline void armada_37xx_update_reg(unsigned int *reg,
210 unsigned int *offset)
212 /* We never have more than 2 registers */
213 if (*offset >= GPIO_PER_REG) {
214 *offset -= GPIO_PER_REG;
219 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
224 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
225 if (!strcmp(grp->funcs[f], func))
231 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
232 struct armada_37xx_pinctrl *info, int pin, int *grp)
234 while (*grp < info->ngroups) {
235 struct armada_37xx_pin_group *group = &info->groups[*grp];
239 for (j = 0; j < (group->npins + group->extra_npins); j++)
240 if (group->pins[j] == pin)
246 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
247 unsigned int selector, unsigned long *config)
252 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
253 unsigned int selector, unsigned long *configs,
254 unsigned int num_configs)
259 static const struct pinconf_ops armada_37xx_pinconf_ops = {
261 .pin_config_group_get = armada_37xx_pin_config_group_get,
262 .pin_config_group_set = armada_37xx_pin_config_group_set,
265 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
267 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
269 return info->ngroups;
272 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
275 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
277 return info->groups[group].name;
280 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
281 unsigned int selector,
282 const unsigned int **pins,
285 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
287 if (selector >= info->ngroups)
290 *pins = info->groups[selector].pins;
291 *npins = info->groups[selector].npins +
292 info->groups[selector].extra_npins;
297 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
298 .get_groups_count = armada_37xx_get_groups_count,
299 .get_group_name = armada_37xx_get_group_name,
300 .get_group_pins = armada_37xx_get_group_pins,
301 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
302 .dt_free_map = pinctrl_utils_free_map,
306 * Pinmux_ops handling
309 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
311 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
316 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
317 unsigned int selector)
319 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
321 return info->funcs[selector].name;
324 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
325 unsigned int selector,
326 const char * const **groups,
327 unsigned int * const num_groups)
329 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
331 *groups = info->funcs[selector].groups;
332 *num_groups = info->funcs[selector].ngroups;
337 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
339 struct armada_37xx_pin_group *grp)
341 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
342 unsigned int reg = SELECTION;
343 unsigned int mask = grp->reg_mask;
346 dev_dbg(info->dev, "enable function %s group %s\n",
349 func = armada_37xx_get_func_reg(grp, name);
354 val = grp->val[func];
356 regmap_update_bits(info->regmap, reg, mask, val);
361 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
362 unsigned int selector,
366 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
367 struct armada_37xx_pin_group *grp = &info->groups[group];
368 const char *name = info->funcs[selector].name;
370 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
373 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
376 int offset = irqd_to_hwirq(d);
378 armada_37xx_update_reg(reg, &offset);
381 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
384 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
385 unsigned int reg = OUTPUT_EN;
388 armada_37xx_update_reg(®, &offset);
391 return regmap_update_bits(info->regmap, reg, mask, 0);
394 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
397 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
398 unsigned int reg = OUTPUT_EN;
399 unsigned int val, mask;
401 armada_37xx_update_reg(®, &offset);
403 regmap_read(info->regmap, reg, &val);
405 return !(val & mask);
408 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
409 unsigned int offset, int value)
411 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
412 unsigned int reg = OUTPUT_EN;
413 unsigned int mask, val, ret;
415 armada_37xx_update_reg(®, &offset);
418 ret = regmap_update_bits(info->regmap, reg, mask, mask);
424 val = value ? mask : 0;
425 regmap_update_bits(info->regmap, reg, mask, val);
430 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
432 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
433 unsigned int reg = INPUT_VAL;
434 unsigned int val, mask;
436 armada_37xx_update_reg(®, &offset);
439 regmap_read(info->regmap, reg, &val);
441 return (val & mask) != 0;
444 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
447 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
448 unsigned int reg = OUTPUT_VAL;
449 unsigned int mask, val;
451 armada_37xx_update_reg(®, &offset);
453 val = value ? mask : 0;
455 regmap_update_bits(info->regmap, reg, mask, val);
458 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
459 struct pinctrl_gpio_range *range,
460 unsigned int offset, bool input)
462 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
463 struct gpio_chip *chip = range->gc;
465 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
466 offset, range->name, offset, input ? "input" : "output");
469 armada_37xx_gpio_direction_input(chip, offset);
471 armada_37xx_gpio_direction_output(chip, offset, 0);
476 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
477 struct pinctrl_gpio_range *range,
480 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
481 struct armada_37xx_pin_group *group;
484 dev_dbg(info->dev, "requesting gpio %d\n", offset);
486 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
487 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
492 static const struct pinmux_ops armada_37xx_pmx_ops = {
493 .get_functions_count = armada_37xx_pmx_get_funcs_count,
494 .get_function_name = armada_37xx_pmx_get_func_name,
495 .get_function_groups = armada_37xx_pmx_get_groups,
496 .set_mux = armada_37xx_pmx_set,
497 .gpio_request_enable = armada_37xx_gpio_request_enable,
498 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
501 static const struct gpio_chip armada_37xx_gpiolib_chip = {
502 .request = gpiochip_generic_request,
503 .free = gpiochip_generic_free,
504 .set = armada_37xx_gpio_set,
505 .get = armada_37xx_gpio_get,
506 .get_direction = armada_37xx_gpio_get_direction,
507 .direction_input = armada_37xx_gpio_direction_input,
508 .direction_output = armada_37xx_gpio_direction_output,
509 .owner = THIS_MODULE,
512 static void armada_37xx_irq_ack(struct irq_data *d)
514 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
515 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
516 u32 reg = IRQ_STATUS;
519 armada_37xx_irq_update_reg(®, d);
520 spin_lock_irqsave(&info->irq_lock, flags);
521 writel(d->mask, info->base + reg);
522 spin_unlock_irqrestore(&info->irq_lock, flags);
525 static void armada_37xx_irq_mask(struct irq_data *d)
527 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
528 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
529 u32 val, reg = IRQ_EN;
532 armada_37xx_irq_update_reg(®, d);
533 spin_lock_irqsave(&info->irq_lock, flags);
534 val = readl(info->base + reg);
535 writel(val & ~d->mask, info->base + reg);
536 spin_unlock_irqrestore(&info->irq_lock, flags);
539 static void armada_37xx_irq_unmask(struct irq_data *d)
541 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
542 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
543 u32 val, reg = IRQ_EN;
546 armada_37xx_irq_update_reg(®, d);
547 spin_lock_irqsave(&info->irq_lock, flags);
548 val = readl(info->base + reg);
549 writel(val | d->mask, info->base + reg);
550 spin_unlock_irqrestore(&info->irq_lock, flags);
553 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
555 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
556 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
557 u32 val, reg = IRQ_WKUP;
560 armada_37xx_irq_update_reg(®, d);
561 spin_lock_irqsave(&info->irq_lock, flags);
562 val = readl(info->base + reg);
564 val |= (BIT(d->hwirq % GPIO_PER_REG));
566 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
567 writel(val, info->base + reg);
568 spin_unlock_irqrestore(&info->irq_lock, flags);
573 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
575 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
576 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
577 u32 val, reg = IRQ_POL;
580 spin_lock_irqsave(&info->irq_lock, flags);
581 armada_37xx_irq_update_reg(®, d);
582 val = readl(info->base + reg);
584 case IRQ_TYPE_EDGE_RISING:
585 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
587 case IRQ_TYPE_EDGE_FALLING:
588 val |= (BIT(d->hwirq % GPIO_PER_REG));
591 spin_unlock_irqrestore(&info->irq_lock, flags);
594 writel(val, info->base + reg);
595 spin_unlock_irqrestore(&info->irq_lock, flags);
601 static void armada_37xx_irq_handler(struct irq_desc *desc)
603 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
604 struct irq_chip *chip = irq_desc_get_chip(desc);
605 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
606 struct irq_domain *d = gc->irqdomain;
609 chained_irq_enter(chip, desc);
610 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
614 spin_lock_irqsave(&info->irq_lock, flags);
615 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
616 /* Manage only the interrupt that was enabled */
617 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
618 spin_unlock_irqrestore(&info->irq_lock, flags);
620 u32 hwirq = ffs(status) - 1;
621 u32 virq = irq_find_mapping(d, hwirq +
624 generic_handle_irq(virq);
626 /* Update status in case a new IRQ appears */
627 spin_lock_irqsave(&info->irq_lock, flags);
628 status = readl_relaxed(info->base +
630 /* Manage only the interrupt that was enabled */
631 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
632 spin_unlock_irqrestore(&info->irq_lock, flags);
635 chained_irq_exit(chip, desc);
638 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
640 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
641 int irq = d->hwirq - chip->irq_base;
643 * The mask field is a "precomputed bitmask for accessing the
644 * chip registers" which was introduced for the generic
645 * irqchip framework. As we don't use this framework, we can
646 * reuse this field for our own usage.
648 d->mask = BIT(irq % GPIO_PER_REG);
650 armada_37xx_irq_unmask(d);
655 static int armada_37xx_irqchip_register(struct platform_device *pdev,
656 struct armada_37xx_pinctrl *info)
658 struct device_node *np = info->dev->of_node;
659 struct gpio_chip *gc = &info->gpio_chip;
660 struct irq_chip *irqchip = &info->irq_chip;
662 int ret = -ENODEV, i, nr_irq_parent;
664 /* Check if we have at least one gpio-controller child node */
665 for_each_child_of_node(info->dev->of_node, np) {
666 if (of_property_read_bool(np, "gpio-controller")) {
674 nr_irq_parent = of_irq_count(np);
675 spin_lock_init(&info->irq_lock);
677 if (!nr_irq_parent) {
678 dev_err(&pdev->dev, "Invalid or no IRQ\n");
682 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
683 dev_err(info->dev, "cannot find IO resource\n");
687 info->base = devm_ioremap_resource(info->dev, &res);
688 if (IS_ERR(info->base))
689 return PTR_ERR(info->base);
691 irqchip->irq_ack = armada_37xx_irq_ack;
692 irqchip->irq_mask = armada_37xx_irq_mask;
693 irqchip->irq_unmask = armada_37xx_irq_unmask;
694 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
695 irqchip->irq_set_type = armada_37xx_irq_set_type;
696 irqchip->irq_startup = armada_37xx_irq_startup;
697 irqchip->name = info->data->name;
698 ret = gpiochip_irqchip_add(gc, irqchip, 0,
699 handle_edge_irq, IRQ_TYPE_NONE);
701 dev_info(&pdev->dev, "could not add irqchip\n");
706 * Many interrupts are connected to the parent interrupt
707 * controller. But we do not take advantage of this and use
708 * the chained irq with all of them.
710 for (i = 0; i < nr_irq_parent; i++) {
711 int irq = irq_of_parse_and_map(np, i);
716 gpiochip_set_chained_irqchip(gc, irqchip, irq,
717 armada_37xx_irq_handler);
723 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
724 struct armada_37xx_pinctrl *info)
726 struct device_node *np;
727 struct gpio_chip *gc;
730 for_each_child_of_node(info->dev->of_node, np) {
731 if (of_find_property(np, "gpio-controller", NULL)) {
739 info->gpio_chip = armada_37xx_gpiolib_chip;
741 gc = &info->gpio_chip;
742 gc->ngpio = info->data->nr_pins;
743 gc->parent = &pdev->dev;
746 gc->label = info->data->name;
748 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
751 ret = armada_37xx_irqchip_register(pdev, info);
759 * armada_37xx_add_function() - Add a new function to the list
760 * @funcs: array of function to add the new one
761 * @funcsize: size of the remaining space for the function
762 * @name: name of the function to add
764 * If it is a new function then create it by adding its name else
765 * increment the number of group associated to this function.
767 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
768 int *funcsize, const char *name)
775 while (funcs->ngroups) {
776 /* function already there */
777 if (strcmp(funcs->name, name) == 0) {
786 /* append new unique function */
795 * armada_37xx_fill_group() - complete the group array
796 * @info: info driver instance
798 * Based on the data available from the armada_37xx_pin_group array
799 * completes the last member of the struct for each function: the list
800 * of the groups associated to this function.
803 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
805 int n, num = 0, funcsize = info->data->nr_pins;
807 for (n = 0; n < info->ngroups; n++) {
808 struct armada_37xx_pin_group *grp = &info->groups[n];
811 grp->pins = devm_kzalloc(info->dev,
812 (grp->npins + grp->extra_npins) *
813 sizeof(*grp->pins), GFP_KERNEL);
817 for (i = 0; i < grp->npins; i++)
818 grp->pins[i] = grp->start_pin + i;
820 for (j = 0; j < grp->extra_npins; j++)
821 grp->pins[i+j] = grp->extra_pin + j;
823 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
825 /* check for unique functions and count groups */
826 ret = armada_37xx_add_function(info->funcs, &funcsize,
828 if (ret == -EOVERFLOW)
830 "More functions than pins(%d)\n",
831 info->data->nr_pins);
844 * armada_37xx_fill_funcs() - complete the funcs array
845 * @info: info driver instance
847 * Based on the data available from the armada_37xx_pin_group array
848 * completes the last two member of the struct for each group:
849 * - the list of the pins included in the group
850 * - the list of pinmux functions that can be selected for this group
853 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
855 struct armada_37xx_pmx_func *funcs = info->funcs;
858 for (n = 0; n < info->nfuncs; n++) {
859 const char *name = funcs[n].name;
863 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
864 sizeof(*(funcs[n].groups)),
866 if (!funcs[n].groups)
869 groups = funcs[n].groups;
871 for (g = 0; g < info->ngroups; g++) {
872 struct armada_37xx_pin_group *gp = &info->groups[g];
875 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
876 if (strcmp(gp->funcs[f], name) == 0) {
886 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
887 struct armada_37xx_pinctrl *info)
889 const struct armada_37xx_pin_data *pin_data = info->data;
890 struct pinctrl_desc *ctrldesc = &info->pctl;
891 struct pinctrl_pin_desc *pindesc, *pdesc;
894 info->groups = pin_data->groups;
895 info->ngroups = pin_data->ngroups;
897 ctrldesc->name = "armada_37xx-pinctrl";
898 ctrldesc->owner = THIS_MODULE;
899 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
900 ctrldesc->pmxops = &armada_37xx_pmx_ops;
901 ctrldesc->confops = &armada_37xx_pinconf_ops;
903 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
904 pin_data->nr_pins, GFP_KERNEL);
908 ctrldesc->pins = pindesc;
909 ctrldesc->npins = pin_data->nr_pins;
912 for (pin = 0; pin < pin_data->nr_pins; pin++) {
914 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
915 pin_data->name, pin);
920 * we allocate functions for number of pins and hope there are
921 * fewer unique functions than pins available
923 info->funcs = devm_kzalloc(&pdev->dev, pin_data->nr_pins *
924 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
929 ret = armada_37xx_fill_group(info);
933 ret = armada_37xx_fill_func(info);
937 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
938 if (IS_ERR(info->pctl_dev)) {
939 dev_err(&pdev->dev, "could not register pinctrl driver\n");
940 return PTR_ERR(info->pctl_dev);
946 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
948 .compatible = "marvell,armada3710-sb-pinctrl",
949 .data = (void *)&armada_37xx_pin_sb,
952 .compatible = "marvell,armada3710-nb-pinctrl",
953 .data = (void *)&armada_37xx_pin_nb,
958 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
960 struct armada_37xx_pinctrl *info;
961 struct device *dev = &pdev->dev;
962 struct device_node *np = dev->of_node;
963 struct regmap *regmap;
966 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
973 regmap = syscon_node_to_regmap(np);
974 if (IS_ERR(regmap)) {
975 dev_err(&pdev->dev, "cannot get regmap\n");
976 return PTR_ERR(regmap);
978 info->regmap = regmap;
980 info->data = of_device_get_match_data(dev);
982 ret = armada_37xx_pinctrl_register(pdev, info);
986 ret = armada_37xx_gpiochip_register(pdev, info);
990 platform_set_drvdata(pdev, info);
995 static struct platform_driver armada_37xx_pinctrl_driver = {
997 .name = "armada-37xx-pinctrl",
998 .of_match_table = armada_37xx_pinctrl_of_match,
1002 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1003 armada_37xx_pinctrl_probe);