2 * Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "../pinctrl-utils.h"
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
37 #define IRQ_STATUS 0x10
41 #define GPIO_PER_REG 32
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
58 struct armada_37xx_pin_group {
60 unsigned int start_pin;
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
70 struct armada_37xx_pin_data {
73 struct armada_37xx_pin_group *groups;
77 struct armada_37xx_pmx_func {
83 struct armada_37xx_pm_state {
95 struct armada_37xx_pinctrl {
96 struct regmap *regmap;
98 const struct armada_37xx_pin_data *data;
100 struct gpio_chip gpio_chip;
101 struct irq_chip irq_chip;
103 struct pinctrl_desc pctl;
104 struct pinctrl_dev *pctl_dev;
105 struct armada_37xx_pin_group *groups;
106 unsigned int ngroups;
107 struct armada_37xx_pmx_func *funcs;
109 struct armada_37xx_pm_state pm;
112 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
115 .start_pin = _start, \
119 .funcs = {_func1, _func2} \
122 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
125 .start_pin = _start, \
129 .funcs = {_func1, "gpio"} \
132 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
135 .start_pin = _start, \
138 .val = {_val1, _val2}, \
139 .funcs = {_func1, "gpio"} \
142 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
145 .start_pin = _start, \
148 .val = {_v1, _v2, _v3}, \
149 .funcs = {_f1, _f2, "gpio"} \
152 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
156 .start_pin = _start, \
160 .extra_pin = _start2, \
161 .extra_npins = _nr2, \
162 .funcs = {_f1, _f2} \
165 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
166 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
167 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
168 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
169 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
171 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
173 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
175 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
177 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
178 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
179 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
180 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
181 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
182 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
183 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
184 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
185 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
186 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
187 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
188 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
189 18, 2, "gpio", "uart"),
192 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
193 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
194 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
195 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
196 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
197 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
198 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
199 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
200 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
201 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
202 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
203 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
204 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
208 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
211 .groups = armada_37xx_nb_groups,
212 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
215 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
218 .groups = armada_37xx_sb_groups,
219 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
222 static inline void armada_37xx_update_reg(unsigned int *reg,
223 unsigned int *offset)
225 /* We never have more than 2 registers */
226 if (*offset >= GPIO_PER_REG) {
227 *offset -= GPIO_PER_REG;
232 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
233 struct armada_37xx_pinctrl *info, int pin, int *grp)
235 while (*grp < info->ngroups) {
236 struct armada_37xx_pin_group *group = &info->groups[*grp];
240 for (j = 0; j < (group->npins + group->extra_npins); j++)
241 if (group->pins[j] == pin)
247 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
248 unsigned int selector, unsigned long *config)
253 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
254 unsigned int selector, unsigned long *configs,
255 unsigned int num_configs)
260 static const struct pinconf_ops armada_37xx_pinconf_ops = {
262 .pin_config_group_get = armada_37xx_pin_config_group_get,
263 .pin_config_group_set = armada_37xx_pin_config_group_set,
266 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
268 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
270 return info->ngroups;
273 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
276 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
278 return info->groups[group].name;
281 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
282 unsigned int selector,
283 const unsigned int **pins,
286 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
288 if (selector >= info->ngroups)
291 *pins = info->groups[selector].pins;
292 *npins = info->groups[selector].npins +
293 info->groups[selector].extra_npins;
298 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
299 .get_groups_count = armada_37xx_get_groups_count,
300 .get_group_name = armada_37xx_get_group_name,
301 .get_group_pins = armada_37xx_get_group_pins,
302 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
303 .dt_free_map = pinctrl_utils_free_map,
307 * Pinmux_ops handling
310 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
312 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
317 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
318 unsigned int selector)
320 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
322 return info->funcs[selector].name;
325 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
326 unsigned int selector,
327 const char * const **groups,
328 unsigned int * const num_groups)
330 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
332 *groups = info->funcs[selector].groups;
333 *num_groups = info->funcs[selector].ngroups;
338 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
340 struct armada_37xx_pin_group *grp)
342 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
343 unsigned int reg = SELECTION;
344 unsigned int mask = grp->reg_mask;
347 dev_dbg(info->dev, "enable function %s group %s\n",
350 func = match_string(grp->funcs, NB_FUNCS, name);
354 val = grp->val[func];
356 regmap_update_bits(info->regmap, reg, mask, val);
361 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
362 unsigned int selector,
366 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
367 struct armada_37xx_pin_group *grp = &info->groups[group];
368 const char *name = info->funcs[selector].name;
370 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
373 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
376 int offset = irqd_to_hwirq(d);
378 armada_37xx_update_reg(reg, &offset);
381 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
384 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
385 unsigned int reg = OUTPUT_EN;
388 armada_37xx_update_reg(®, &offset);
391 return regmap_update_bits(info->regmap, reg, mask, 0);
394 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
397 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
398 unsigned int reg = OUTPUT_EN;
399 unsigned int val, mask;
401 armada_37xx_update_reg(®, &offset);
403 regmap_read(info->regmap, reg, &val);
405 return !(val & mask);
408 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
409 unsigned int offset, int value)
411 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
412 unsigned int reg = OUTPUT_EN;
413 unsigned int mask, val, ret;
415 armada_37xx_update_reg(®, &offset);
418 ret = regmap_update_bits(info->regmap, reg, mask, mask);
424 val = value ? mask : 0;
425 regmap_update_bits(info->regmap, reg, mask, val);
430 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
432 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
433 unsigned int reg = INPUT_VAL;
434 unsigned int val, mask;
436 armada_37xx_update_reg(®, &offset);
439 regmap_read(info->regmap, reg, &val);
441 return (val & mask) != 0;
444 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
447 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
448 unsigned int reg = OUTPUT_VAL;
449 unsigned int mask, val;
451 armada_37xx_update_reg(®, &offset);
453 val = value ? mask : 0;
455 regmap_update_bits(info->regmap, reg, mask, val);
458 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
459 struct pinctrl_gpio_range *range,
460 unsigned int offset, bool input)
462 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
463 struct gpio_chip *chip = range->gc;
465 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
466 offset, range->name, offset, input ? "input" : "output");
469 armada_37xx_gpio_direction_input(chip, offset);
471 armada_37xx_gpio_direction_output(chip, offset, 0);
476 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
477 struct pinctrl_gpio_range *range,
480 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
481 struct armada_37xx_pin_group *group;
484 dev_dbg(info->dev, "requesting gpio %d\n", offset);
486 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
487 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
492 static const struct pinmux_ops armada_37xx_pmx_ops = {
493 .get_functions_count = armada_37xx_pmx_get_funcs_count,
494 .get_function_name = armada_37xx_pmx_get_func_name,
495 .get_function_groups = armada_37xx_pmx_get_groups,
496 .set_mux = armada_37xx_pmx_set,
497 .gpio_request_enable = armada_37xx_gpio_request_enable,
498 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
501 static const struct gpio_chip armada_37xx_gpiolib_chip = {
502 .request = gpiochip_generic_request,
503 .free = gpiochip_generic_free,
504 .set = armada_37xx_gpio_set,
505 .get = armada_37xx_gpio_get,
506 .get_direction = armada_37xx_gpio_get_direction,
507 .direction_input = armada_37xx_gpio_direction_input,
508 .direction_output = armada_37xx_gpio_direction_output,
509 .owner = THIS_MODULE,
512 static void armada_37xx_irq_ack(struct irq_data *d)
514 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
515 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
516 u32 reg = IRQ_STATUS;
519 armada_37xx_irq_update_reg(®, d);
520 spin_lock_irqsave(&info->irq_lock, flags);
521 writel(d->mask, info->base + reg);
522 spin_unlock_irqrestore(&info->irq_lock, flags);
525 static void armada_37xx_irq_mask(struct irq_data *d)
527 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
528 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
529 u32 val, reg = IRQ_EN;
532 armada_37xx_irq_update_reg(®, d);
533 spin_lock_irqsave(&info->irq_lock, flags);
534 val = readl(info->base + reg);
535 writel(val & ~d->mask, info->base + reg);
536 spin_unlock_irqrestore(&info->irq_lock, flags);
539 static void armada_37xx_irq_unmask(struct irq_data *d)
541 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
542 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
543 u32 val, reg = IRQ_EN;
546 armada_37xx_irq_update_reg(®, d);
547 spin_lock_irqsave(&info->irq_lock, flags);
548 val = readl(info->base + reg);
549 writel(val | d->mask, info->base + reg);
550 spin_unlock_irqrestore(&info->irq_lock, flags);
553 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
555 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
556 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
557 u32 val, reg = IRQ_WKUP;
560 armada_37xx_irq_update_reg(®, d);
561 spin_lock_irqsave(&info->irq_lock, flags);
562 val = readl(info->base + reg);
564 val |= (BIT(d->hwirq % GPIO_PER_REG));
566 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
567 writel(val, info->base + reg);
568 spin_unlock_irqrestore(&info->irq_lock, flags);
573 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
575 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
576 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
577 u32 val, reg = IRQ_POL;
580 spin_lock_irqsave(&info->irq_lock, flags);
581 armada_37xx_irq_update_reg(®, d);
582 val = readl(info->base + reg);
584 case IRQ_TYPE_EDGE_RISING:
585 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
587 case IRQ_TYPE_EDGE_FALLING:
588 val |= (BIT(d->hwirq % GPIO_PER_REG));
590 case IRQ_TYPE_EDGE_BOTH: {
591 u32 in_val, in_reg = INPUT_VAL;
593 armada_37xx_irq_update_reg(&in_reg, d);
594 regmap_read(info->regmap, in_reg, &in_val);
596 /* Set initial polarity based on current input level. */
597 if (in_val & BIT(d->hwirq % GPIO_PER_REG))
598 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
600 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
604 spin_unlock_irqrestore(&info->irq_lock, flags);
607 writel(val, info->base + reg);
608 spin_unlock_irqrestore(&info->irq_lock, flags);
613 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
616 u32 reg_idx = pin_idx / GPIO_PER_REG;
617 u32 bit_num = pin_idx % GPIO_PER_REG;
621 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
623 spin_lock_irqsave(&info->irq_lock, flags);
624 p = readl(info->base + IRQ_POL + 4 * reg_idx);
625 if ((p ^ l) & (1 << bit_num)) {
627 * For the gpios which are used for both-edge irqs, when their
628 * interrupts happen, their input levels are changed,
629 * yet their interrupt polarities are kept in old values, we
630 * should synchronize their interrupt polarities; for example,
631 * at first a gpio's input level is low and its interrupt
632 * polarity control is "Detect rising edge", then the gpio has
633 * a interrupt , its level turns to high, we should change its
634 * polarity control to "Detect falling edge" correspondingly.
637 writel(p, info->base + IRQ_POL + 4 * reg_idx);
644 spin_unlock_irqrestore(&info->irq_lock, flags);
648 static void armada_37xx_irq_handler(struct irq_desc *desc)
650 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
651 struct irq_chip *chip = irq_desc_get_chip(desc);
652 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
653 struct irq_domain *d = gc->irq.domain;
656 chained_irq_enter(chip, desc);
657 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
661 spin_lock_irqsave(&info->irq_lock, flags);
662 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
663 /* Manage only the interrupt that was enabled */
664 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
665 spin_unlock_irqrestore(&info->irq_lock, flags);
667 u32 hwirq = ffs(status) - 1;
668 u32 virq = irq_find_mapping(d, hwirq +
670 u32 t = irq_get_trigger_type(virq);
672 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
673 /* Swap polarity (race with GPIO line) */
674 if (armada_37xx_edge_both_irq_swap_pol(info,
675 hwirq + i * GPIO_PER_REG)) {
677 * For spurious irq, which gpio level
678 * is not as expected after incoming
679 * edge, just ack the gpio irq.
688 generic_handle_irq(virq);
691 /* Update status in case a new IRQ appears */
692 spin_lock_irqsave(&info->irq_lock, flags);
693 status = readl_relaxed(info->base +
695 /* Manage only the interrupt that was enabled */
696 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
697 spin_unlock_irqrestore(&info->irq_lock, flags);
700 chained_irq_exit(chip, desc);
703 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
706 * The mask field is a "precomputed bitmask for accessing the
707 * chip registers" which was introduced for the generic
708 * irqchip framework. As we don't use this framework, we can
709 * reuse this field for our own usage.
711 d->mask = BIT(d->hwirq % GPIO_PER_REG);
713 armada_37xx_irq_unmask(d);
718 static int armada_37xx_irqchip_register(struct platform_device *pdev,
719 struct armada_37xx_pinctrl *info)
721 struct device_node *np = info->dev->of_node;
722 struct gpio_chip *gc = &info->gpio_chip;
723 struct irq_chip *irqchip = &info->irq_chip;
725 int ret = -ENODEV, i, nr_irq_parent;
727 /* Check if we have at least one gpio-controller child node */
728 for_each_child_of_node(info->dev->of_node, np) {
729 if (of_property_read_bool(np, "gpio-controller")) {
737 nr_irq_parent = of_irq_count(np);
738 spin_lock_init(&info->irq_lock);
740 if (!nr_irq_parent) {
741 dev_err(&pdev->dev, "Invalid or no IRQ\n");
745 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
746 dev_err(info->dev, "cannot find IO resource\n");
750 info->base = devm_ioremap_resource(info->dev, &res);
751 if (IS_ERR(info->base))
752 return PTR_ERR(info->base);
754 irqchip->irq_ack = armada_37xx_irq_ack;
755 irqchip->irq_mask = armada_37xx_irq_mask;
756 irqchip->irq_unmask = armada_37xx_irq_unmask;
757 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
758 irqchip->irq_set_type = armada_37xx_irq_set_type;
759 irqchip->irq_startup = armada_37xx_irq_startup;
760 irqchip->name = info->data->name;
761 ret = gpiochip_irqchip_add(gc, irqchip, 0,
762 handle_edge_irq, IRQ_TYPE_NONE);
764 dev_info(&pdev->dev, "could not add irqchip\n");
769 * Many interrupts are connected to the parent interrupt
770 * controller. But we do not take advantage of this and use
771 * the chained irq with all of them.
773 for (i = 0; i < nr_irq_parent; i++) {
774 int irq = irq_of_parse_and_map(np, i);
779 gpiochip_set_chained_irqchip(gc, irqchip, irq,
780 armada_37xx_irq_handler);
786 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
787 struct armada_37xx_pinctrl *info)
789 struct device_node *np;
790 struct gpio_chip *gc;
793 for_each_child_of_node(info->dev->of_node, np) {
794 if (of_find_property(np, "gpio-controller", NULL)) {
802 info->gpio_chip = armada_37xx_gpiolib_chip;
804 gc = &info->gpio_chip;
805 gc->ngpio = info->data->nr_pins;
806 gc->parent = &pdev->dev;
809 gc->label = info->data->name;
811 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
814 ret = armada_37xx_irqchip_register(pdev, info);
822 * armada_37xx_add_function() - Add a new function to the list
823 * @funcs: array of function to add the new one
824 * @funcsize: size of the remaining space for the function
825 * @name: name of the function to add
827 * If it is a new function then create it by adding its name else
828 * increment the number of group associated to this function.
830 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
831 int *funcsize, const char *name)
838 while (funcs->ngroups) {
839 /* function already there */
840 if (strcmp(funcs->name, name) == 0) {
849 /* append new unique function */
858 * armada_37xx_fill_group() - complete the group array
859 * @info: info driver instance
861 * Based on the data available from the armada_37xx_pin_group array
862 * completes the last member of the struct for each function: the list
863 * of the groups associated to this function.
866 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
868 int n, num = 0, funcsize = info->data->nr_pins;
870 for (n = 0; n < info->ngroups; n++) {
871 struct armada_37xx_pin_group *grp = &info->groups[n];
874 grp->pins = devm_kcalloc(info->dev,
875 grp->npins + grp->extra_npins,
881 for (i = 0; i < grp->npins; i++)
882 grp->pins[i] = grp->start_pin + i;
884 for (j = 0; j < grp->extra_npins; j++)
885 grp->pins[i+j] = grp->extra_pin + j;
887 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
889 /* check for unique functions and count groups */
890 ret = armada_37xx_add_function(info->funcs, &funcsize,
892 if (ret == -EOVERFLOW)
894 "More functions than pins(%d)\n",
895 info->data->nr_pins);
908 * armada_37xx_fill_funcs() - complete the funcs array
909 * @info: info driver instance
911 * Based on the data available from the armada_37xx_pin_group array
912 * completes the last two member of the struct for each group:
913 * - the list of the pins included in the group
914 * - the list of pinmux functions that can be selected for this group
917 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
919 struct armada_37xx_pmx_func *funcs = info->funcs;
922 for (n = 0; n < info->nfuncs; n++) {
923 const char *name = funcs[n].name;
927 funcs[n].groups = devm_kcalloc(info->dev,
929 sizeof(*(funcs[n].groups)),
931 if (!funcs[n].groups)
934 groups = funcs[n].groups;
936 for (g = 0; g < info->ngroups; g++) {
937 struct armada_37xx_pin_group *gp = &info->groups[g];
940 f = match_string(gp->funcs, NB_FUNCS, name);
951 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
952 struct armada_37xx_pinctrl *info)
954 const struct armada_37xx_pin_data *pin_data = info->data;
955 struct pinctrl_desc *ctrldesc = &info->pctl;
956 struct pinctrl_pin_desc *pindesc, *pdesc;
959 info->groups = pin_data->groups;
960 info->ngroups = pin_data->ngroups;
962 ctrldesc->name = "armada_37xx-pinctrl";
963 ctrldesc->owner = THIS_MODULE;
964 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
965 ctrldesc->pmxops = &armada_37xx_pmx_ops;
966 ctrldesc->confops = &armada_37xx_pinconf_ops;
968 pindesc = devm_kcalloc(&pdev->dev,
969 pin_data->nr_pins, sizeof(*pindesc),
974 ctrldesc->pins = pindesc;
975 ctrldesc->npins = pin_data->nr_pins;
978 for (pin = 0; pin < pin_data->nr_pins; pin++) {
980 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
981 pin_data->name, pin);
986 * we allocate functions for number of pins and hope there are
987 * fewer unique functions than pins available
989 info->funcs = devm_kcalloc(&pdev->dev,
991 sizeof(struct armada_37xx_pmx_func),
997 ret = armada_37xx_fill_group(info);
1001 ret = armada_37xx_fill_func(info);
1005 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1006 if (IS_ERR(info->pctl_dev)) {
1007 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1008 return PTR_ERR(info->pctl_dev);
1014 #if defined(CONFIG_PM)
1015 static int armada_3700_pinctrl_suspend(struct device *dev)
1017 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1019 /* Save GPIO state */
1020 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1021 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1022 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1023 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1024 &info->pm.out_val_h);
1026 info->pm.irq_en_l = readl(info->base + IRQ_EN);
1027 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1028 info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1029 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1031 /* Save pinctrl state */
1032 regmap_read(info->regmap, SELECTION, &info->pm.selection);
1037 static int armada_3700_pinctrl_resume(struct device *dev)
1039 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1040 struct gpio_chip *gc;
1041 struct irq_domain *d;
1044 /* Restore GPIO state */
1045 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1046 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1048 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1049 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1050 info->pm.out_val_h);
1053 * Input levels may change during suspend, which is not monitored at
1054 * that time. GPIOs used for both-edge IRQs may not be synchronized
1055 * anymore with their polarities (rising/falling edge) and must be
1056 * re-configured manually.
1058 gc = &info->gpio_chip;
1060 for (i = 0; i < gc->ngpio; i++) {
1061 u32 irq_bit = BIT(i % GPIO_PER_REG);
1062 u32 mask, *irq_pol, input_reg, virq, type, level;
1064 if (i < GPIO_PER_REG) {
1065 mask = info->pm.irq_en_l;
1066 irq_pol = &info->pm.irq_pol_l;
1067 input_reg = INPUT_VAL;
1069 mask = info->pm.irq_en_h;
1070 irq_pol = &info->pm.irq_pol_h;
1071 input_reg = INPUT_VAL + sizeof(u32);
1074 if (!(mask & irq_bit))
1077 virq = irq_find_mapping(d, i);
1078 type = irq_get_trigger_type(virq);
1081 * Synchronize level and polarity for both-edge irqs:
1082 * - a high input level expects a falling edge,
1083 * - a low input level exepects a rising edge.
1085 if ((type & IRQ_TYPE_SENSE_MASK) ==
1086 IRQ_TYPE_EDGE_BOTH) {
1087 regmap_read(info->regmap, input_reg, &level);
1088 if ((*irq_pol ^ level) & irq_bit)
1089 *irq_pol ^= irq_bit;
1093 writel(info->pm.irq_en_l, info->base + IRQ_EN);
1094 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1095 writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1096 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1098 /* Restore pinctrl state */
1099 regmap_write(info->regmap, SELECTION, info->pm.selection);
1105 * Since pinctrl is an infrastructure module, its resume should be issued prior
1106 * to other IO drivers.
1108 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1109 .suspend_late = armada_3700_pinctrl_suspend,
1110 .resume_early = armada_3700_pinctrl_resume,
1113 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1115 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1116 #endif /* CONFIG_PM */
1118 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1120 .compatible = "marvell,armada3710-sb-pinctrl",
1121 .data = &armada_37xx_pin_sb,
1124 .compatible = "marvell,armada3710-nb-pinctrl",
1125 .data = &armada_37xx_pin_nb,
1130 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1132 struct armada_37xx_pinctrl *info;
1133 struct device *dev = &pdev->dev;
1134 struct device_node *np = dev->of_node;
1135 struct regmap *regmap;
1138 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1145 regmap = syscon_node_to_regmap(np);
1146 if (IS_ERR(regmap)) {
1147 dev_err(&pdev->dev, "cannot get regmap\n");
1148 return PTR_ERR(regmap);
1150 info->regmap = regmap;
1152 info->data = of_device_get_match_data(dev);
1154 ret = armada_37xx_pinctrl_register(pdev, info);
1158 ret = armada_37xx_gpiochip_register(pdev, info);
1162 platform_set_drvdata(pdev, info);
1167 static struct platform_driver armada_37xx_pinctrl_driver = {
1169 .name = "armada-37xx-pinctrl",
1170 .of_match_table = armada_37xx_pinctrl_of_match,
1171 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1175 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1176 armada_37xx_pinctrl_probe);