2 * Pin controller and GPIO driver for Amlogic Meson SoCs
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
18 * variable number of pins.
20 * The AO bank is special because it belongs to the Always-On power
21 * domain which can't be powered off; the bank also uses a set of
22 * registers different from the other banks.
24 * For each pin controller there are 4 different register ranges that
25 * control the following properties of the pins:
27 * 2) pull enable/disable
29 * 4) GPIO direction, output value, input value
31 * In some cases the register ranges for pull enable and pull
32 * direction are the same and thus there are only 3 register ranges.
34 * Every pinmux group can be enabled by a specific bit in the first
35 * register range; when all groups for a given pin are disabled the
38 * For the pull and GPIO configuration every bank uses a contiguous
39 * set of bits in the register sets described above; the same register
40 * can be shared by more banks with different offsets.
42 * In addition to this there are some registers shared between all
43 * banks that control the IRQ functionality. This feature is not
44 * supported at the moment by the driver.
47 #include <linux/device.h>
48 #include <linux/gpio.h>
49 #include <linux/init.h>
52 #include <linux/of_address.h>
53 #include <linux/pinctrl/pinconf-generic.h>
54 #include <linux/pinctrl/pinconf.h>
55 #include <linux/pinctrl/pinctrl.h>
56 #include <linux/pinctrl/pinmux.h>
57 #include <linux/platform_device.h>
58 #include <linux/regmap.h>
59 #include <linux/seq_file.h>
62 #include "../pinctrl-utils.h"
63 #include "pinctrl-meson.h"
66 * meson_get_bank() - find the bank containing a given pin
68 * @pc: the pinctrl instance
69 * @pin: the pin number
70 * @bank: the found bank
72 * Return: 0 on success, a negative value on error
74 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
75 struct meson_bank **bank)
79 for (i = 0; i < pc->data->num_banks; i++) {
80 if (pin >= pc->data->banks[i].first &&
81 pin <= pc->data->banks[i].last) {
82 *bank = &pc->data->banks[i];
91 * meson_calc_reg_and_bit() - calculate register and bit for a pin
93 * @bank: the bank containing the pin
94 * @pin: the pin number
95 * @reg_type: the type of register needed (pull-enable, pull, etc...)
96 * @reg: the computed register offset
97 * @bit: the computed bit
99 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
100 enum meson_reg_type reg_type,
101 unsigned int *reg, unsigned int *bit)
103 struct meson_reg_desc *desc = &bank->regs[reg_type];
105 *reg = desc->reg * 4;
106 *bit = desc->bit + pin - bank->first;
109 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
111 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
113 return pc->data->num_groups;
116 static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
119 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
121 return pc->data->groups[selector].name;
124 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
125 const unsigned **pins, unsigned *num_pins)
127 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
129 *pins = pc->data->groups[selector].pins;
130 *num_pins = pc->data->groups[selector].num_pins;
135 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
138 seq_printf(s, " %s", dev_name(pcdev->dev));
141 static const struct pinctrl_ops meson_pctrl_ops = {
142 .get_groups_count = meson_get_groups_count,
143 .get_group_name = meson_get_group_name,
144 .get_group_pins = meson_get_group_pins,
145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
146 .dt_free_map = pinctrl_utils_free_map,
147 .pin_dbg_show = meson_pin_dbg_show,
151 * meson_pmx_disable_other_groups() - disable other groups using a given pin
153 * @pc: meson pin controller device
154 * @pin: number of the pin
155 * @sel_group: index of the selected group, or -1 if none
157 * The function disables all pinmux groups using a pin except the
158 * selected one. If @sel_group is -1 all groups are disabled, leaving
159 * the pin in GPIO mode.
161 static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
162 unsigned int pin, int sel_group)
164 struct meson_pmx_group *group;
167 for (i = 0; i < pc->data->num_groups; i++) {
168 group = &pc->data->groups[i];
169 if (group->is_gpio || i == sel_group)
172 for (j = 0; j < group->num_pins; j++) {
173 if (group->pins[j] == pin) {
174 /* We have found a group using the pin */
175 regmap_update_bits(pc->reg_mux,
183 static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
186 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
187 struct meson_pmx_func *func = &pc->data->funcs[func_num];
188 struct meson_pmx_group *group = &pc->data->groups[group_num];
191 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
195 * Disable groups using the same pin.
196 * The selected group is not disabled to avoid glitches.
198 for (i = 0; i < group->num_pins; i++)
199 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
201 /* Function 0 (GPIO) doesn't need any additional setting */
203 ret = regmap_update_bits(pc->reg_mux, group->reg * 4,
204 BIT(group->bit), BIT(group->bit));
209 static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
210 struct pinctrl_gpio_range *range,
213 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
215 meson_pmx_disable_other_groups(pc, offset, -1);
220 static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
222 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
224 return pc->data->num_funcs;
227 static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
230 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
232 return pc->data->funcs[selector].name;
235 static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
236 const char * const **groups,
237 unsigned * const num_groups)
239 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
241 *groups = pc->data->funcs[selector].groups;
242 *num_groups = pc->data->funcs[selector].num_groups;
247 static const struct pinmux_ops meson_pmx_ops = {
248 .set_mux = meson_pmx_set_mux,
249 .get_functions_count = meson_pmx_get_funcs_count,
250 .get_function_name = meson_pmx_get_func_name,
251 .get_function_groups = meson_pmx_get_groups,
252 .gpio_request_enable = meson_pmx_request_gpio,
255 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
256 unsigned long *configs, unsigned num_configs)
258 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
259 struct meson_bank *bank;
260 enum pin_config_param param;
261 unsigned int reg, bit;
264 ret = meson_get_bank(pc, pin, &bank);
268 for (i = 0; i < num_configs; i++) {
269 param = pinconf_to_config_param(configs[i]);
272 case PIN_CONFIG_BIAS_DISABLE:
273 dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
275 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®,
277 ret = regmap_update_bits(pc->reg_pullen, reg,
282 case PIN_CONFIG_BIAS_PULL_UP:
283 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
285 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
287 ret = regmap_update_bits(pc->reg_pullen, reg,
292 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
293 ret = regmap_update_bits(pc->reg_pull, reg,
298 case PIN_CONFIG_BIAS_PULL_DOWN:
299 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
301 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
303 ret = regmap_update_bits(pc->reg_pullen, reg,
308 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
309 ret = regmap_update_bits(pc->reg_pull, reg,
322 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
324 struct meson_bank *bank;
325 unsigned int reg, bit, val;
328 ret = meson_get_bank(pc, pin, &bank);
332 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit);
334 ret = regmap_read(pc->reg_pullen, reg, &val);
338 if (!(val & BIT(bit))) {
339 conf = PIN_CONFIG_BIAS_DISABLE;
341 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
343 ret = regmap_read(pc->reg_pull, reg, &val);
348 conf = PIN_CONFIG_BIAS_PULL_UP;
350 conf = PIN_CONFIG_BIAS_PULL_DOWN;
356 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
357 unsigned long *config)
359 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
360 enum pin_config_param param = pinconf_to_config_param(*config);
364 case PIN_CONFIG_BIAS_DISABLE:
365 case PIN_CONFIG_BIAS_PULL_DOWN:
366 case PIN_CONFIG_BIAS_PULL_UP:
367 if (meson_pinconf_get_pull(pc, pin) == param)
376 *config = pinconf_to_config_packed(param, arg);
377 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
382 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
383 unsigned int num_group,
384 unsigned long *configs, unsigned num_configs)
386 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
387 struct meson_pmx_group *group = &pc->data->groups[num_group];
390 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
392 for (i = 0; i < group->num_pins; i++) {
393 meson_pinconf_set(pcdev, group->pins[i], configs,
400 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
401 unsigned int group, unsigned long *config)
406 static const struct pinconf_ops meson_pinconf_ops = {
407 .pin_config_get = meson_pinconf_get,
408 .pin_config_set = meson_pinconf_set,
409 .pin_config_group_get = meson_pinconf_group_get,
410 .pin_config_group_set = meson_pinconf_group_set,
414 static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
416 return pinctrl_request_gpio(chip->base + gpio);
419 static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
421 struct meson_pinctrl *pc = gpiochip_get_data(chip);
423 pinctrl_free_gpio(pc->data->pin_base + gpio);
426 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
428 struct meson_pinctrl *pc = gpiochip_get_data(chip);
429 unsigned int reg, bit, pin;
430 struct meson_bank *bank;
433 pin = pc->data->pin_base + gpio;
434 ret = meson_get_bank(pc, pin, &bank);
438 meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
440 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit));
443 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
446 struct meson_pinctrl *pc = gpiochip_get_data(chip);
447 unsigned int reg, bit, pin;
448 struct meson_bank *bank;
451 pin = pc->data->pin_base + gpio;
452 ret = meson_get_bank(pc, pin, &bank);
456 meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
457 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0);
461 meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
462 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
463 value ? BIT(bit) : 0);
466 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
468 struct meson_pinctrl *pc = gpiochip_get_data(chip);
469 unsigned int reg, bit, pin;
470 struct meson_bank *bank;
473 pin = pc->data->pin_base + gpio;
474 ret = meson_get_bank(pc, pin, &bank);
478 meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
479 regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
480 value ? BIT(bit) : 0);
483 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
485 struct meson_pinctrl *pc = gpiochip_get_data(chip);
486 unsigned int reg, bit, val, pin;
487 struct meson_bank *bank;
490 pin = pc->data->pin_base + gpio;
491 ret = meson_get_bank(pc, pin, &bank);
495 meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit);
496 regmap_read(pc->reg_gpio, reg, &val);
498 return !!(val & BIT(bit));
501 static const struct of_device_id meson_pinctrl_dt_match[] = {
503 .compatible = "amlogic,meson8-cbus-pinctrl",
504 .data = &meson8_cbus_pinctrl_data,
507 .compatible = "amlogic,meson8b-cbus-pinctrl",
508 .data = &meson8b_cbus_pinctrl_data,
511 .compatible = "amlogic,meson8-aobus-pinctrl",
512 .data = &meson8_aobus_pinctrl_data,
515 .compatible = "amlogic,meson8b-aobus-pinctrl",
516 .data = &meson8b_aobus_pinctrl_data,
519 .compatible = "amlogic,meson-gxbb-periphs-pinctrl",
520 .data = &meson_gxbb_periphs_pinctrl_data,
523 .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
524 .data = &meson_gxbb_aobus_pinctrl_data,
527 .compatible = "amlogic,meson-gxl-periphs-pinctrl",
528 .data = &meson_gxl_periphs_pinctrl_data,
531 .compatible = "amlogic,meson-gxl-aobus-pinctrl",
532 .data = &meson_gxl_aobus_pinctrl_data,
537 static int meson_gpiolib_register(struct meson_pinctrl *pc)
541 pc->chip.label = pc->data->name;
542 pc->chip.parent = pc->dev;
543 pc->chip.request = meson_gpio_request;
544 pc->chip.free = meson_gpio_free;
545 pc->chip.direction_input = meson_gpio_direction_input;
546 pc->chip.direction_output = meson_gpio_direction_output;
547 pc->chip.get = meson_gpio_get;
548 pc->chip.set = meson_gpio_set;
549 pc->chip.base = pc->data->pin_base;
550 pc->chip.ngpio = pc->data->num_pins;
551 pc->chip.can_sleep = false;
552 pc->chip.of_node = pc->of_node;
553 pc->chip.of_gpio_n_cells = 2;
555 ret = gpiochip_add_data(&pc->chip, pc);
557 dev_err(pc->dev, "can't add gpio chip %s\n",
565 static struct regmap_config meson_regmap_config = {
571 static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
572 struct device_node *node, char *name)
578 i = of_property_match_string(node, "reg-names", name);
579 if (of_address_to_resource(node, i, &res))
580 return ERR_PTR(-ENOENT);
582 base = devm_ioremap_resource(pc->dev, &res);
584 return ERR_CAST(base);
586 meson_regmap_config.max_register = resource_size(&res) - 4;
587 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
590 if (!meson_regmap_config.name)
591 return ERR_PTR(-ENOMEM);
593 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
596 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
597 struct device_node *node)
599 struct device_node *np, *gpio_np = NULL;
601 for_each_child_of_node(node, np) {
602 if (!of_find_property(np, "gpio-controller", NULL))
605 dev_err(pc->dev, "multiple gpio nodes\n");
612 dev_err(pc->dev, "no gpio node found\n");
616 pc->of_node = gpio_np;
618 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
619 if (IS_ERR(pc->reg_mux)) {
620 dev_err(pc->dev, "mux registers not found\n");
621 return PTR_ERR(pc->reg_mux);
624 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
625 if (IS_ERR(pc->reg_pull)) {
626 dev_err(pc->dev, "pull registers not found\n");
627 return PTR_ERR(pc->reg_pull);
630 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
631 /* Use pull region if pull-enable one is not present */
632 if (IS_ERR(pc->reg_pullen))
633 pc->reg_pullen = pc->reg_pull;
635 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
636 if (IS_ERR(pc->reg_gpio)) {
637 dev_err(pc->dev, "gpio registers not found\n");
638 return PTR_ERR(pc->reg_gpio);
644 static int meson_pinctrl_probe(struct platform_device *pdev)
646 const struct of_device_id *match;
647 struct device *dev = &pdev->dev;
648 struct meson_pinctrl *pc;
651 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
656 match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
657 pc->data = (struct meson_pinctrl_data *) match->data;
659 ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
663 pc->desc.name = "pinctrl-meson";
664 pc->desc.owner = THIS_MODULE;
665 pc->desc.pctlops = &meson_pctrl_ops;
666 pc->desc.pmxops = &meson_pmx_ops;
667 pc->desc.confops = &meson_pinconf_ops;
668 pc->desc.pins = pc->data->pins;
669 pc->desc.npins = pc->data->num_pins;
671 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
672 if (IS_ERR(pc->pcdev)) {
673 dev_err(pc->dev, "can't register pinctrl device");
674 return PTR_ERR(pc->pcdev);
677 return meson_gpiolib_register(pc);
680 static struct platform_driver meson_pinctrl_driver = {
681 .probe = meson_pinctrl_probe,
683 .name = "meson-pinctrl",
684 .of_match_table = meson_pinctrl_dt_match,
687 builtin_platform_driver(meson_pinctrl_driver);