1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
4 * bindings for MediaTek SoC.
6 * Copyright (C) 2018 MediaTek Inc.
7 * Author: Sean Wang <sean.wang@mediatek.com>
8 * Zhiyong Tao <zhiyong.tao@mediatek.com>
9 * Hongzhou.Yang <hongzhou.yang@mediatek.com>
12 #include <linux/gpio/driver.h>
13 #include <linux/module.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
15 #include "pinctrl-paris.h"
17 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
19 /* Custom pinconf parameters */
20 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
21 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
22 #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
23 #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
24 #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
26 static const struct pinconf_generic_params mtk_custom_bindings[] = {
27 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
28 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
29 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
30 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
31 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
34 #ifdef CONFIG_DEBUG_FS
35 static const struct pin_config_item mtk_conf_items[] = {
36 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
37 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
38 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
39 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
40 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
44 static const char * const mtk_gpio_functions[] = {
45 "func0", "func1", "func2", "func3",
46 "func4", "func5", "func6", "func7",
47 "func8", "func9", "func10", "func11",
48 "func12", "func13", "func14", "func15",
52 * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
53 * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
55 * The custom value encodes three hardware bits as follows:
58 * | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA)
59 * ------------------------------------------------
60 * | x | x | 0 | disabled, use standard drive strength
61 * -------------------------------------
62 * | 0 | 0 | 1 | 125 uA
63 * | 0 | 1 | 1 | 250 uA
64 * | 1 | 0 | 1 | 500 uA
65 * | 1 | 1 | 1 | 1000 uA
67 static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
69 static int mtk_drv_adv_to_uA(int val)
71 /* This should never happen. */
72 if (WARN_ON_ONCE(val < 0 || val > 7))
75 /* Bit 0 simply enables this hardware part */
79 return mtk_drv_adv_uA[(val >> 1)];
82 static int mtk_drv_uA_to_adv(int val)
98 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
99 struct pinctrl_gpio_range *range,
102 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
103 const struct mtk_pin_desc *desc;
105 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
107 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
111 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
112 struct pinctrl_gpio_range *range,
113 unsigned int pin, bool input)
115 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
116 const struct mtk_pin_desc *desc;
118 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
120 /* hardware would take 0 as input direction */
121 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
124 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
125 unsigned int pin, unsigned long *config)
127 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
128 u32 param = pinconf_to_config_param(*config);
129 int pullup, reg, err = -ENOTSUPP, ret = 1;
130 const struct mtk_pin_desc *desc;
132 if (pin >= hw->soc->npins)
135 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
138 case PIN_CONFIG_BIAS_DISABLE:
139 case PIN_CONFIG_BIAS_PULL_UP:
140 case PIN_CONFIG_BIAS_PULL_DOWN:
141 if (!hw->soc->bias_get_combo)
143 err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
146 if (ret == MTK_PUPD_SET_R1R0_00)
148 if (param == PIN_CONFIG_BIAS_DISABLE) {
149 if (ret != MTK_DISABLE)
151 } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
152 if (!pullup || ret == MTK_DISABLE)
154 } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
155 if (pullup || ret == MTK_DISABLE)
159 case PIN_CONFIG_SLEW_RATE:
160 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
162 case PIN_CONFIG_INPUT_ENABLE:
163 case PIN_CONFIG_OUTPUT_ENABLE:
164 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
167 /* CONFIG Current direction return value
168 * ------------- ----------------- ----------------------
169 * OUTPUT_ENABLE output 1 (= HW value)
170 * input 0 (= HW value)
171 * INPUT_ENABLE output 0 (= reverse HW value)
172 * input 1 (= reverse HW value)
174 if (param == PIN_CONFIG_INPUT_ENABLE)
178 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
179 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
182 /* return error when in output mode
183 * because schmitt trigger only work in input mode
190 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
192 case PIN_CONFIG_DRIVE_STRENGTH:
193 if (!hw->soc->drive_get)
196 if (hw->soc->adv_drive_get) {
197 err = hw->soc->adv_drive_get(hw, desc, &ret);
199 err = mtk_drv_adv_to_uA(ret);
201 /* PIN_CONFIG_DRIVE_STRENGTH_UA used */
208 err = hw->soc->drive_get(hw, desc, &ret);
210 case PIN_CONFIG_DRIVE_STRENGTH_UA:
211 if (!hw->soc->adv_drive_get)
214 err = hw->soc->adv_drive_get(hw, desc, &ret);
217 err = mtk_drv_adv_to_uA(ret);
224 case MTK_PIN_CONFIG_TDSEL:
225 case MTK_PIN_CONFIG_RDSEL:
226 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
227 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
228 err = mtk_hw_get_value(hw, desc, reg, &ret);
230 case MTK_PIN_CONFIG_PU_ADV:
231 case MTK_PIN_CONFIG_PD_ADV:
232 if (!hw->soc->adv_pull_get)
234 pullup = param == MTK_PIN_CONFIG_PU_ADV;
235 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
237 case MTK_PIN_CONFIG_DRV_ADV:
238 if (!hw->soc->adv_drive_get)
240 err = hw->soc->adv_drive_get(hw, desc, &ret);
245 *config = pinconf_to_config_packed(param, ret);
250 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
251 enum pin_config_param param, u32 arg)
253 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
254 const struct mtk_pin_desc *desc;
258 if (pin >= hw->soc->npins)
261 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
263 switch ((u32)param) {
264 case PIN_CONFIG_BIAS_DISABLE:
265 if (!hw->soc->bias_set_combo)
267 err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
269 case PIN_CONFIG_BIAS_PULL_UP:
270 if (!hw->soc->bias_set_combo)
272 err = hw->soc->bias_set_combo(hw, desc, 1, arg);
274 case PIN_CONFIG_BIAS_PULL_DOWN:
275 if (!hw->soc->bias_set_combo)
277 err = hw->soc->bias_set_combo(hw, desc, 0, arg);
279 case PIN_CONFIG_OUTPUT_ENABLE:
280 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
282 /* Keep set direction to consider the case that a GPIO pin
283 * does not have SMT control
285 if (err != -ENOTSUPP)
288 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
291 case PIN_CONFIG_INPUT_ENABLE:
292 /* regard all non-zero value as enable */
293 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
297 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
300 case PIN_CONFIG_SLEW_RATE:
301 /* regard all non-zero value as enable */
302 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
304 case PIN_CONFIG_OUTPUT:
305 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
310 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
313 case PIN_CONFIG_INPUT_SCHMITT:
314 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
315 /* arg = 1: Input mode & SMT enable ;
316 * arg = 0: Output mode & SMT disable
318 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
322 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
324 case PIN_CONFIG_DRIVE_STRENGTH:
325 if (!hw->soc->drive_set)
327 err = hw->soc->drive_set(hw, desc, arg);
329 case PIN_CONFIG_DRIVE_STRENGTH_UA:
330 if (!hw->soc->adv_drive_set)
333 err = mtk_drv_uA_to_adv(arg);
336 err = hw->soc->adv_drive_set(hw, desc, err);
338 case MTK_PIN_CONFIG_TDSEL:
339 case MTK_PIN_CONFIG_RDSEL:
340 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
341 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
342 err = mtk_hw_set_value(hw, desc, reg, arg);
344 case MTK_PIN_CONFIG_PU_ADV:
345 case MTK_PIN_CONFIG_PD_ADV:
346 if (!hw->soc->adv_pull_set)
348 err = hw->soc->adv_pull_set(hw, desc,
349 (param == MTK_PIN_CONFIG_PU_ADV),
352 case MTK_PIN_CONFIG_DRV_ADV:
353 if (!hw->soc->adv_drive_set)
355 err = hw->soc->adv_drive_set(hw, desc, arg);
362 static struct mtk_pinctrl_group *
363 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
367 for (i = 0; i < hw->soc->ngrps; i++) {
368 struct mtk_pinctrl_group *grp = hw->groups + i;
377 static const struct mtk_func_desc *
378 mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
380 const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
381 const struct mtk_func_desc *func = pin->funcs;
383 while (func && func->name) {
384 if (func->muxval == fnum)
392 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
397 for (i = 0; i < hw->soc->npins; i++) {
398 const struct mtk_pin_desc *pin = hw->soc->pins + i;
400 if (pin->number == pin_num) {
401 const struct mtk_func_desc *func = pin->funcs;
403 while (func && func->name) {
404 if (func->muxval == fnum)
416 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
418 struct mtk_pinctrl_group *grp,
419 struct pinctrl_map **map,
420 unsigned *reserved_maps,
425 if (*num_maps == *reserved_maps)
428 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
429 (*map)[*num_maps].data.mux.group = grp->name;
431 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
433 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
438 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
444 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
445 struct device_node *node,
446 struct pinctrl_map **map,
447 unsigned *reserved_maps,
450 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
451 int num_pins, num_funcs, maps_per_pin, i, err;
452 struct mtk_pinctrl_group *grp;
453 unsigned int num_configs;
454 bool has_config = false;
455 unsigned long *configs;
456 u32 pinfunc, pin, func;
457 struct property *pins;
458 unsigned reserve = 0;
460 pins = of_find_property(node, "pinmux", NULL);
462 dev_err(hw->dev, "missing pins property in node %pOFn .\n",
467 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
475 num_pins = pins->length / sizeof(u32);
476 num_funcs = num_pins;
480 if (has_config && num_pins >= 1)
483 if (!num_pins || !maps_per_pin) {
488 reserve = num_pins * maps_per_pin;
490 err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
495 for (i = 0; i < num_pins; i++) {
496 err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
500 pin = MTK_GET_PIN_NO(pinfunc);
501 func = MTK_GET_PIN_FUNC(pinfunc);
503 if (pin >= hw->soc->npins ||
504 func >= ARRAY_SIZE(mtk_gpio_functions)) {
505 dev_err(hw->dev, "invalid pins value.\n");
510 grp = mtk_pctrl_find_group_by_pin(hw, pin);
512 dev_err(hw->dev, "unable to match pin %d to group\n",
518 err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
519 reserved_maps, num_maps);
524 err = pinctrl_utils_add_map_configs(pctldev, map,
530 PIN_MAP_TYPE_CONFIGS_GROUP);
543 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
544 struct device_node *np_config,
545 struct pinctrl_map **map,
548 struct device_node *np;
549 unsigned reserved_maps;
556 for_each_child_of_node(np_config, np) {
557 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
561 pinctrl_utils_free_map(pctldev, *map, *num_maps);
570 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
572 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
574 return hw->soc->ngrps;
577 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
580 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
582 return hw->groups[group].name;
585 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
586 unsigned group, const unsigned **pins,
589 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
591 *pins = (unsigned *)&hw->groups[group].pin;
597 static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
599 const struct mtk_pin_desc *desc;
602 if (gpio >= hw->soc->npins)
605 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
607 err = mtk_hw_get_value(hw, desc, field, &value);
614 #define mtk_pctrl_get_pinmux(hw, gpio) \
615 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
617 #define mtk_pctrl_get_direction(hw, gpio) \
618 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
620 #define mtk_pctrl_get_out(hw, gpio) \
621 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
623 #define mtk_pctrl_get_in(hw, gpio) \
624 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
626 #define mtk_pctrl_get_smt(hw, gpio) \
627 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
629 #define mtk_pctrl_get_ies(hw, gpio) \
630 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
632 #define mtk_pctrl_get_driving(hw, gpio) \
633 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
635 ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
636 unsigned int gpio, char *buf, unsigned int buf_len)
638 int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
639 const struct mtk_pin_desc *desc;
640 u32 try_all_type = 0;
642 if (gpio >= hw->soc->npins)
645 if (mtk_is_virt_gpio(hw, gpio))
648 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
649 pinmux = mtk_pctrl_get_pinmux(hw, gpio);
650 if (pinmux >= hw->soc->nfuncs)
651 pinmux -= hw->soc->nfuncs;
653 mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
655 if (hw->soc->pull_type)
656 try_all_type = hw->soc->pull_type[desc->number];
658 if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
663 if (pullen == MTK_PUPD_SET_R1R0_00) {
667 } else if (pullen == MTK_PUPD_SET_R1R0_01) {
671 } else if (pullen == MTK_PUPD_SET_R1R0_10) {
675 } else if (pullen == MTK_PUPD_SET_R1R0_11) {
682 if (pullen >= MTK_PULL_SET_RSEL_000 &&
683 pullen <= MTK_PULL_SET_RSEL_111) {
684 rsel = pullen - MTK_PULL_SET_RSEL_000;
688 len += scnprintf(buf + len, buf_len - len,
689 "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
692 mtk_pctrl_get_direction(hw, gpio),
693 mtk_pctrl_get_out(hw, gpio),
694 mtk_pctrl_get_in(hw, gpio),
695 mtk_pctrl_get_driving(hw, gpio),
696 mtk_pctrl_get_smt(hw, gpio),
697 mtk_pctrl_get_ies(hw, gpio),
702 len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
704 len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
708 EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin);
710 #define PIN_DBG_BUF_SZ 96
711 static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
714 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
715 char buf[PIN_DBG_BUF_SZ] = { 0 };
717 (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
719 seq_printf(s, "%s", buf);
722 static const struct pinctrl_ops mtk_pctlops = {
723 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
724 .dt_free_map = pinctrl_utils_free_map,
725 .get_groups_count = mtk_pctrl_get_groups_count,
726 .get_group_name = mtk_pctrl_get_group_name,
727 .get_group_pins = mtk_pctrl_get_group_pins,
728 .pin_dbg_show = mtk_pctrl_dbg_show,
731 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
733 return ARRAY_SIZE(mtk_gpio_functions);
736 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
739 return mtk_gpio_functions[selector];
742 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
744 const char * const **groups,
745 unsigned * const num_groups)
747 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
749 *groups = hw->grp_names;
750 *num_groups = hw->soc->ngrps;
755 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
759 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
760 struct mtk_pinctrl_group *grp = hw->groups + group;
761 const struct mtk_func_desc *desc_func;
762 const struct mtk_pin_desc *desc;
765 ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
767 dev_err(hw->dev, "invalid function %d on group %d .\n",
772 desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
776 desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
777 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
782 static const struct pinmux_ops mtk_pmxops = {
783 .get_functions_count = mtk_pmx_get_funcs_cnt,
784 .get_function_name = mtk_pmx_get_func_name,
785 .get_function_groups = mtk_pmx_get_func_groups,
786 .set_mux = mtk_pmx_set_mux,
787 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
788 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
791 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
792 unsigned long *config)
794 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
795 struct mtk_pinctrl_group *grp = &hw->groups[group];
797 /* One pin per group only */
798 return mtk_pinconf_get(pctldev, grp->pin, config);
801 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
802 unsigned long *configs, unsigned num_configs)
804 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
805 struct mtk_pinctrl_group *grp = &hw->groups[group];
806 bool drive_strength_uA_found = false;
807 bool adv_drve_strength_found = false;
810 for (i = 0; i < num_configs; i++) {
811 ret = mtk_pinconf_set(pctldev, grp->pin,
812 pinconf_to_config_param(configs[i]),
813 pinconf_to_config_argument(configs[i]));
817 if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
818 drive_strength_uA_found = true;
819 if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
820 adv_drve_strength_found = true;
824 * Disable advanced drive strength mode if drive-strength-microamp
825 * is not set. However, mediatek,drive-strength-adv takes precedence
826 * as its value can explicitly request the mode be enabled or not.
828 if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
829 !adv_drve_strength_found)
830 hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
835 static const struct pinconf_ops mtk_confops = {
836 .pin_config_get = mtk_pinconf_get,
837 .pin_config_group_get = mtk_pconf_group_get,
838 .pin_config_group_set = mtk_pconf_group_set,
842 static struct pinctrl_desc mtk_desc = {
843 .name = PINCTRL_PINCTRL_DEV,
844 .pctlops = &mtk_pctlops,
845 .pmxops = &mtk_pmxops,
846 .confops = &mtk_confops,
847 .owner = THIS_MODULE,
850 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
852 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
853 const struct mtk_pin_desc *desc;
856 if (gpio >= hw->soc->npins)
860 * "Virtual" GPIOs are always and only used for interrupts
861 * Since they are only used for interrupts, they are always inputs
863 if (mtk_is_virt_gpio(hw, gpio))
866 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
868 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
873 return GPIO_LINE_DIRECTION_OUT;
875 return GPIO_LINE_DIRECTION_IN;
878 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
880 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
881 const struct mtk_pin_desc *desc;
884 if (gpio >= hw->soc->npins)
887 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
889 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
896 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
898 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
899 const struct mtk_pin_desc *desc;
901 if (gpio >= hw->soc->npins)
904 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
906 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
909 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
911 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
913 if (gpio >= hw->soc->npins)
916 return pinctrl_gpio_direction_input(chip->base + gpio);
919 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
922 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
924 if (gpio >= hw->soc->npins)
927 mtk_gpio_set(chip, gpio, value);
929 return pinctrl_gpio_direction_output(chip->base + gpio);
932 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
934 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
935 const struct mtk_pin_desc *desc;
940 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
942 if (desc->eint.eint_n == EINT_NA)
945 return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
948 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
949 unsigned long config)
951 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
952 const struct mtk_pin_desc *desc;
955 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
958 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
959 desc->eint.eint_n == EINT_NA)
962 debounce = pinconf_to_config_argument(config);
964 return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
967 static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
969 struct gpio_chip *chip = &hw->chip;
972 chip->label = PINCTRL_PINCTRL_DEV;
973 chip->parent = hw->dev;
974 chip->request = gpiochip_generic_request;
975 chip->free = gpiochip_generic_free;
976 chip->get_direction = mtk_gpio_get_direction;
977 chip->direction_input = mtk_gpio_direction_input;
978 chip->direction_output = mtk_gpio_direction_output;
979 chip->get = mtk_gpio_get;
980 chip->set = mtk_gpio_set;
981 chip->to_irq = mtk_gpio_to_irq;
982 chip->set_config = mtk_gpio_set_config;
984 chip->ngpio = hw->soc->npins;
985 chip->of_gpio_n_cells = 2;
987 ret = gpiochip_add_data(chip, hw);
994 static int mtk_pctrl_build_state(struct platform_device *pdev)
996 struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
999 /* Allocate groups */
1000 hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
1001 sizeof(*hw->groups), GFP_KERNEL);
1005 /* We assume that one pin is one group, use pin name as group name. */
1006 hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
1007 sizeof(*hw->grp_names), GFP_KERNEL);
1011 for (i = 0; i < hw->soc->npins; i++) {
1012 const struct mtk_pin_desc *pin = hw->soc->pins + i;
1013 struct mtk_pinctrl_group *group = hw->groups + i;
1015 group->name = pin->name;
1016 group->pin = pin->number;
1018 hw->grp_names[i] = pin->name;
1024 int mtk_paris_pinctrl_probe(struct platform_device *pdev)
1026 struct device *dev = &pdev->dev;
1027 struct pinctrl_pin_desc *pins;
1028 struct mtk_pinctrl *hw;
1031 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
1035 platform_set_drvdata(pdev, hw);
1037 hw->soc = device_get_match_data(dev);
1041 hw->dev = &pdev->dev;
1043 if (!hw->soc->nbase_names)
1044 return dev_err_probe(dev, -EINVAL,
1045 "SoC should be assigned at least one register base\n");
1047 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
1048 sizeof(*hw->base), GFP_KERNEL);
1052 for (i = 0; i < hw->soc->nbase_names; i++) {
1053 hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
1054 hw->soc->base_names[i]);
1055 if (IS_ERR(hw->base[i]))
1056 return PTR_ERR(hw->base[i]);
1059 hw->nbase = hw->soc->nbase_names;
1061 if (of_find_property(hw->dev->of_node,
1062 "mediatek,rsel-resistance-in-si-unit", NULL))
1063 hw->rsel_si_unit = true;
1065 hw->rsel_si_unit = false;
1067 spin_lock_init(&hw->lock);
1069 err = mtk_pctrl_build_state(pdev);
1071 return dev_err_probe(dev, err, "build state failed\n");
1073 /* Copy from internal struct mtk_pin_desc to register to the core */
1074 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
1079 for (i = 0; i < hw->soc->npins; i++) {
1080 pins[i].number = hw->soc->pins[i].number;
1081 pins[i].name = hw->soc->pins[i].name;
1084 /* Setup pins descriptions per SoC types */
1085 mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
1086 mtk_desc.npins = hw->soc->npins;
1087 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
1088 mtk_desc.custom_params = mtk_custom_bindings;
1089 #ifdef CONFIG_DEBUG_FS
1090 mtk_desc.custom_conf_items = mtk_conf_items;
1093 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
1098 err = pinctrl_enable(hw->pctrl);
1102 err = mtk_build_eint(hw, pdev);
1104 dev_warn(&pdev->dev,
1105 "Failed to add EINT, but pinctrl still can work\n");
1107 /* Build gpiochip should be after pinctrl_enable is done */
1108 err = mtk_build_gpiochip(hw);
1110 return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
1112 platform_set_drvdata(pdev, hw);
1116 EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe);
1118 static int mtk_paris_pinctrl_suspend(struct device *device)
1120 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1122 return mtk_eint_do_suspend(pctl->eint);
1125 static int mtk_paris_pinctrl_resume(struct device *device)
1127 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1129 return mtk_eint_do_resume(pctl->eint);
1132 const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
1133 .suspend_noirq = mtk_paris_pinctrl_suspend,
1134 .resume_noirq = mtk_paris_pinctrl_resume,
1137 MODULE_LICENSE("GPL v2");
1138 MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris");