1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/platform_device.h>
15 #include <linux/module.h>
16 #include <linux/of_irq.h>
19 #include "pinctrl-mtk-common-v2.h"
22 * struct mtk_drive_desc - the structure that holds the information
23 * of the driving current
24 * @min: the minimum current of this group
25 * @max: the maximum current of this group
26 * @step: the step current of this group
27 * @scal: the weight factor
29 * formula: output = ((input) / step - 1) * scal
31 struct mtk_drive_desc {
38 /* The groups of drive strength */
39 static const struct mtk_drive_desc mtk_drive[] = {
40 [DRV_GRP0] = { 4, 16, 4, 1 },
41 [DRV_GRP1] = { 4, 16, 4, 2 },
42 [DRV_GRP2] = { 2, 8, 2, 1 },
43 [DRV_GRP3] = { 2, 8, 2, 2 },
44 [DRV_GRP4] = { 2, 16, 2, 1 },
47 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
49 writel_relaxed(val, pctl->base[i] + reg);
52 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
54 return readl_relaxed(pctl->base[i] + reg);
57 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
61 val = mtk_r32(pctl, i, reg);
64 mtk_w32(pctl, i, reg, val);
67 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
68 const struct mtk_pin_desc *desc,
69 int field, struct mtk_pin_field *pfd)
71 const struct mtk_pin_field_calc *c;
72 const struct mtk_pin_reg_calc *rc;
73 int start = 0, end, check;
77 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
78 rc = &hw->soc->reg_cal[field];
81 "Not support field %d for this soc\n", field);
85 end = rc->nranges - 1;
87 while (start <= end) {
88 check = (start + end) >> 1;
89 if (desc->number >= rc->range[check].s_pin
90 && desc->number <= rc->range[check].e_pin) {
93 } else if (start == end)
95 else if (desc->number < rc->range[check].s_pin)
102 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
103 field, desc->number, desc->name);
107 c = rc->range + check;
109 if (c->i_base > hw->nbase - 1) {
111 "Invalid base for field %d for pin = %d (%s)\n",
112 field, desc->number, desc->name);
116 /* Calculated bits as the overall offset the pin is located at,
117 * if c->fixed is held, that determines the all the pins in the
118 * range use the same field with the s_pin.
120 bits = c->fixed ? c->s_bit : c->s_bit +
121 (desc->number - c->s_pin) * (c->x_bits);
123 /* Fill pfd from bits. For example 32-bit register applied is assumed
124 * when c->sz_reg is equal to 32.
126 pfd->index = c->i_base;
127 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
128 pfd->bitpos = bits % c->sz_reg;
129 pfd->mask = (1 << c->x_bits) - 1;
131 /* pfd->next is used for indicating that bit wrapping-around happens
132 * which requires the manipulation for bit 0 starting in the next
133 * register to form the complete field read/write.
135 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
140 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
141 const struct mtk_pin_desc *desc,
142 int field, struct mtk_pin_field *pfd)
144 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
145 dev_err(hw->dev, "Invalid Field %d\n", field);
149 return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
152 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
154 *l = 32 - pf->bitpos;
155 *h = get_count_order(pf->mask) - *l;
158 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
159 struct mtk_pin_field *pf, int value)
161 int nbits_l, nbits_h;
163 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
165 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
166 (value & pf->mask) << pf->bitpos);
168 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
169 (value & pf->mask) >> nbits_l);
172 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
173 struct mtk_pin_field *pf, int *value)
175 int nbits_l, nbits_h, h, l;
177 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
179 l = (mtk_r32(hw, pf->index, pf->offset)
180 >> pf->bitpos) & (BIT(nbits_l) - 1);
181 h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
182 & (BIT(nbits_h) - 1);
184 *value = (h << nbits_l) | l;
187 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
188 int field, int value)
190 struct mtk_pin_field pf;
193 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
197 if (value < 0 || value > pf.mask)
201 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
202 (value & pf.mask) << pf.bitpos);
204 mtk_hw_write_cross_field(hw, &pf, value);
208 EXPORT_SYMBOL_GPL(mtk_hw_set_value);
210 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
211 int field, int *value)
213 struct mtk_pin_field pf;
216 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
221 *value = (mtk_r32(hw, pf.index, pf.offset)
222 >> pf.bitpos) & pf.mask;
224 mtk_hw_read_cross_field(hw, &pf, value);
228 EXPORT_SYMBOL_GPL(mtk_hw_get_value);
230 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
232 const struct mtk_pin_desc *desc;
235 desc = (const struct mtk_pin_desc *)hw->soc->pins;
237 while (i < hw->soc->npins) {
238 if (desc[i].eint.eint_n == eint_n)
239 return desc[i].number;
247 * Virtual GPIO only used inside SOC and not being exported to outside SOC.
248 * Some modules use virtual GPIO as eint (e.g. pmif or usb).
249 * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
250 * and we can set GPIO as eint.
251 * But some modules use specific eint which doesn't have real GPIO pin.
252 * So we use virtual GPIO to map it.
255 bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
257 const struct mtk_pin_desc *desc;
258 bool virt_gpio = false;
260 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
262 /* if the GPIO is not supported for eint mode */
263 if (desc->eint.eint_m == NO_EINT_SUPPORT)
266 if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
271 EXPORT_SYMBOL_GPL(mtk_is_virt_gpio);
273 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
274 unsigned int *gpio_n,
275 struct gpio_chip **gpio_chip)
277 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
278 const struct mtk_pin_desc *desc;
280 desc = (const struct mtk_pin_desc *)hw->soc->pins;
281 *gpio_chip = &hw->chip;
284 * Be greedy to guess first gpio_n is equal to eint_n.
285 * Only eint virtual eint number is greater than gpio number.
287 if (hw->soc->npins > eint_n &&
288 desc[eint_n].eint.eint_n == eint_n)
291 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
293 return *gpio_n == EINT_NA ? -EINVAL : 0;
296 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
298 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
299 const struct mtk_pin_desc *desc;
300 struct gpio_chip *gpio_chip;
304 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
308 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
310 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
317 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
319 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
320 const struct mtk_pin_desc *desc;
321 struct gpio_chip *gpio_chip;
325 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
329 if (mtk_is_virt_gpio(hw, gpio_n))
332 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
334 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
339 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
343 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
344 /* SMT is supposed to be supported by every real GPIO and doesn't
345 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
346 * is just for adding EINT support to these virtual GPIOs. It should
347 * add an extra flag in the pin descriptor when more pins with
348 * distinctive characteristic come out.
350 if (err && err != -ENOTSUPP)
356 static const struct mtk_eint_xt mtk_eint_xt = {
357 .get_gpio_n = mtk_xt_get_gpio_n,
358 .get_gpio_state = mtk_xt_get_gpio_state,
359 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
362 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
364 struct device_node *np = pdev->dev.of_node;
367 if (!IS_ENABLED(CONFIG_EINT_MTK))
370 if (!of_property_read_bool(np, "interrupt-controller"))
373 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
377 hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint");
378 if (IS_ERR(hw->eint->base)) {
379 ret = PTR_ERR(hw->eint->base);
383 hw->eint->irq = irq_of_parse_and_map(np, 0);
384 if (!hw->eint->irq) {
389 if (!hw->soc->eint_hw) {
394 hw->eint->dev = &pdev->dev;
395 hw->eint->hw = hw->soc->eint_hw;
397 hw->eint->gpio_xlate = &mtk_eint_xt;
399 return mtk_eint_do_init(hw->eint);
402 devm_kfree(hw->dev, hw->eint);
406 EXPORT_SYMBOL_GPL(mtk_build_eint);
409 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
410 const struct mtk_pin_desc *desc)
414 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
419 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
426 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set);
428 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
429 const struct mtk_pin_desc *desc, int *res)
434 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
438 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
442 if (v == MTK_ENABLE || v2 == MTK_ENABLE)
449 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get);
451 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
452 const struct mtk_pin_desc *desc, bool pullup)
456 arg = pullup ? 1 : 2;
458 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
462 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
469 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set);
471 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
472 const struct mtk_pin_desc *desc, bool pullup, int *res)
476 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
478 err = mtk_hw_get_value(hw, desc, reg, &v);
489 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get);
492 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
493 const struct mtk_pin_desc *desc)
497 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
504 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1);
506 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
507 const struct mtk_pin_desc *desc, int *res)
511 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
522 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1);
524 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
525 const struct mtk_pin_desc *desc, bool pullup)
529 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
531 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
536 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
542 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1);
544 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
545 const struct mtk_pin_desc *desc, bool pullup,
550 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
554 if (v == MTK_DISABLE)
557 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
561 if (pullup ^ (v == MTK_PULLUP))
568 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);
570 /* Combo for the following pull register type:
572 * 2. PULLSEL + PULLEN
575 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
576 const struct mtk_pin_desc *desc,
581 if (arg == MTK_DISABLE) {
584 } else if ((arg == MTK_ENABLE) && pullup) {
587 } else if ((arg == MTK_ENABLE) && !pullup) {
595 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
599 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
605 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
606 const struct mtk_pin_desc *desc,
611 if (arg == MTK_DISABLE)
613 else if (arg == MTK_ENABLE)
620 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
624 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
630 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
631 const struct mtk_pin_desc *desc,
636 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
640 } else if (arg == MTK_PUPD_SET_R1R0_01) {
643 } else if (arg == MTK_PUPD_SET_R1R0_10) {
646 } else if (arg == MTK_PUPD_SET_R1R0_11) {
654 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
655 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
659 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
663 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
669 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
670 const struct mtk_pin_desc *desc,
671 u32 *pullup, u32 *enable)
675 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
679 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
683 if (pu == 0 && pd == 0) {
685 *enable = MTK_DISABLE;
686 } else if (pu == 1 && pd == 0) {
688 *enable = MTK_ENABLE;
689 } else if (pu == 0 && pd == 1) {
691 *enable = MTK_ENABLE;
699 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
700 const struct mtk_pin_desc *desc,
701 u32 *pullup, u32 *enable)
705 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
709 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
715 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
716 const struct mtk_pin_desc *desc,
717 u32 *pullup, u32 *enable)
721 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
724 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
725 *pullup = !(*pullup);
727 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
731 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
735 if ((r1 == 0) && (r0 == 0))
736 *enable = MTK_PUPD_SET_R1R0_00;
737 else if ((r1 == 0) && (r0 == 1))
738 *enable = MTK_PUPD_SET_R1R0_01;
739 else if ((r1 == 1) && (r0 == 0))
740 *enable = MTK_PUPD_SET_R1R0_10;
741 else if ((r1 == 1) && (r0 == 1))
742 *enable = MTK_PUPD_SET_R1R0_11;
750 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
751 const struct mtk_pin_desc *desc,
756 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
760 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
764 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
769 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
771 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
772 const struct mtk_pin_desc *desc,
773 u32 *pullup, u32 *enable)
777 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
781 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
785 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
790 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
793 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
794 const struct mtk_pin_desc *desc, u32 arg)
796 const struct mtk_drive_desc *tb;
799 tb = &mtk_drive[desc->drv_n];
800 /* 4mA when (e8, e4) = (0, 0)
801 * 8mA when (e8, e4) = (0, 1)
802 * 12mA when (e8, e4) = (1, 0)
803 * 16mA when (e8, e4) = (1, 1)
805 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
806 arg = (arg / tb->step - 1) * tb->scal;
807 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
812 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
820 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set);
822 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
823 const struct mtk_pin_desc *desc, int *val)
825 const struct mtk_drive_desc *tb;
828 tb = &mtk_drive[desc->drv_n];
830 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
834 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
838 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
839 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
841 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
845 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get);
848 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
849 const struct mtk_pin_desc *desc, u32 arg)
851 const struct mtk_drive_desc *tb;
854 tb = &mtk_drive[desc->drv_n];
856 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
857 arg = (arg / tb->step - 1) * tb->scal;
859 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
867 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1);
869 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
870 const struct mtk_pin_desc *desc, int *val)
872 const struct mtk_drive_desc *tb;
875 tb = &mtk_drive[desc->drv_n];
877 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
881 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
885 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1);
887 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
888 const struct mtk_pin_desc *desc, u32 arg)
890 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
892 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw);
894 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
895 const struct mtk_pin_desc *desc, int *val)
897 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
899 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw);
901 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
902 const struct mtk_pin_desc *desc, bool pullup,
907 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
908 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
909 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
910 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
912 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
916 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
921 arg = pullup ? 0 : 1;
923 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
925 /* If PUPD register is not supported for that pin, let's fallback to
926 * general bias control.
928 if (err == -ENOTSUPP) {
929 if (hw->soc->bias_set) {
930 err = hw->soc->bias_set(hw, desc, pullup);
934 err = mtk_pinconf_bias_set_rev1(hw, desc, pullup);
936 err = mtk_pinconf_bias_set(hw, desc, pullup);
942 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set);
944 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
945 const struct mtk_pin_desc *desc, bool pullup,
951 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
953 /* If PUPD register is not supported for that pin, let's fallback to
954 * general bias control.
956 if (err == -ENOTSUPP) {
957 if (hw->soc->bias_get) {
958 err = hw->soc->bias_get(hw, desc, pullup, val);
965 /* t == 0 supposes PULLUP for the customized PULL setup */
973 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
977 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
981 *val = (t | t2 << 1) & 0x7;
985 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get);
987 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
988 const struct mtk_pin_desc *desc, u32 arg)
992 int e0 = !!(arg & 2);
993 int e1 = !!(arg & 4);
995 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
1002 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
1006 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
1012 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set);
1014 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
1015 const struct mtk_pin_desc *desc, u32 *val)
1020 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
1024 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
1028 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
1032 *val = (en | e0 << 1 | e1 << 2) & 0x7;
1036 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get);
1038 MODULE_LICENSE("GPL v2");
1039 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1040 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");