1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/platform_device.h>
15 #include <linux/module.h>
16 #include <linux/of_irq.h>
19 #include "pinctrl-mtk-common-v2.h"
22 * struct mtk_drive_desc - the structure that holds the information
23 * of the driving current
24 * @min: the minimum current of this group
25 * @max: the maximum current of this group
26 * @step: the step current of this group
27 * @scal: the weight factor
29 * formula: output = ((input) / step - 1) * scal
31 struct mtk_drive_desc {
38 /* The groups of drive strength */
39 static const struct mtk_drive_desc mtk_drive[] = {
40 [DRV_GRP0] = { 4, 16, 4, 1 },
41 [DRV_GRP1] = { 4, 16, 4, 2 },
42 [DRV_GRP2] = { 2, 8, 2, 1 },
43 [DRV_GRP3] = { 2, 8, 2, 2 },
44 [DRV_GRP4] = { 2, 16, 2, 1 },
47 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
49 writel_relaxed(val, pctl->base[i] + reg);
52 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
54 return readl_relaxed(pctl->base[i] + reg);
57 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
62 spin_lock_irqsave(&pctl->lock, flags);
64 val = mtk_r32(pctl, i, reg);
67 mtk_w32(pctl, i, reg, val);
69 spin_unlock_irqrestore(&pctl->lock, flags);
72 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
73 const struct mtk_pin_desc *desc,
74 int field, struct mtk_pin_field *pfd)
76 const struct mtk_pin_field_calc *c;
77 const struct mtk_pin_reg_calc *rc;
78 int start = 0, end, check;
82 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
83 rc = &hw->soc->reg_cal[field];
86 "Not support field %d for this soc\n", field);
90 end = rc->nranges - 1;
92 while (start <= end) {
93 check = (start + end) >> 1;
94 if (desc->number >= rc->range[check].s_pin
95 && desc->number <= rc->range[check].e_pin) {
98 } else if (start == end)
100 else if (desc->number < rc->range[check].s_pin)
107 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
108 field, desc->number, desc->name);
112 c = rc->range + check;
114 if (c->i_base > hw->nbase - 1) {
116 "Invalid base for field %d for pin = %d (%s)\n",
117 field, desc->number, desc->name);
121 /* Calculated bits as the overall offset the pin is located at,
122 * if c->fixed is held, that determines the all the pins in the
123 * range use the same field with the s_pin.
125 bits = c->fixed ? c->s_bit : c->s_bit +
126 (desc->number - c->s_pin) * (c->x_bits);
128 /* Fill pfd from bits. For example 32-bit register applied is assumed
129 * when c->sz_reg is equal to 32.
131 pfd->index = c->i_base;
132 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
133 pfd->bitpos = bits % c->sz_reg;
134 pfd->mask = (1 << c->x_bits) - 1;
136 /* pfd->next is used for indicating that bit wrapping-around happens
137 * which requires the manipulation for bit 0 starting in the next
138 * register to form the complete field read/write.
140 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
145 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
146 const struct mtk_pin_desc *desc,
147 int field, struct mtk_pin_field *pfd)
149 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
150 dev_err(hw->dev, "Invalid Field %d\n", field);
154 return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
157 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
159 *l = 32 - pf->bitpos;
160 *h = get_count_order(pf->mask) - *l;
163 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
164 struct mtk_pin_field *pf, int value)
166 int nbits_l, nbits_h;
168 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
170 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
171 (value & pf->mask) << pf->bitpos);
173 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
174 (value & pf->mask) >> nbits_l);
177 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
178 struct mtk_pin_field *pf, int *value)
180 int nbits_l, nbits_h, h, l;
182 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
184 l = (mtk_r32(hw, pf->index, pf->offset)
185 >> pf->bitpos) & (BIT(nbits_l) - 1);
186 h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
187 & (BIT(nbits_h) - 1);
189 *value = (h << nbits_l) | l;
192 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
193 int field, int value)
195 struct mtk_pin_field pf;
198 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
202 if (value < 0 || value > pf.mask)
206 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
207 (value & pf.mask) << pf.bitpos);
209 mtk_hw_write_cross_field(hw, &pf, value);
213 EXPORT_SYMBOL_GPL(mtk_hw_set_value);
215 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
216 int field, int *value)
218 struct mtk_pin_field pf;
221 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
226 *value = (mtk_r32(hw, pf.index, pf.offset)
227 >> pf.bitpos) & pf.mask;
229 mtk_hw_read_cross_field(hw, &pf, value);
233 EXPORT_SYMBOL_GPL(mtk_hw_get_value);
235 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
237 const struct mtk_pin_desc *desc;
240 desc = (const struct mtk_pin_desc *)hw->soc->pins;
242 while (i < hw->soc->npins) {
243 if (desc[i].eint.eint_n == eint_n)
244 return desc[i].number;
252 * Virtual GPIO only used inside SOC and not being exported to outside SOC.
253 * Some modules use virtual GPIO as eint (e.g. pmif or usb).
254 * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
255 * and we can set GPIO as eint.
256 * But some modules use specific eint which doesn't have real GPIO pin.
257 * So we use virtual GPIO to map it.
260 bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
262 const struct mtk_pin_desc *desc;
263 bool virt_gpio = false;
265 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
267 /* if the GPIO is not supported for eint mode */
268 if (desc->eint.eint_m == NO_EINT_SUPPORT)
271 if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
276 EXPORT_SYMBOL_GPL(mtk_is_virt_gpio);
278 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
279 unsigned int *gpio_n,
280 struct gpio_chip **gpio_chip)
282 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
283 const struct mtk_pin_desc *desc;
285 desc = (const struct mtk_pin_desc *)hw->soc->pins;
286 *gpio_chip = &hw->chip;
289 * Be greedy to guess first gpio_n is equal to eint_n.
290 * Only eint virtual eint number is greater than gpio number.
292 if (hw->soc->npins > eint_n &&
293 desc[eint_n].eint.eint_n == eint_n)
296 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
298 return *gpio_n == EINT_NA ? -EINVAL : 0;
301 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
303 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
304 const struct mtk_pin_desc *desc;
305 struct gpio_chip *gpio_chip;
309 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
313 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
315 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
322 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
324 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
325 const struct mtk_pin_desc *desc;
326 struct gpio_chip *gpio_chip;
330 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
334 if (mtk_is_virt_gpio(hw, gpio_n))
337 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
339 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
344 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
348 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
349 /* SMT is supposed to be supported by every real GPIO and doesn't
350 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
351 * is just for adding EINT support to these virtual GPIOs. It should
352 * add an extra flag in the pin descriptor when more pins with
353 * distinctive characteristic come out.
355 if (err && err != -ENOTSUPP)
361 static const struct mtk_eint_xt mtk_eint_xt = {
362 .get_gpio_n = mtk_xt_get_gpio_n,
363 .get_gpio_state = mtk_xt_get_gpio_state,
364 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
367 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
369 struct device_node *np = pdev->dev.of_node;
372 if (!IS_ENABLED(CONFIG_EINT_MTK))
375 if (!of_property_read_bool(np, "interrupt-controller"))
378 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
382 hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint");
383 if (IS_ERR(hw->eint->base)) {
384 ret = PTR_ERR(hw->eint->base);
388 hw->eint->irq = irq_of_parse_and_map(np, 0);
389 if (!hw->eint->irq) {
394 if (!hw->soc->eint_hw) {
399 hw->eint->dev = &pdev->dev;
400 hw->eint->hw = hw->soc->eint_hw;
402 hw->eint->gpio_xlate = &mtk_eint_xt;
404 return mtk_eint_do_init(hw->eint);
407 devm_kfree(hw->dev, hw->eint);
411 EXPORT_SYMBOL_GPL(mtk_build_eint);
414 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
415 const struct mtk_pin_desc *desc)
419 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
424 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
431 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set);
433 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
434 const struct mtk_pin_desc *desc, int *res)
439 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
443 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
447 if (v == MTK_ENABLE || v2 == MTK_ENABLE)
454 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get);
456 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
457 const struct mtk_pin_desc *desc, bool pullup)
461 arg = pullup ? 1 : 2;
463 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
467 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
474 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set);
476 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
477 const struct mtk_pin_desc *desc, bool pullup, int *res)
481 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
483 err = mtk_hw_get_value(hw, desc, reg, &v);
494 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get);
497 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
498 const struct mtk_pin_desc *desc)
500 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
503 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1);
505 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
506 const struct mtk_pin_desc *desc, int *res)
510 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
521 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1);
523 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
524 const struct mtk_pin_desc *desc, bool pullup)
528 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
530 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
535 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
541 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1);
543 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
544 const struct mtk_pin_desc *desc, bool pullup,
549 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
553 if (v == MTK_DISABLE)
556 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
560 if (pullup ^ (v == MTK_PULLUP))
567 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);
569 /* Combo for the following pull register type:
571 * 2. PULLSEL + PULLEN
574 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
575 const struct mtk_pin_desc *desc,
580 if (arg == MTK_DISABLE) {
583 } else if ((arg == MTK_ENABLE) && pullup) {
586 } else if ((arg == MTK_ENABLE) && !pullup) {
594 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
598 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
604 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
605 const struct mtk_pin_desc *desc,
610 if (arg == MTK_DISABLE)
612 else if (arg == MTK_ENABLE)
619 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
623 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
629 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
630 const struct mtk_pin_desc *desc,
635 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
639 } else if (arg == MTK_PUPD_SET_R1R0_01) {
642 } else if (arg == MTK_PUPD_SET_R1R0_10) {
645 } else if (arg == MTK_PUPD_SET_R1R0_11) {
653 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
654 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
658 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
662 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
668 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
669 const struct mtk_pin_desc *desc,
670 u32 *pullup, u32 *enable)
674 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
678 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
682 if (pu == 0 && pd == 0) {
684 *enable = MTK_DISABLE;
685 } else if (pu == 1 && pd == 0) {
687 *enable = MTK_ENABLE;
688 } else if (pu == 0 && pd == 1) {
690 *enable = MTK_ENABLE;
698 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
699 const struct mtk_pin_desc *desc,
700 u32 *pullup, u32 *enable)
704 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
708 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
714 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
715 const struct mtk_pin_desc *desc,
716 u32 *pullup, u32 *enable)
720 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
723 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
724 *pullup = !(*pullup);
726 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
730 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
734 if ((r1 == 0) && (r0 == 0))
735 *enable = MTK_PUPD_SET_R1R0_00;
736 else if ((r1 == 0) && (r0 == 1))
737 *enable = MTK_PUPD_SET_R1R0_01;
738 else if ((r1 == 1) && (r0 == 0))
739 *enable = MTK_PUPD_SET_R1R0_10;
740 else if ((r1 == 1) && (r0 == 1))
741 *enable = MTK_PUPD_SET_R1R0_11;
749 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
750 const struct mtk_pin_desc *desc,
755 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
759 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
763 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
768 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
770 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
771 const struct mtk_pin_desc *desc,
772 u32 *pullup, u32 *enable)
776 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
780 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
784 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
789 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
792 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
793 const struct mtk_pin_desc *desc, u32 arg)
795 const struct mtk_drive_desc *tb;
798 tb = &mtk_drive[desc->drv_n];
799 /* 4mA when (e8, e4) = (0, 0)
800 * 8mA when (e8, e4) = (0, 1)
801 * 12mA when (e8, e4) = (1, 0)
802 * 16mA when (e8, e4) = (1, 1)
804 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
805 arg = (arg / tb->step - 1) * tb->scal;
806 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
811 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
819 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set);
821 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
822 const struct mtk_pin_desc *desc, int *val)
824 const struct mtk_drive_desc *tb;
827 tb = &mtk_drive[desc->drv_n];
829 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
833 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
837 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
838 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
840 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
844 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get);
847 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
848 const struct mtk_pin_desc *desc, u32 arg)
850 const struct mtk_drive_desc *tb;
853 tb = &mtk_drive[desc->drv_n];
855 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
856 arg = (arg / tb->step - 1) * tb->scal;
858 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
866 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1);
868 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
869 const struct mtk_pin_desc *desc, int *val)
871 const struct mtk_drive_desc *tb;
874 tb = &mtk_drive[desc->drv_n];
876 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
880 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
884 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1);
886 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
887 const struct mtk_pin_desc *desc, u32 arg)
889 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
891 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw);
893 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
894 const struct mtk_pin_desc *desc, int *val)
896 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
898 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw);
900 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
901 const struct mtk_pin_desc *desc, bool pullup,
906 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
907 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
908 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
909 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
911 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
915 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
920 arg = pullup ? 0 : 1;
922 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
924 /* If PUPD register is not supported for that pin, let's fallback to
925 * general bias control.
927 if (err == -ENOTSUPP) {
928 if (hw->soc->bias_set) {
929 err = hw->soc->bias_set(hw, desc, pullup);
933 err = mtk_pinconf_bias_set_rev1(hw, desc, pullup);
935 err = mtk_pinconf_bias_set(hw, desc, pullup);
941 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set);
943 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
944 const struct mtk_pin_desc *desc, bool pullup,
950 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
952 /* If PUPD register is not supported for that pin, let's fallback to
953 * general bias control.
955 if (err == -ENOTSUPP) {
956 if (hw->soc->bias_get) {
957 err = hw->soc->bias_get(hw, desc, pullup, val);
964 /* t == 0 supposes PULLUP for the customized PULL setup */
972 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
976 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
980 *val = (t | t2 << 1) & 0x7;
984 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get);
986 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
987 const struct mtk_pin_desc *desc, u32 arg)
991 int e0 = !!(arg & 2);
992 int e1 = !!(arg & 4);
994 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
1001 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
1005 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
1011 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set);
1013 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
1014 const struct mtk_pin_desc *desc, u32 *val)
1019 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
1023 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
1027 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
1031 *val = (en | e0 << 1 | e1 << 2) & 0x7;
1035 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get);
1037 int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw,
1038 const struct mtk_pin_desc *desc, u32 arg)
1040 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, arg);
1042 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set_raw);
1044 int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw,
1045 const struct mtk_pin_desc *desc, u32 *val)
1047 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, val);
1049 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get_raw);
1051 MODULE_LICENSE("GPL v2");
1052 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1053 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");