2 * Core pinctrl/GPIO driver for Intel GPIO controllers
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef PINCTRL_INTEL_H
14 #define PINCTRL_INTEL_H
16 struct pinctrl_pin_desc;
17 struct platform_device;
21 * struct intel_pingroup - Description about group of pins
22 * @name: Name of the groups
23 * @pins: All pins in this group
24 * @npins: Number of pins in this groups
25 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
27 * @modes: If not %NULL this will hold mode for each pin in @pins
29 struct intel_pingroup {
34 const unsigned *modes;
38 * struct intel_function - Description about a function
39 * @name: Name of the function
40 * @groups: An array of groups for this function
41 * @ngroups: Number of groups in @groups
43 struct intel_function {
45 const char * const *groups;
50 * struct intel_padgroup - Hardware pad group information
51 * @reg_num: GPI_IS register number
52 * @base: Starting pin of this group
53 * @size: Size of this group (maximum is 32).
54 * @padown_num: PAD_OWN register number (assigned by the core driver)
56 * If pad groups of a community are not the same size, use this structure
59 struct intel_padgroup {
67 * struct intel_community - Intel pin community description
68 * @barno: MMIO BAR number where registers for this community reside
69 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
70 * then there is no support for owner.
71 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
72 * locking is not supported.
73 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
74 * is assumed that the host owns the pin (rather than
76 * @ie_offset: Register offset of GPI_IE from @regs.
77 * @pin_base: Starting pin of pins in this community
78 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
79 * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
80 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
81 * minimum. Use %0 if the number of registers can be
82 * determined by the size of the group.
83 * @npins: Number of pins in this community
84 * @features: Additional features supported by the hardware
85 * @gpps: Pad groups if the controller has variable size pad groups
86 * @ngpps: Number of pad groups in this community
87 * @regs: Community specific common registers (reserved for core driver)
88 * @pad_regs: Community specific pad registers (reserved for core driver)
90 * Most Intel GPIO host controllers this driver supports each pad group is
91 * of equal size (except the last one). In that case the driver can just
92 * fill in @gpp_size field and let the core driver to handle the rest. If
93 * the controller has pad groups of variable size the client driver can
94 * pass custom @gpps and @ngpps instead.
96 struct intel_community {
98 unsigned padown_offset;
99 unsigned padcfglock_offset;
100 unsigned hostown_offset;
104 unsigned gpp_num_padown_regs;
107 const struct intel_padgroup *gpps;
109 /* Reserved for the core driver */
111 void __iomem *pad_regs;
114 /* Additional features supported by the hardware */
115 #define PINCTRL_FEATURE_DEBOUNCE BIT(0)
116 #define PINCTRL_FEATURE_1K_PD BIT(1)
119 * PIN_GROUP - Declare a pin group
120 * @n: Name of the group
121 * @p: An array of pins this group consists
122 * @m: Mode which the pins are put when this group is active. Can be either
123 * a single integer or an array of integers in which case mode is per
126 #define PIN_GROUP(n, p, m) \
130 .npins = ARRAY_SIZE((p)), \
131 .mode = __builtin_choose_expr( \
132 __builtin_constant_p((m)), (m), 0), \
133 .modes = __builtin_choose_expr( \
134 __builtin_constant_p((m)), NULL, (m)), \
137 #define FUNCTION(n, g) \
141 .ngroups = ARRAY_SIZE((g)), \
145 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
146 * @uid: ACPI _UID for the probe driver use if needed
147 * @pins: Array if pins this pinctrl controls
148 * @npins: Number of pins in the array
149 * @groups: Array of pin groups
150 * @ngroups: Number of groups in the array
151 * @functions: Array of functions
152 * @nfunctions: Number of functions in the array
153 * @communities: Array of communities this pinctrl handles
154 * @ncommunities: Number of communities in the array
156 * The @communities is used as a template by the core driver. It will make
157 * copy of all communities and fill in rest of the information.
159 struct intel_pinctrl_soc_data {
161 const struct pinctrl_pin_desc *pins;
163 const struct intel_pingroup *groups;
165 const struct intel_function *functions;
167 const struct intel_community *communities;
171 int intel_pinctrl_probe(struct platform_device *pdev,
172 const struct intel_pinctrl_soc_data *soc_data);
173 #ifdef CONFIG_PM_SLEEP
174 int intel_pinctrl_suspend(struct device *dev);
175 int intel_pinctrl_resume(struct device *dev);
178 #endif /* PINCTRL_INTEL_H */