1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/log2.h>
14 #include <linux/platform_device.h>
15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/pinctrl/pinmux.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
21 #include "pinctrl-intel.h"
23 /* Offset from regs */
25 #define REVID_SHIFT 16
26 #define REVID_MASK GENMASK(31, 16)
32 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
33 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
34 #define PADOWN_GPP(p) ((p) / 8)
36 /* Offset from pad_regs */
38 #define PADCFG0_RXEVCFG_SHIFT 25
39 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
40 #define PADCFG0_RXEVCFG_LEVEL 0
41 #define PADCFG0_RXEVCFG_EDGE 1
42 #define PADCFG0_RXEVCFG_DISABLED 2
43 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
44 #define PADCFG0_PREGFRXSEL BIT(24)
45 #define PADCFG0_RXINV BIT(23)
46 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
47 #define PADCFG0_GPIROUTSCI BIT(19)
48 #define PADCFG0_GPIROUTSMI BIT(18)
49 #define PADCFG0_GPIROUTNMI BIT(17)
50 #define PADCFG0_PMODE_SHIFT 10
51 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
52 #define PADCFG0_PMODE_GPIO 0
53 #define PADCFG0_GPIORXDIS BIT(9)
54 #define PADCFG0_GPIOTXDIS BIT(8)
55 #define PADCFG0_GPIORXSTATE BIT(1)
56 #define PADCFG0_GPIOTXSTATE BIT(0)
59 #define PADCFG1_TERM_UP BIT(13)
60 #define PADCFG1_TERM_SHIFT 10
61 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
62 #define PADCFG1_TERM_20K 4
63 #define PADCFG1_TERM_2K 3
64 #define PADCFG1_TERM_5K 2
65 #define PADCFG1_TERM_1K 1
68 #define PADCFG2_DEBEN BIT(0)
69 #define PADCFG2_DEBOUNCE_SHIFT 1
70 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
72 #define DEBOUNCE_PERIOD 31250 /* ns */
74 struct intel_pad_context {
80 struct intel_community_context {
84 struct intel_pinctrl_context {
85 struct intel_pad_context *pads;
86 struct intel_community_context *communities;
90 * struct intel_pinctrl - Intel pinctrl private structure
91 * @dev: Pointer to the device structure
92 * @lock: Lock to serialize register access
93 * @pctldesc: Pin controller description
94 * @pctldev: Pointer to the pin controller device
95 * @chip: GPIO chip in this pin controller
96 * @soc: SoC/PCH specific pin configuration data
97 * @communities: All communities in this pin controller
98 * @ncommunities: Number of communities in this pin controller
99 * @context: Configuration saved over system sleep
100 * @irq: pinctrl/GPIO chip irq number
102 struct intel_pinctrl {
105 struct pinctrl_desc pctldesc;
106 struct pinctrl_dev *pctldev;
107 struct gpio_chip chip;
108 const struct intel_pinctrl_soc_data *soc;
109 struct intel_community *communities;
111 struct intel_pinctrl_context context;
115 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
116 #define padgroup_offset(g, p) ((p) - (g)->base)
118 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
121 struct intel_community *community;
124 for (i = 0; i < pctrl->ncommunities; i++) {
125 community = &pctrl->communities[i];
126 if (pin >= community->pin_base &&
127 pin < community->pin_base + community->npins)
131 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
135 static const struct intel_padgroup *
136 intel_community_get_padgroup(const struct intel_community *community,
141 for (i = 0; i < community->ngpps; i++) {
142 const struct intel_padgroup *padgrp = &community->gpps[i];
144 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
151 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
152 unsigned int pin, unsigned int reg)
154 const struct intel_community *community;
158 community = intel_get_community(pctrl, pin);
162 padno = pin_to_padno(community, pin);
163 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
165 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
168 return community->pad_regs + reg + padno * nregs * 4;
171 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
173 const struct intel_community *community;
174 const struct intel_padgroup *padgrp;
175 unsigned int gpp, offset, gpp_offset;
176 void __iomem *padown;
178 community = intel_get_community(pctrl, pin);
181 if (!community->padown_offset)
184 padgrp = intel_community_get_padgroup(community, pin);
188 gpp_offset = padgroup_offset(padgrp, pin);
189 gpp = PADOWN_GPP(gpp_offset);
190 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
191 padown = community->regs + offset;
193 return !(readl(padown) & PADOWN_MASK(gpp_offset));
196 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
198 const struct intel_community *community;
199 const struct intel_padgroup *padgrp;
200 unsigned int offset, gpp_offset;
201 void __iomem *hostown;
203 community = intel_get_community(pctrl, pin);
206 if (!community->hostown_offset)
209 padgrp = intel_community_get_padgroup(community, pin);
213 gpp_offset = padgroup_offset(padgrp, pin);
214 offset = community->hostown_offset + padgrp->reg_num * 4;
215 hostown = community->regs + offset;
217 return !(readl(hostown) & BIT(gpp_offset));
220 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
222 struct intel_community *community;
223 const struct intel_padgroup *padgrp;
224 unsigned int offset, gpp_offset;
227 community = intel_get_community(pctrl, pin);
230 if (!community->padcfglock_offset)
233 padgrp = intel_community_get_padgroup(community, pin);
237 gpp_offset = padgroup_offset(padgrp, pin);
240 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
241 * the pad is considered unlocked. Any other case means that it is
242 * either fully or partially locked and we don't touch it.
244 offset = community->padcfglock_offset + padgrp->reg_num * 8;
245 value = readl(community->regs + offset);
246 if (value & BIT(gpp_offset))
249 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
250 value = readl(community->regs + offset);
251 if (value & BIT(gpp_offset))
257 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
259 return intel_pad_owned_by_host(pctrl, pin) &&
260 !intel_pad_locked(pctrl, pin);
263 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
265 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
267 return pctrl->soc->ngroups;
270 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
273 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
275 return pctrl->soc->groups[group].name;
278 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
279 const unsigned int **pins, unsigned int *npins)
281 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
283 *pins = pctrl->soc->groups[group].pins;
284 *npins = pctrl->soc->groups[group].npins;
288 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
291 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
292 void __iomem *padcfg;
293 u32 cfg0, cfg1, mode;
296 if (!intel_pad_owned_by_host(pctrl, pin)) {
297 seq_puts(s, "not available");
301 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
302 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
304 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
305 if (mode == PADCFG0_PMODE_GPIO)
306 seq_puts(s, "GPIO ");
308 seq_printf(s, "mode %d ", mode);
310 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
312 /* Dump the additional PADCFG registers if available */
313 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
315 seq_printf(s, " 0x%08x", readl(padcfg));
317 locked = intel_pad_locked(pctrl, pin);
318 acpi = intel_pad_acpi_mode(pctrl, pin);
320 if (locked || acpi) {
323 seq_puts(s, "LOCKED");
333 static const struct pinctrl_ops intel_pinctrl_ops = {
334 .get_groups_count = intel_get_groups_count,
335 .get_group_name = intel_get_group_name,
336 .get_group_pins = intel_get_group_pins,
337 .pin_dbg_show = intel_pin_dbg_show,
340 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
342 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
344 return pctrl->soc->nfunctions;
347 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
348 unsigned int function)
350 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
352 return pctrl->soc->functions[function].name;
355 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
356 unsigned int function,
357 const char * const **groups,
358 unsigned int * const ngroups)
360 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
362 *groups = pctrl->soc->functions[function].groups;
363 *ngroups = pctrl->soc->functions[function].ngroups;
367 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
368 unsigned int function, unsigned int group)
370 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
371 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
375 raw_spin_lock_irqsave(&pctrl->lock, flags);
378 * All pins in the groups needs to be accessible and writable
379 * before we can enable the mux for this group.
381 for (i = 0; i < grp->npins; i++) {
382 if (!intel_pad_usable(pctrl, grp->pins[i])) {
383 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
388 /* Now enable the mux setting for each pin in the group */
389 for (i = 0; i < grp->npins; i++) {
390 void __iomem *padcfg0;
393 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
394 value = readl(padcfg0);
396 value &= ~PADCFG0_PMODE_MASK;
399 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
401 value |= grp->mode << PADCFG0_PMODE_SHIFT;
403 writel(value, padcfg0);
406 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
411 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
415 value = readl(padcfg0);
417 value &= ~PADCFG0_GPIORXDIS;
418 value |= PADCFG0_GPIOTXDIS;
420 value &= ~PADCFG0_GPIOTXDIS;
421 value |= PADCFG0_GPIORXDIS;
423 writel(value, padcfg0);
426 static int __intel_gpio_get_gpio_mode(u32 value)
428 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
431 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
433 return __intel_gpio_get_gpio_mode(readl(padcfg0));
436 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
440 /* Put the pad into GPIO mode */
441 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
442 /* Disable SCI/SMI/NMI generation */
443 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
444 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
445 writel(value, padcfg0);
448 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
449 struct pinctrl_gpio_range *range,
452 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
453 void __iomem *padcfg0;
456 raw_spin_lock_irqsave(&pctrl->lock, flags);
458 if (!intel_pad_usable(pctrl, pin)) {
459 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
463 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
466 * If pin is already configured in GPIO mode, we assume that
467 * firmware provides correct settings. In such case we avoid
468 * potential glitches on the pin. Otherwise, for the pin in
469 * alternative mode, consumer has to supply respective flags.
471 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
472 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
476 intel_gpio_set_gpio_mode(padcfg0);
478 /* Disable TX buffer and enable RX (this will be input) */
479 __intel_gpio_set_direction(padcfg0, true);
481 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
486 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
487 struct pinctrl_gpio_range *range,
488 unsigned int pin, bool input)
490 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
491 void __iomem *padcfg0;
494 raw_spin_lock_irqsave(&pctrl->lock, flags);
496 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
497 __intel_gpio_set_direction(padcfg0, input);
499 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
504 static const struct pinmux_ops intel_pinmux_ops = {
505 .get_functions_count = intel_get_functions_count,
506 .get_function_name = intel_get_function_name,
507 .get_function_groups = intel_get_function_groups,
508 .set_mux = intel_pinmux_set_mux,
509 .gpio_request_enable = intel_gpio_request_enable,
510 .gpio_set_direction = intel_gpio_set_direction,
513 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
514 unsigned long *config)
516 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
517 enum pin_config_param param = pinconf_to_config_param(*config);
518 const struct intel_community *community;
522 if (!intel_pad_owned_by_host(pctrl, pin))
525 community = intel_get_community(pctrl, pin);
526 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
527 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
530 case PIN_CONFIG_BIAS_DISABLE:
535 case PIN_CONFIG_BIAS_PULL_UP:
536 if (!term || !(value & PADCFG1_TERM_UP))
540 case PADCFG1_TERM_1K:
543 case PADCFG1_TERM_2K:
546 case PADCFG1_TERM_5K:
549 case PADCFG1_TERM_20K:
556 case PIN_CONFIG_BIAS_PULL_DOWN:
557 if (!term || value & PADCFG1_TERM_UP)
561 case PADCFG1_TERM_1K:
562 if (!(community->features & PINCTRL_FEATURE_1K_PD))
566 case PADCFG1_TERM_5K:
569 case PADCFG1_TERM_20K:
576 case PIN_CONFIG_INPUT_DEBOUNCE: {
577 void __iomem *padcfg2;
580 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
585 if (!(v & PADCFG2_DEBEN))
588 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
589 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
598 *config = pinconf_to_config_packed(param, arg);
602 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
603 unsigned long config)
605 unsigned int param = pinconf_to_config_param(config);
606 unsigned int arg = pinconf_to_config_argument(config);
607 const struct intel_community *community;
608 void __iomem *padcfg1;
613 raw_spin_lock_irqsave(&pctrl->lock, flags);
615 community = intel_get_community(pctrl, pin);
616 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
617 value = readl(padcfg1);
620 case PIN_CONFIG_BIAS_DISABLE:
621 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
624 case PIN_CONFIG_BIAS_PULL_UP:
625 value &= ~PADCFG1_TERM_MASK;
627 value |= PADCFG1_TERM_UP;
629 /* Set default strength value in case none is given */
635 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
638 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
641 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
644 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
652 case PIN_CONFIG_BIAS_PULL_DOWN:
653 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
655 /* Set default strength value in case none is given */
661 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
664 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
667 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
671 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
681 writel(value, padcfg1);
683 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
688 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
689 unsigned int pin, unsigned int debounce)
691 void __iomem *padcfg0, *padcfg2;
696 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
700 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
702 raw_spin_lock_irqsave(&pctrl->lock, flags);
704 value0 = readl(padcfg0);
705 value2 = readl(padcfg2);
707 /* Disable glitch filter and debouncer */
708 value0 &= ~PADCFG0_PREGFRXSEL;
709 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
714 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
715 if (v < 3 || v > 15) {
719 /* Enable glitch filter and debouncer */
720 value0 |= PADCFG0_PREGFRXSEL;
721 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
722 value2 |= PADCFG2_DEBEN;
726 writel(value0, padcfg0);
727 writel(value2, padcfg2);
730 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
735 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
736 unsigned long *configs, unsigned int nconfigs)
738 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
741 if (!intel_pad_usable(pctrl, pin))
744 for (i = 0; i < nconfigs; i++) {
745 switch (pinconf_to_config_param(configs[i])) {
746 case PIN_CONFIG_BIAS_DISABLE:
747 case PIN_CONFIG_BIAS_PULL_UP:
748 case PIN_CONFIG_BIAS_PULL_DOWN:
749 ret = intel_config_set_pull(pctrl, pin, configs[i]);
754 case PIN_CONFIG_INPUT_DEBOUNCE:
755 ret = intel_config_set_debounce(pctrl, pin,
756 pinconf_to_config_argument(configs[i]));
769 static const struct pinconf_ops intel_pinconf_ops = {
771 .pin_config_get = intel_config_get,
772 .pin_config_set = intel_config_set,
775 static const struct pinctrl_desc intel_pinctrl_desc = {
776 .pctlops = &intel_pinctrl_ops,
777 .pmxops = &intel_pinmux_ops,
778 .confops = &intel_pinconf_ops,
779 .owner = THIS_MODULE,
783 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
784 * @pctrl: Pinctrl structure
785 * @offset: GPIO offset from gpiolib
786 * @commmunity: Community is filled here if not %NULL
787 * @padgrp: Pad group is filled here if not %NULL
789 * When coming through gpiolib irqchip, the GPIO offset is not
790 * automatically translated to pinctrl pin number. This function can be
791 * used to find out the corresponding pinctrl pin.
793 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
794 const struct intel_community **community,
795 const struct intel_padgroup **padgrp)
799 for (i = 0; i < pctrl->ncommunities; i++) {
800 const struct intel_community *comm = &pctrl->communities[i];
803 for (j = 0; j < comm->ngpps; j++) {
804 const struct intel_padgroup *pgrp = &comm->gpps[j];
806 if (pgrp->gpio_base < 0)
809 if (offset >= pgrp->gpio_base &&
810 offset < pgrp->gpio_base + pgrp->size) {
813 pin = pgrp->base + offset - pgrp->gpio_base;
827 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
829 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
834 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
838 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
842 padcfg0 = readl(reg);
843 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
844 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
846 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
849 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
852 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
858 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
862 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
866 raw_spin_lock_irqsave(&pctrl->lock, flags);
867 padcfg0 = readl(reg);
869 padcfg0 |= PADCFG0_GPIOTXSTATE;
871 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
872 writel(padcfg0, reg);
873 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
876 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
878 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
883 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
887 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
891 padcfg0 = readl(reg);
893 if (padcfg0 & PADCFG0_PMODE_MASK)
896 return !!(padcfg0 & PADCFG0_GPIOTXDIS);
899 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
901 return pinctrl_gpio_direction_input(chip->base + offset);
904 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
907 intel_gpio_set(chip, offset, value);
908 return pinctrl_gpio_direction_output(chip->base + offset);
911 static const struct gpio_chip intel_gpio_chip = {
912 .owner = THIS_MODULE,
913 .request = gpiochip_generic_request,
914 .free = gpiochip_generic_free,
915 .get_direction = intel_gpio_get_direction,
916 .direction_input = intel_gpio_direction_input,
917 .direction_output = intel_gpio_direction_output,
918 .get = intel_gpio_get,
919 .set = intel_gpio_set,
920 .set_config = gpiochip_generic_config,
923 static void intel_gpio_irq_ack(struct irq_data *d)
925 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
926 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
927 const struct intel_community *community;
928 const struct intel_padgroup *padgrp;
931 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
933 unsigned int gpp, gpp_offset, is_offset;
935 gpp = padgrp->reg_num;
936 gpp_offset = padgroup_offset(padgrp, pin);
937 is_offset = community->is_offset + gpp * 4;
939 raw_spin_lock(&pctrl->lock);
940 writel(BIT(gpp_offset), community->regs + is_offset);
941 raw_spin_unlock(&pctrl->lock);
945 static void intel_gpio_irq_enable(struct irq_data *d)
947 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
948 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
949 const struct intel_community *community;
950 const struct intel_padgroup *padgrp;
953 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
955 unsigned int gpp, gpp_offset, is_offset;
959 gpp = padgrp->reg_num;
960 gpp_offset = padgroup_offset(padgrp, pin);
961 is_offset = community->is_offset + gpp * 4;
963 raw_spin_lock_irqsave(&pctrl->lock, flags);
964 /* Clear interrupt status first to avoid unexpected interrupt */
965 writel(BIT(gpp_offset), community->regs + is_offset);
967 value = readl(community->regs + community->ie_offset + gpp * 4);
968 value |= BIT(gpp_offset);
969 writel(value, community->regs + community->ie_offset + gpp * 4);
970 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
974 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
976 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
977 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
978 const struct intel_community *community;
979 const struct intel_padgroup *padgrp;
982 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
984 unsigned int gpp, gpp_offset;
989 gpp = padgrp->reg_num;
990 gpp_offset = padgroup_offset(padgrp, pin);
992 reg = community->regs + community->ie_offset + gpp * 4;
994 raw_spin_lock_irqsave(&pctrl->lock, flags);
997 value &= ~BIT(gpp_offset);
999 value |= BIT(gpp_offset);
1001 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1005 static void intel_gpio_irq_mask(struct irq_data *d)
1007 intel_gpio_irq_mask_unmask(d, true);
1010 static void intel_gpio_irq_unmask(struct irq_data *d)
1012 intel_gpio_irq_mask_unmask(d, false);
1015 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1017 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1018 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1019 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1020 unsigned long flags;
1024 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1029 * If the pin is in ACPI mode it is still usable as a GPIO but it
1030 * cannot be used as IRQ because GPI_IS status bit will not be
1031 * updated by the host controller hardware.
1033 if (intel_pad_acpi_mode(pctrl, pin)) {
1034 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1038 raw_spin_lock_irqsave(&pctrl->lock, flags);
1040 intel_gpio_set_gpio_mode(reg);
1044 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1046 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1047 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1048 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1049 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1050 value |= PADCFG0_RXINV;
1051 } else if (type & IRQ_TYPE_EDGE_RISING) {
1052 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1053 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1054 if (type & IRQ_TYPE_LEVEL_LOW)
1055 value |= PADCFG0_RXINV;
1057 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1062 if (type & IRQ_TYPE_EDGE_BOTH)
1063 irq_set_handler_locked(d, handle_edge_irq);
1064 else if (type & IRQ_TYPE_LEVEL_MASK)
1065 irq_set_handler_locked(d, handle_level_irq);
1067 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1072 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1074 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1075 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1076 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1079 enable_irq_wake(pctrl->irq);
1081 disable_irq_wake(pctrl->irq);
1083 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1087 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1088 const struct intel_community *community)
1090 struct gpio_chip *gc = &pctrl->chip;
1091 irqreturn_t ret = IRQ_NONE;
1094 for (gpp = 0; gpp < community->ngpps; gpp++) {
1095 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1096 unsigned long pending, enabled, gpp_offset;
1098 pending = readl(community->regs + community->is_offset +
1099 padgrp->reg_num * 4);
1100 enabled = readl(community->regs + community->ie_offset +
1101 padgrp->reg_num * 4);
1103 /* Only interrupts that are enabled */
1106 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1109 irq = irq_find_mapping(gc->irq.domain,
1110 padgrp->gpio_base + gpp_offset);
1111 generic_handle_irq(irq);
1120 static irqreturn_t intel_gpio_irq(int irq, void *data)
1122 const struct intel_community *community;
1123 struct intel_pinctrl *pctrl = data;
1124 irqreturn_t ret = IRQ_NONE;
1127 /* Need to check all communities for pending interrupts */
1128 for (i = 0; i < pctrl->ncommunities; i++) {
1129 community = &pctrl->communities[i];
1130 ret |= intel_gpio_community_irq_handler(pctrl, community);
1136 static struct irq_chip intel_gpio_irqchip = {
1137 .name = "intel-gpio",
1138 .irq_enable = intel_gpio_irq_enable,
1139 .irq_ack = intel_gpio_irq_ack,
1140 .irq_mask = intel_gpio_irq_mask,
1141 .irq_unmask = intel_gpio_irq_unmask,
1142 .irq_set_type = intel_gpio_irq_type,
1143 .irq_set_wake = intel_gpio_irq_wake,
1144 .flags = IRQCHIP_MASK_ON_SUSPEND,
1147 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1148 const struct intel_community *community)
1152 for (i = 0; i < community->ngpps; i++) {
1153 const struct intel_padgroup *gpp = &community->gpps[i];
1155 if (gpp->gpio_base < 0)
1158 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1159 gpp->gpio_base, gpp->base,
1168 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1170 const struct intel_community *community;
1171 unsigned int ngpio = 0;
1174 for (i = 0; i < pctrl->ncommunities; i++) {
1175 community = &pctrl->communities[i];
1176 for (j = 0; j < community->ngpps; j++) {
1177 const struct intel_padgroup *gpp = &community->gpps[j];
1179 if (gpp->gpio_base < 0)
1182 if (gpp->gpio_base + gpp->size > ngpio)
1183 ngpio = gpp->gpio_base + gpp->size;
1190 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1194 pctrl->chip = intel_gpio_chip;
1196 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1197 pctrl->chip.label = dev_name(pctrl->dev);
1198 pctrl->chip.parent = pctrl->dev;
1199 pctrl->chip.base = -1;
1202 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1204 dev_err(pctrl->dev, "failed to register gpiochip\n");
1208 for (i = 0; i < pctrl->ncommunities; i++) {
1209 struct intel_community *community = &pctrl->communities[i];
1211 ret = intel_gpio_add_pin_ranges(pctrl, community);
1213 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1219 * We need to request the interrupt here (instead of providing chip
1220 * to the irq directly) because on some platforms several GPIO
1221 * controllers share the same interrupt line.
1223 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1224 IRQF_SHARED | IRQF_NO_THREAD,
1225 dev_name(pctrl->dev), pctrl);
1227 dev_err(pctrl->dev, "failed to request interrupt\n");
1231 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1232 handle_bad_irq, IRQ_TYPE_NONE);
1234 dev_err(pctrl->dev, "failed to add irqchip\n");
1238 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1243 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1244 struct intel_community *community)
1246 struct intel_padgroup *gpps;
1247 unsigned int npins = community->npins;
1248 unsigned int padown_num = 0;
1251 if (community->gpps)
1252 ngpps = community->ngpps;
1254 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1256 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1260 for (i = 0; i < ngpps; i++) {
1261 if (community->gpps) {
1262 gpps[i] = community->gpps[i];
1264 unsigned int gpp_size = community->gpp_size;
1266 gpps[i].reg_num = i;
1267 gpps[i].base = community->pin_base + i * gpp_size;
1268 gpps[i].size = min(gpp_size, npins);
1269 npins -= gpps[i].size;
1272 if (gpps[i].size > 32)
1275 if (!gpps[i].gpio_base)
1276 gpps[i].gpio_base = gpps[i].base;
1278 gpps[i].padown_num = padown_num;
1281 * In older hardware the number of padown registers per
1282 * group is fixed regardless of the group size.
1284 if (community->gpp_num_padown_regs)
1285 padown_num += community->gpp_num_padown_regs;
1287 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1290 community->ngpps = ngpps;
1291 community->gpps = gpps;
1296 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1298 #ifdef CONFIG_PM_SLEEP
1299 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1300 struct intel_community_context *communities;
1301 struct intel_pad_context *pads;
1304 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1308 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1309 sizeof(*communities), GFP_KERNEL);
1314 for (i = 0; i < pctrl->ncommunities; i++) {
1315 struct intel_community *community = &pctrl->communities[i];
1318 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1319 sizeof(*intmask), GFP_KERNEL);
1323 communities[i].intmask = intmask;
1326 pctrl->context.pads = pads;
1327 pctrl->context.communities = communities;
1333 int intel_pinctrl_probe(struct platform_device *pdev,
1334 const struct intel_pinctrl_soc_data *soc_data)
1336 struct intel_pinctrl *pctrl;
1342 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1346 pctrl->dev = &pdev->dev;
1347 pctrl->soc = soc_data;
1348 raw_spin_lock_init(&pctrl->lock);
1351 * Make a copy of the communities which we can use to hold pointers
1354 pctrl->ncommunities = pctrl->soc->ncommunities;
1355 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1356 sizeof(*pctrl->communities), GFP_KERNEL);
1357 if (!pctrl->communities)
1360 for (i = 0; i < pctrl->ncommunities; i++) {
1361 struct intel_community *community = &pctrl->communities[i];
1362 struct resource *res;
1366 *community = pctrl->soc->communities[i];
1368 res = platform_get_resource(pdev, IORESOURCE_MEM,
1370 regs = devm_ioremap_resource(&pdev->dev, res);
1372 return PTR_ERR(regs);
1375 * Determine community features based on the revision if
1376 * not specified already.
1378 if (!community->features) {
1381 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1383 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1384 community->features |= PINCTRL_FEATURE_1K_PD;
1388 /* Read offset of the pad configuration registers */
1389 padbar = readl(regs + PADBAR);
1391 community->regs = regs;
1392 community->pad_regs = regs + padbar;
1394 if (!community->is_offset)
1395 community->is_offset = GPI_IS;
1397 ret = intel_pinctrl_add_padgroups(pctrl, community);
1402 irq = platform_get_irq(pdev, 0);
1404 dev_err(&pdev->dev, "failed to get interrupt number\n");
1408 ret = intel_pinctrl_pm_init(pctrl);
1412 pctrl->pctldesc = intel_pinctrl_desc;
1413 pctrl->pctldesc.name = dev_name(&pdev->dev);
1414 pctrl->pctldesc.pins = pctrl->soc->pins;
1415 pctrl->pctldesc.npins = pctrl->soc->npins;
1417 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1419 if (IS_ERR(pctrl->pctldev)) {
1420 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1421 return PTR_ERR(pctrl->pctldev);
1424 ret = intel_gpio_probe(pctrl, irq);
1428 platform_set_drvdata(pdev, pctrl);
1432 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1434 #ifdef CONFIG_PM_SLEEP
1435 static bool __intel_gpio_is_direct_irq(u32 value)
1437 return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1438 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1441 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1443 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1446 if (!pd || !intel_pad_usable(pctrl, pin))
1450 * Only restore the pin if it is actually in use by the kernel (or
1451 * by userspace). It is possible that some pins are used by the
1452 * BIOS during resume and those are not always locked down so leave
1455 if (pd->mux_owner || pd->gpio_owner ||
1456 gpiochip_line_is_irq(&pctrl->chip, pin))
1460 * The firmware on some systems may configure GPIO pins to be
1461 * an interrupt source in so called "direct IRQ" mode. In such
1462 * cases the GPIO controller driver has no idea if those pins
1463 * are being used or not. At the same time, there is a known bug
1464 * in the firmwares that don't restore the pin settings correctly
1465 * after suspend, i.e. by an unknown reason the Rx value becomes
1468 * Hence, let's save and restore the pins that are configured
1469 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1471 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1473 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1474 if (__intel_gpio_is_direct_irq(value))
1480 int intel_pinctrl_suspend(struct device *dev)
1482 struct platform_device *pdev = to_platform_device(dev);
1483 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1484 struct intel_community_context *communities;
1485 struct intel_pad_context *pads;
1488 pads = pctrl->context.pads;
1489 for (i = 0; i < pctrl->soc->npins; i++) {
1490 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1491 void __iomem *padcfg;
1494 if (!intel_pinctrl_should_save(pctrl, desc->number))
1497 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1498 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1499 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1500 pads[i].padcfg1 = val;
1502 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1504 pads[i].padcfg2 = readl(padcfg);
1507 communities = pctrl->context.communities;
1508 for (i = 0; i < pctrl->ncommunities; i++) {
1509 struct intel_community *community = &pctrl->communities[i];
1513 base = community->regs + community->ie_offset;
1514 for (gpp = 0; gpp < community->ngpps; gpp++)
1515 communities[i].intmask[gpp] = readl(base + gpp * 4);
1520 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1522 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1526 for (i = 0; i < pctrl->ncommunities; i++) {
1527 const struct intel_community *community;
1531 community = &pctrl->communities[i];
1532 base = community->regs;
1534 for (gpp = 0; gpp < community->ngpps; gpp++) {
1535 /* Mask and clear all interrupts */
1536 writel(0, base + community->ie_offset + gpp * 4);
1537 writel(0xffff, base + community->is_offset + gpp * 4);
1542 int intel_pinctrl_resume(struct device *dev)
1544 struct platform_device *pdev = to_platform_device(dev);
1545 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1546 const struct intel_community_context *communities;
1547 const struct intel_pad_context *pads;
1550 /* Mask all interrupts */
1551 intel_gpio_irq_init(pctrl);
1553 pads = pctrl->context.pads;
1554 for (i = 0; i < pctrl->soc->npins; i++) {
1555 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1556 void __iomem *padcfg;
1559 if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1561 * If the firmware mangled the register contents too much,
1562 * check the saved value for the Direct IRQ mode.
1564 __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1567 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1568 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1569 if (val != pads[i].padcfg0) {
1570 writel(pads[i].padcfg0, padcfg);
1571 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1572 desc->number, readl(padcfg));
1575 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1576 val = readl(padcfg);
1577 if (val != pads[i].padcfg1) {
1578 writel(pads[i].padcfg1, padcfg);
1579 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1580 desc->number, readl(padcfg));
1583 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1585 val = readl(padcfg);
1586 if (val != pads[i].padcfg2) {
1587 writel(pads[i].padcfg2, padcfg);
1588 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1589 desc->number, readl(padcfg));
1594 communities = pctrl->context.communities;
1595 for (i = 0; i < pctrl->ncommunities; i++) {
1596 struct intel_community *community = &pctrl->communities[i];
1600 base = community->regs + community->ie_offset;
1601 for (gpp = 0; gpp < community->ngpps; gpp++) {
1602 writel(communities[i].intmask[gpp], base + gpp * 4);
1603 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1604 readl(base + gpp * 4));
1610 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1613 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1614 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1615 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1616 MODULE_LICENSE("GPL v2");