2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/log2.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-intel.h"
26 /* Offset from regs */
28 #define REVID_SHIFT 16
29 #define REVID_MASK GENMASK(31, 16)
33 #define GPI_GPE_STS 0x140
34 #define GPI_GPE_EN 0x160
37 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
38 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
39 #define PADOWN_GPP(p) ((p) / 8)
41 /* Offset from pad_regs */
43 #define PADCFG0_RXEVCFG_SHIFT 25
44 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
45 #define PADCFG0_RXEVCFG_LEVEL 0
46 #define PADCFG0_RXEVCFG_EDGE 1
47 #define PADCFG0_RXEVCFG_DISABLED 2
48 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
49 #define PADCFG0_PREGFRXSEL BIT(24)
50 #define PADCFG0_RXINV BIT(23)
51 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
52 #define PADCFG0_GPIROUTSCI BIT(19)
53 #define PADCFG0_GPIROUTSMI BIT(18)
54 #define PADCFG0_GPIROUTNMI BIT(17)
55 #define PADCFG0_PMODE_SHIFT 10
56 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
57 #define PADCFG0_GPIORXDIS BIT(9)
58 #define PADCFG0_GPIOTXDIS BIT(8)
59 #define PADCFG0_GPIORXSTATE BIT(1)
60 #define PADCFG0_GPIOTXSTATE BIT(0)
63 #define PADCFG1_TERM_UP BIT(13)
64 #define PADCFG1_TERM_SHIFT 10
65 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
66 #define PADCFG1_TERM_20K 4
67 #define PADCFG1_TERM_2K 3
68 #define PADCFG1_TERM_5K 2
69 #define PADCFG1_TERM_1K 1
72 #define PADCFG2_DEBEN BIT(0)
73 #define PADCFG2_DEBOUNCE_SHIFT 1
74 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
76 #define DEBOUNCE_PERIOD 31250 /* ns */
78 struct intel_pad_context {
84 struct intel_community_context {
88 struct intel_pinctrl_context {
89 struct intel_pad_context *pads;
90 struct intel_community_context *communities;
94 * struct intel_pinctrl - Intel pinctrl private structure
95 * @dev: Pointer to the device structure
96 * @lock: Lock to serialize register access
97 * @pctldesc: Pin controller description
98 * @pctldev: Pointer to the pin controller device
99 * @chip: GPIO chip in this pin controller
100 * @soc: SoC/PCH specific pin configuration data
101 * @communities: All communities in this pin controller
102 * @ncommunities: Number of communities in this pin controller
103 * @context: Configuration saved over system sleep
104 * @irq: pinctrl/GPIO chip irq number
106 struct intel_pinctrl {
109 struct pinctrl_desc pctldesc;
110 struct pinctrl_dev *pctldev;
111 struct gpio_chip chip;
112 const struct intel_pinctrl_soc_data *soc;
113 struct intel_community *communities;
115 struct intel_pinctrl_context context;
119 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
120 #define padgroup_offset(g, p) ((p) - (g)->base)
122 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
125 struct intel_community *community;
128 for (i = 0; i < pctrl->ncommunities; i++) {
129 community = &pctrl->communities[i];
130 if (pin >= community->pin_base &&
131 pin < community->pin_base + community->npins)
135 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
139 static const struct intel_padgroup *
140 intel_community_get_padgroup(const struct intel_community *community,
145 for (i = 0; i < community->ngpps; i++) {
146 const struct intel_padgroup *padgrp = &community->gpps[i];
148 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
155 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
158 const struct intel_community *community;
162 community = intel_get_community(pctrl, pin);
166 padno = pin_to_padno(community, pin);
167 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
169 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
172 return community->pad_regs + reg + padno * nregs * 4;
175 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
177 const struct intel_community *community;
178 const struct intel_padgroup *padgrp;
179 unsigned gpp, offset, gpp_offset;
180 void __iomem *padown;
182 community = intel_get_community(pctrl, pin);
185 if (!community->padown_offset)
188 padgrp = intel_community_get_padgroup(community, pin);
192 gpp_offset = padgroup_offset(padgrp, pin);
193 gpp = PADOWN_GPP(gpp_offset);
194 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
195 padown = community->regs + offset;
197 return !(readl(padown) & PADOWN_MASK(gpp_offset));
200 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
202 const struct intel_community *community;
203 const struct intel_padgroup *padgrp;
204 unsigned offset, gpp_offset;
205 void __iomem *hostown;
207 community = intel_get_community(pctrl, pin);
210 if (!community->hostown_offset)
213 padgrp = intel_community_get_padgroup(community, pin);
217 gpp_offset = padgroup_offset(padgrp, pin);
218 offset = community->hostown_offset + padgrp->reg_num * 4;
219 hostown = community->regs + offset;
221 return !(readl(hostown) & BIT(gpp_offset));
224 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
226 struct intel_community *community;
227 const struct intel_padgroup *padgrp;
228 unsigned offset, gpp_offset;
231 community = intel_get_community(pctrl, pin);
234 if (!community->padcfglock_offset)
237 padgrp = intel_community_get_padgroup(community, pin);
241 gpp_offset = padgroup_offset(padgrp, pin);
244 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
245 * the pad is considered unlocked. Any other case means that it is
246 * either fully or partially locked and we don't touch it.
248 offset = community->padcfglock_offset + padgrp->reg_num * 8;
249 value = readl(community->regs + offset);
250 if (value & BIT(gpp_offset))
253 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
254 value = readl(community->regs + offset);
255 if (value & BIT(gpp_offset))
261 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
263 return intel_pad_owned_by_host(pctrl, pin) &&
264 !intel_pad_locked(pctrl, pin);
267 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
269 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
271 return pctrl->soc->ngroups;
274 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
277 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
279 return pctrl->soc->groups[group].name;
282 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
283 const unsigned **pins, unsigned *npins)
285 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
287 *pins = pctrl->soc->groups[group].pins;
288 *npins = pctrl->soc->groups[group].npins;
292 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
295 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
296 void __iomem *padcfg;
297 u32 cfg0, cfg1, mode;
300 if (!intel_pad_owned_by_host(pctrl, pin)) {
301 seq_puts(s, "not available");
305 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
306 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
308 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
310 seq_puts(s, "GPIO ");
312 seq_printf(s, "mode %d ", mode);
314 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
316 /* Dump the additional PADCFG registers if available */
317 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
319 seq_printf(s, " 0x%08x", readl(padcfg));
321 locked = intel_pad_locked(pctrl, pin);
322 acpi = intel_pad_acpi_mode(pctrl, pin);
324 if (locked || acpi) {
327 seq_puts(s, "LOCKED");
337 static const struct pinctrl_ops intel_pinctrl_ops = {
338 .get_groups_count = intel_get_groups_count,
339 .get_group_name = intel_get_group_name,
340 .get_group_pins = intel_get_group_pins,
341 .pin_dbg_show = intel_pin_dbg_show,
344 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
346 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
348 return pctrl->soc->nfunctions;
351 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
354 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
356 return pctrl->soc->functions[function].name;
359 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
361 const char * const **groups,
362 unsigned * const ngroups)
364 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
366 *groups = pctrl->soc->functions[function].groups;
367 *ngroups = pctrl->soc->functions[function].ngroups;
371 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
374 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
375 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
379 raw_spin_lock_irqsave(&pctrl->lock, flags);
382 * All pins in the groups needs to be accessible and writable
383 * before we can enable the mux for this group.
385 for (i = 0; i < grp->npins; i++) {
386 if (!intel_pad_usable(pctrl, grp->pins[i])) {
387 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
392 /* Now enable the mux setting for each pin in the group */
393 for (i = 0; i < grp->npins; i++) {
394 void __iomem *padcfg0;
397 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
398 value = readl(padcfg0);
400 value &= ~PADCFG0_PMODE_MASK;
403 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
405 value |= grp->mode << PADCFG0_PMODE_SHIFT;
407 writel(value, padcfg0);
410 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
415 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
419 value = readl(padcfg0);
421 value &= ~PADCFG0_GPIORXDIS;
422 value |= PADCFG0_GPIOTXDIS;
424 value &= ~PADCFG0_GPIOTXDIS;
425 value |= PADCFG0_GPIORXDIS;
427 writel(value, padcfg0);
430 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
431 struct pinctrl_gpio_range *range,
434 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
435 void __iomem *padcfg0;
439 raw_spin_lock_irqsave(&pctrl->lock, flags);
441 if (!intel_pad_usable(pctrl, pin)) {
442 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
446 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
447 /* Put the pad into GPIO mode */
448 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
449 /* Disable SCI/SMI/NMI generation */
450 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
451 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
452 writel(value, padcfg0);
454 /* Disable TX buffer and enable RX (this will be input) */
455 __intel_gpio_set_direction(padcfg0, true);
457 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
462 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
463 struct pinctrl_gpio_range *range,
464 unsigned pin, bool input)
466 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
467 void __iomem *padcfg0;
470 raw_spin_lock_irqsave(&pctrl->lock, flags);
472 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
473 __intel_gpio_set_direction(padcfg0, input);
475 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
480 static const struct pinmux_ops intel_pinmux_ops = {
481 .get_functions_count = intel_get_functions_count,
482 .get_function_name = intel_get_function_name,
483 .get_function_groups = intel_get_function_groups,
484 .set_mux = intel_pinmux_set_mux,
485 .gpio_request_enable = intel_gpio_request_enable,
486 .gpio_set_direction = intel_gpio_set_direction,
489 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
490 unsigned long *config)
492 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
493 enum pin_config_param param = pinconf_to_config_param(*config);
494 const struct intel_community *community;
498 if (!intel_pad_owned_by_host(pctrl, pin))
501 community = intel_get_community(pctrl, pin);
502 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
503 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
506 case PIN_CONFIG_BIAS_DISABLE:
511 case PIN_CONFIG_BIAS_PULL_UP:
512 if (!term || !(value & PADCFG1_TERM_UP))
516 case PADCFG1_TERM_1K:
519 case PADCFG1_TERM_2K:
522 case PADCFG1_TERM_5K:
525 case PADCFG1_TERM_20K:
532 case PIN_CONFIG_BIAS_PULL_DOWN:
533 if (!term || value & PADCFG1_TERM_UP)
537 case PADCFG1_TERM_1K:
538 if (!(community->features & PINCTRL_FEATURE_1K_PD))
542 case PADCFG1_TERM_5K:
545 case PADCFG1_TERM_20K:
552 case PIN_CONFIG_INPUT_DEBOUNCE: {
553 void __iomem *padcfg2;
556 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
561 if (!(v & PADCFG2_DEBEN))
564 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
565 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
574 *config = pinconf_to_config_packed(param, arg);
578 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
579 unsigned long config)
581 unsigned param = pinconf_to_config_param(config);
582 unsigned arg = pinconf_to_config_argument(config);
583 const struct intel_community *community;
584 void __iomem *padcfg1;
589 raw_spin_lock_irqsave(&pctrl->lock, flags);
591 community = intel_get_community(pctrl, pin);
592 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
593 value = readl(padcfg1);
596 case PIN_CONFIG_BIAS_DISABLE:
597 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
600 case PIN_CONFIG_BIAS_PULL_UP:
601 value &= ~PADCFG1_TERM_MASK;
603 value |= PADCFG1_TERM_UP;
605 /* Set default strength value in case none is given */
611 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
614 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
617 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
620 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
628 case PIN_CONFIG_BIAS_PULL_DOWN:
629 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
631 /* Set default strength value in case none is given */
637 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
640 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
643 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
647 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
657 writel(value, padcfg1);
659 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
664 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
667 void __iomem *padcfg0, *padcfg2;
672 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
676 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
678 raw_spin_lock_irqsave(&pctrl->lock, flags);
680 value0 = readl(padcfg0);
681 value2 = readl(padcfg2);
683 /* Disable glitch filter and debouncer */
684 value0 &= ~PADCFG0_PREGFRXSEL;
685 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
690 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
691 if (v < 3 || v > 15) {
695 /* Enable glitch filter and debouncer */
696 value0 |= PADCFG0_PREGFRXSEL;
697 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
698 value2 |= PADCFG2_DEBEN;
702 writel(value0, padcfg0);
703 writel(value2, padcfg2);
706 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
711 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
712 unsigned long *configs, unsigned nconfigs)
714 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
717 if (!intel_pad_usable(pctrl, pin))
720 for (i = 0; i < nconfigs; i++) {
721 switch (pinconf_to_config_param(configs[i])) {
722 case PIN_CONFIG_BIAS_DISABLE:
723 case PIN_CONFIG_BIAS_PULL_UP:
724 case PIN_CONFIG_BIAS_PULL_DOWN:
725 ret = intel_config_set_pull(pctrl, pin, configs[i]);
730 case PIN_CONFIG_INPUT_DEBOUNCE:
731 ret = intel_config_set_debounce(pctrl, pin,
732 pinconf_to_config_argument(configs[i]));
745 static const struct pinconf_ops intel_pinconf_ops = {
747 .pin_config_get = intel_config_get,
748 .pin_config_set = intel_config_set,
751 static const struct pinctrl_desc intel_pinctrl_desc = {
752 .pctlops = &intel_pinctrl_ops,
753 .pmxops = &intel_pinmux_ops,
754 .confops = &intel_pinconf_ops,
755 .owner = THIS_MODULE,
758 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
760 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
764 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
768 padcfg0 = readl(reg);
769 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
770 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
772 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
775 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
777 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
782 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
786 raw_spin_lock_irqsave(&pctrl->lock, flags);
787 padcfg0 = readl(reg);
789 padcfg0 |= PADCFG0_GPIOTXSTATE;
791 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
792 writel(padcfg0, reg);
793 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
796 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
798 return pinctrl_gpio_direction_input(chip->base + offset);
801 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
804 intel_gpio_set(chip, offset, value);
805 return pinctrl_gpio_direction_output(chip->base + offset);
808 static const struct gpio_chip intel_gpio_chip = {
809 .owner = THIS_MODULE,
810 .request = gpiochip_generic_request,
811 .free = gpiochip_generic_free,
812 .direction_input = intel_gpio_direction_input,
813 .direction_output = intel_gpio_direction_output,
814 .get = intel_gpio_get,
815 .set = intel_gpio_set,
816 .set_config = gpiochip_generic_config,
819 static void intel_gpio_irq_ack(struct irq_data *d)
821 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
822 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
823 const struct intel_community *community;
824 unsigned pin = irqd_to_hwirq(d);
826 community = intel_get_community(pctrl, pin);
828 const struct intel_padgroup *padgrp;
829 unsigned gpp, gpp_offset;
831 padgrp = intel_community_get_padgroup(community, pin);
835 gpp = padgrp->reg_num;
836 gpp_offset = padgroup_offset(padgrp, pin);
838 raw_spin_lock(&pctrl->lock);
839 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
840 raw_spin_unlock(&pctrl->lock);
844 static void intel_gpio_irq_enable(struct irq_data *d)
846 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
847 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
848 const struct intel_community *community;
849 unsigned pin = irqd_to_hwirq(d);
851 community = intel_get_community(pctrl, pin);
853 const struct intel_padgroup *padgrp;
854 unsigned gpp, gpp_offset;
858 padgrp = intel_community_get_padgroup(community, pin);
862 gpp = padgrp->reg_num;
863 gpp_offset = padgroup_offset(padgrp, pin);
865 raw_spin_lock_irqsave(&pctrl->lock, flags);
866 /* Clear interrupt status first to avoid unexpected interrupt */
867 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
869 value = readl(community->regs + community->ie_offset + gpp * 4);
870 value |= BIT(gpp_offset);
871 writel(value, community->regs + community->ie_offset + gpp * 4);
872 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
876 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
878 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
879 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
880 const struct intel_community *community;
881 unsigned pin = irqd_to_hwirq(d);
883 community = intel_get_community(pctrl, pin);
885 const struct intel_padgroup *padgrp;
886 unsigned gpp, gpp_offset;
891 padgrp = intel_community_get_padgroup(community, pin);
895 gpp = padgrp->reg_num;
896 gpp_offset = padgroup_offset(padgrp, pin);
898 reg = community->regs + community->ie_offset + gpp * 4;
900 raw_spin_lock_irqsave(&pctrl->lock, flags);
903 value &= ~BIT(gpp_offset);
905 value |= BIT(gpp_offset);
907 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
911 static void intel_gpio_irq_mask(struct irq_data *d)
913 intel_gpio_irq_mask_unmask(d, true);
916 static void intel_gpio_irq_unmask(struct irq_data *d)
918 intel_gpio_irq_mask_unmask(d, false);
921 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
923 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
924 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
925 unsigned pin = irqd_to_hwirq(d);
930 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
935 * If the pin is in ACPI mode it is still usable as a GPIO but it
936 * cannot be used as IRQ because GPI_IS status bit will not be
937 * updated by the host controller hardware.
939 if (intel_pad_acpi_mode(pctrl, pin)) {
940 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
944 raw_spin_lock_irqsave(&pctrl->lock, flags);
948 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
950 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
951 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
952 } else if (type & IRQ_TYPE_EDGE_FALLING) {
953 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
954 value |= PADCFG0_RXINV;
955 } else if (type & IRQ_TYPE_EDGE_RISING) {
956 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
957 } else if (type & IRQ_TYPE_LEVEL_MASK) {
958 if (type & IRQ_TYPE_LEVEL_LOW)
959 value |= PADCFG0_RXINV;
961 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
966 if (type & IRQ_TYPE_EDGE_BOTH)
967 irq_set_handler_locked(d, handle_edge_irq);
968 else if (type & IRQ_TYPE_LEVEL_MASK)
969 irq_set_handler_locked(d, handle_level_irq);
971 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
976 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
978 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
979 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
980 unsigned pin = irqd_to_hwirq(d);
983 enable_irq_wake(pctrl->irq);
985 disable_irq_wake(pctrl->irq);
987 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
991 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
992 const struct intel_community *community)
994 struct gpio_chip *gc = &pctrl->chip;
995 irqreturn_t ret = IRQ_NONE;
998 for (gpp = 0; gpp < community->ngpps; gpp++) {
999 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1000 unsigned long pending, enabled, gpp_offset;
1002 pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4);
1003 enabled = readl(community->regs + community->ie_offset +
1004 padgrp->reg_num * 4);
1006 /* Only interrupts that are enabled */
1009 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1010 unsigned padno, irq;
1012 padno = padgrp->base - community->pin_base + gpp_offset;
1013 if (padno >= community->npins)
1016 irq = irq_find_mapping(gc->irqdomain,
1017 community->pin_base + padno);
1018 generic_handle_irq(irq);
1027 static irqreturn_t intel_gpio_irq(int irq, void *data)
1029 const struct intel_community *community;
1030 struct intel_pinctrl *pctrl = data;
1031 irqreturn_t ret = IRQ_NONE;
1034 /* Need to check all communities for pending interrupts */
1035 for (i = 0; i < pctrl->ncommunities; i++) {
1036 community = &pctrl->communities[i];
1037 ret |= intel_gpio_community_irq_handler(pctrl, community);
1043 static struct irq_chip intel_gpio_irqchip = {
1044 .name = "intel-gpio",
1045 .irq_enable = intel_gpio_irq_enable,
1046 .irq_ack = intel_gpio_irq_ack,
1047 .irq_mask = intel_gpio_irq_mask,
1048 .irq_unmask = intel_gpio_irq_unmask,
1049 .irq_set_type = intel_gpio_irq_type,
1050 .irq_set_wake = intel_gpio_irq_wake,
1051 .flags = IRQCHIP_MASK_ON_SUSPEND,
1054 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1058 pctrl->chip = intel_gpio_chip;
1060 pctrl->chip.ngpio = pctrl->soc->npins;
1061 pctrl->chip.label = dev_name(pctrl->dev);
1062 pctrl->chip.parent = pctrl->dev;
1063 pctrl->chip.base = -1;
1066 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1068 dev_err(pctrl->dev, "failed to register gpiochip\n");
1072 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1073 0, 0, pctrl->soc->npins);
1075 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1080 * We need to request the interrupt here (instead of providing chip
1081 * to the irq directly) because on some platforms several GPIO
1082 * controllers share the same interrupt line.
1084 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1085 IRQF_SHARED | IRQF_NO_THREAD,
1086 dev_name(pctrl->dev), pctrl);
1088 dev_err(pctrl->dev, "failed to request interrupt\n");
1092 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1093 handle_bad_irq, IRQ_TYPE_NONE);
1095 dev_err(pctrl->dev, "failed to add irqchip\n");
1099 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1104 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1105 struct intel_community *community)
1107 struct intel_padgroup *gpps;
1108 unsigned npins = community->npins;
1109 unsigned padown_num = 0;
1112 if (community->gpps)
1113 ngpps = community->ngpps;
1115 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1117 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1121 for (i = 0; i < ngpps; i++) {
1122 if (community->gpps) {
1123 gpps[i] = community->gpps[i];
1125 unsigned gpp_size = community->gpp_size;
1127 gpps[i].reg_num = i;
1128 gpps[i].base = community->pin_base + i * gpp_size;
1129 gpps[i].size = min(gpp_size, npins);
1130 npins -= gpps[i].size;
1133 if (gpps[i].size > 32)
1136 gpps[i].padown_num = padown_num;
1139 * In older hardware the number of padown registers per
1140 * group is fixed regardless of the group size.
1142 if (community->gpp_num_padown_regs)
1143 padown_num += community->gpp_num_padown_regs;
1145 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1148 community->ngpps = ngpps;
1149 community->gpps = gpps;
1154 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1156 #ifdef CONFIG_PM_SLEEP
1157 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1158 struct intel_community_context *communities;
1159 struct intel_pad_context *pads;
1162 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1166 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1167 sizeof(*communities), GFP_KERNEL);
1172 for (i = 0; i < pctrl->ncommunities; i++) {
1173 struct intel_community *community = &pctrl->communities[i];
1176 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1177 sizeof(*intmask), GFP_KERNEL);
1181 communities[i].intmask = intmask;
1184 pctrl->context.pads = pads;
1185 pctrl->context.communities = communities;
1191 int intel_pinctrl_probe(struct platform_device *pdev,
1192 const struct intel_pinctrl_soc_data *soc_data)
1194 struct intel_pinctrl *pctrl;
1200 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1204 pctrl->dev = &pdev->dev;
1205 pctrl->soc = soc_data;
1206 raw_spin_lock_init(&pctrl->lock);
1209 * Make a copy of the communities which we can use to hold pointers
1212 pctrl->ncommunities = pctrl->soc->ncommunities;
1213 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1214 sizeof(*pctrl->communities), GFP_KERNEL);
1215 if (!pctrl->communities)
1218 for (i = 0; i < pctrl->ncommunities; i++) {
1219 struct intel_community *community = &pctrl->communities[i];
1220 struct resource *res;
1224 *community = pctrl->soc->communities[i];
1226 res = platform_get_resource(pdev, IORESOURCE_MEM,
1228 regs = devm_ioremap_resource(&pdev->dev, res);
1230 return PTR_ERR(regs);
1233 * Determine community features based on the revision if
1234 * not specified already.
1236 if (!community->features) {
1239 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1241 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1242 community->features |= PINCTRL_FEATURE_1K_PD;
1246 /* Read offset of the pad configuration registers */
1247 padbar = readl(regs + PADBAR);
1249 community->regs = regs;
1250 community->pad_regs = regs + padbar;
1252 ret = intel_pinctrl_add_padgroups(pctrl, community);
1257 irq = platform_get_irq(pdev, 0);
1259 dev_err(&pdev->dev, "failed to get interrupt number\n");
1263 ret = intel_pinctrl_pm_init(pctrl);
1267 pctrl->pctldesc = intel_pinctrl_desc;
1268 pctrl->pctldesc.name = dev_name(&pdev->dev);
1269 pctrl->pctldesc.pins = pctrl->soc->pins;
1270 pctrl->pctldesc.npins = pctrl->soc->npins;
1272 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1274 if (IS_ERR(pctrl->pctldev)) {
1275 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1276 return PTR_ERR(pctrl->pctldev);
1279 ret = intel_gpio_probe(pctrl, irq);
1283 platform_set_drvdata(pdev, pctrl);
1287 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1289 #ifdef CONFIG_PM_SLEEP
1290 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1292 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1294 if (!pd || !intel_pad_usable(pctrl, pin))
1298 * Only restore the pin if it is actually in use by the kernel (or
1299 * by userspace). It is possible that some pins are used by the
1300 * BIOS during resume and those are not always locked down so leave
1303 if (pd->mux_owner || pd->gpio_owner ||
1304 gpiochip_line_is_irq(&pctrl->chip, pin))
1310 int intel_pinctrl_suspend(struct device *dev)
1312 struct platform_device *pdev = to_platform_device(dev);
1313 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1314 struct intel_community_context *communities;
1315 struct intel_pad_context *pads;
1318 pads = pctrl->context.pads;
1319 for (i = 0; i < pctrl->soc->npins; i++) {
1320 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1321 void __iomem *padcfg;
1324 if (!intel_pinctrl_should_save(pctrl, desc->number))
1327 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1328 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1329 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1330 pads[i].padcfg1 = val;
1332 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1334 pads[i].padcfg2 = readl(padcfg);
1337 communities = pctrl->context.communities;
1338 for (i = 0; i < pctrl->ncommunities; i++) {
1339 struct intel_community *community = &pctrl->communities[i];
1343 base = community->regs + community->ie_offset;
1344 for (gpp = 0; gpp < community->ngpps; gpp++)
1345 communities[i].intmask[gpp] = readl(base + gpp * 4);
1350 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1352 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1356 for (i = 0; i < pctrl->ncommunities; i++) {
1357 const struct intel_community *community;
1361 community = &pctrl->communities[i];
1362 base = community->regs;
1364 for (gpp = 0; gpp < community->ngpps; gpp++) {
1365 /* Mask and clear all interrupts */
1366 writel(0, base + community->ie_offset + gpp * 4);
1367 writel(0xffff, base + GPI_IS + gpp * 4);
1372 int intel_pinctrl_resume(struct device *dev)
1374 struct platform_device *pdev = to_platform_device(dev);
1375 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1376 const struct intel_community_context *communities;
1377 const struct intel_pad_context *pads;
1380 /* Mask all interrupts */
1381 intel_gpio_irq_init(pctrl);
1383 pads = pctrl->context.pads;
1384 for (i = 0; i < pctrl->soc->npins; i++) {
1385 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1386 void __iomem *padcfg;
1389 if (!intel_pinctrl_should_save(pctrl, desc->number))
1392 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1393 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1394 if (val != pads[i].padcfg0) {
1395 writel(pads[i].padcfg0, padcfg);
1396 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1397 desc->number, readl(padcfg));
1400 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1401 val = readl(padcfg);
1402 if (val != pads[i].padcfg1) {
1403 writel(pads[i].padcfg1, padcfg);
1404 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1405 desc->number, readl(padcfg));
1408 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1410 val = readl(padcfg);
1411 if (val != pads[i].padcfg2) {
1412 writel(pads[i].padcfg2, padcfg);
1413 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1414 desc->number, readl(padcfg));
1419 communities = pctrl->context.communities;
1420 for (i = 0; i < pctrl->ncommunities; i++) {
1421 struct intel_community *community = &pctrl->communities[i];
1425 base = community->regs + community->ie_offset;
1426 for (gpp = 0; gpp < community->ngpps; gpp++) {
1427 writel(communities[i].intmask[gpp], base + gpp * 4);
1428 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1429 readl(base + gpp * 4));
1435 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1438 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1439 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1440 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1441 MODULE_LICENSE("GPL v2");