drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/log2.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pinctrl/pinctrl.h>
  16 #include <linux/pinctrl/pinmux.h>
  17 #include <linux/pinctrl/pinconf.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19
  20 #include "../core.h"
  21 #include "pinctrl-intel.h"
  22
  23 /* Offset from regs */
  24 #define REVID                           0x000
  25 #define REVID_SHIFT                     16
  26 #define REVID_MASK                      GENMASK(31, 16)
  27
  28 #define PADBAR                          0x00c
  29 #define GPI_IS                          0x100
  30
  31 #define PADOWN_BITS                     4
  32 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  33 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  34 #define PADOWN_GPP(p)                   ((p) / 8)
  35
  36 /* Offset from pad_regs */
  37 #define PADCFG0                         0x000
  38 #define PADCFG0_RXEVCFG_SHIFT           25
  39 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  40 #define PADCFG0_RXEVCFG_LEVEL           0
  41 #define PADCFG0_RXEVCFG_EDGE            1
  42 #define PADCFG0_RXEVCFG_DISABLED        2
  43 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  44 #define PADCFG0_PREGFRXSEL              BIT(24)
  45 #define PADCFG0_RXINV                   BIT(23)
  46 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  47 #define PADCFG0_GPIROUTSCI              BIT(19)
  48 #define PADCFG0_GPIROUTSMI              BIT(18)
  49 #define PADCFG0_GPIROUTNMI              BIT(17)
  50 #define PADCFG0_PMODE_SHIFT             10
  51 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  52 #define PADCFG0_PMODE_GPIO              0
  53 #define PADCFG0_GPIORXDIS               BIT(9)
  54 #define PADCFG0_GPIOTXDIS               BIT(8)
  55 #define PADCFG0_GPIORXSTATE             BIT(1)
  56 #define PADCFG0_GPIOTXSTATE             BIT(0)
  57
  58 #define PADCFG1                         0x004
  59 #define PADCFG1_TERM_UP                 BIT(13)
  60 #define PADCFG1_TERM_SHIFT              10
  61 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  62 #define PADCFG1_TERM_20K                4
  63 #define PADCFG1_TERM_2K                 3
  64 #define PADCFG1_TERM_5K                 2
  65 #define PADCFG1_TERM_1K                 1
  66
  67 #define PADCFG2                         0x008
  68 #define PADCFG2_DEBEN                   BIT(0)
  69 #define PADCFG2_DEBOUNCE_SHIFT          1
  70 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  71
  72 #define DEBOUNCE_PERIOD                 31250 /* ns */
  73
  74 struct intel_pad_context {
  75         u32 padcfg0;
  76         u32 padcfg1;
  77         u32 padcfg2;
  78 };
  79
  80 struct intel_community_context {
  81         u32 *intmask;
  82 };
  83
  84 struct intel_pinctrl_context {
  85         struct intel_pad_context *pads;
  86         struct intel_community_context *communities;
  87 };
  88
  89 /**
  90  * struct intel_pinctrl - Intel pinctrl private structure
  91  * @dev: Pointer to the device structure
  92  * @lock: Lock to serialize register access
  93  * @pctldesc: Pin controller description
  94  * @pctldev: Pointer to the pin controller device
  95  * @chip: GPIO chip in this pin controller
  96  * @soc: SoC/PCH specific pin configuration data
  97  * @communities: All communities in this pin controller
  98  * @ncommunities: Number of communities in this pin controller
  99  * @context: Configuration saved over system sleep
 100  * @irq: pinctrl/GPIO chip irq number
 101  */
 102 struct intel_pinctrl {
 103         struct device *dev;
 104         raw_spinlock_t lock;
 105         struct pinctrl_desc pctldesc;
 106         struct pinctrl_dev *pctldev;
 107         struct gpio_chip chip;
 108         const struct intel_pinctrl_soc_data *soc;
 109         struct intel_community *communities;
 110         size_t ncommunities;
 111         struct intel_pinctrl_context context;
 112         int irq;
 113 };
 114
 115 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 116 #define padgroup_offset(g, p)   ((p) - (g)->base)
 117
 118 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 119                                                    unsigned int pin)
 120 {
 121         struct intel_community *community;
 122         int i;
 123
 124         for (i = 0; i < pctrl->ncommunities; i++) {
 125                 community = &pctrl->communities[i];
 126                 if (pin >= community->pin_base &&
 127                     pin < community->pin_base + community->npins)
 128                         return community;
 129         }
 130
 131         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 132         return NULL;
 133 }
 134
 135 static const struct intel_padgroup *
 136 intel_community_get_padgroup(const struct intel_community *community,
 137                              unsigned int pin)
 138 {
 139         int i;
 140
 141         for (i = 0; i < community->ngpps; i++) {
 142                 const struct intel_padgroup *padgrp = &community->gpps[i];
 143
 144                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 145                         return padgrp;
 146         }
 147
 148         return NULL;
 149 }
 150
 151 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 152                                       unsigned int pin, unsigned int reg)
 153 {
 154         const struct intel_community *community;
 155         unsigned int padno;
 156         size_t nregs;
 157
 158         community = intel_get_community(pctrl, pin);
 159         if (!community)
 160                 return NULL;
 161
 162         padno = pin_to_padno(community, pin);
 163         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 164
 165         if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
 166                 return NULL;
 167
 168         return community->pad_regs + reg + padno * nregs * 4;
 169 }
 170
 171 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 172 {
 173         const struct intel_community *community;
 174         const struct intel_padgroup *padgrp;
 175         unsigned int gpp, offset, gpp_offset;
 176         void __iomem *padown;
 177
 178         community = intel_get_community(pctrl, pin);
 179         if (!community)
 180                 return false;
 181         if (!community->padown_offset)
 182                 return true;
 183
 184         padgrp = intel_community_get_padgroup(community, pin);
 185         if (!padgrp)
 186                 return false;
 187
 188         gpp_offset = padgroup_offset(padgrp, pin);
 189         gpp = PADOWN_GPP(gpp_offset);
 190         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 191         padown = community->regs + offset;
 192
 193         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 194 }
 195
 196 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 197 {
 198         const struct intel_community *community;
 199         const struct intel_padgroup *padgrp;
 200         unsigned int offset, gpp_offset;
 201         void __iomem *hostown;
 202
 203         community = intel_get_community(pctrl, pin);
 204         if (!community)
 205                 return true;
 206         if (!community->hostown_offset)
 207                 return false;
 208
 209         padgrp = intel_community_get_padgroup(community, pin);
 210         if (!padgrp)
 211                 return true;
 212
 213         gpp_offset = padgroup_offset(padgrp, pin);
 214         offset = community->hostown_offset + padgrp->reg_num * 4;
 215         hostown = community->regs + offset;
 216
 217         return !(readl(hostown) & BIT(gpp_offset));
 218 }
 219
 220 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 221 {
 222         struct intel_community *community;
 223         const struct intel_padgroup *padgrp;
 224         unsigned int offset, gpp_offset;
 225         u32 value;
 226
 227         community = intel_get_community(pctrl, pin);
 228         if (!community)
 229                 return true;
 230         if (!community->padcfglock_offset)
 231                 return false;
 232
 233         padgrp = intel_community_get_padgroup(community, pin);
 234         if (!padgrp)
 235                 return true;
 236
 237         gpp_offset = padgroup_offset(padgrp, pin);
 238
 239         /*
 240          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 241          * the pad is considered unlocked. Any other case means that it is
 242          * either fully or partially locked and we don't touch it.
 243          */
 244         offset = community->padcfglock_offset + padgrp->reg_num * 8;
 245         value = readl(community->regs + offset);
 246         if (value & BIT(gpp_offset))
 247                 return true;
 248
 249         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 250         value = readl(community->regs + offset);
 251         if (value & BIT(gpp_offset))
 252                 return true;
 253
 254         return false;
 255 }
 256
 257 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 258 {
 259         return intel_pad_owned_by_host(pctrl, pin) &&
 260                 !intel_pad_locked(pctrl, pin);
 261 }
 262
 263 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 264 {
 265         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 266
 267         return pctrl->soc->ngroups;
 268 }
 269
 270 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 271                                       unsigned int group)
 272 {
 273         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 274
 275         return pctrl->soc->groups[group].name;
 276 }
 277
 278 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 279                               const unsigned int **pins, unsigned int *npins)
 280 {
 281         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 282
 283         *pins = pctrl->soc->groups[group].pins;
 284         *npins = pctrl->soc->groups[group].npins;
 285         return 0;
 286 }
 287
 288 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 289                                unsigned int pin)
 290 {
 291         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 292         void __iomem *padcfg;
 293         u32 cfg0, cfg1, mode;
 294         bool locked, acpi;
 295
 296         if (!intel_pad_owned_by_host(pctrl, pin)) {
 297                 seq_puts(s, "not available");
 298                 return;
 299         }
 300
 301         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 302         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 303
 304         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 305         if (mode == PADCFG0_PMODE_GPIO)
 306                 seq_puts(s, "GPIO ");
 307         else
 308                 seq_printf(s, "mode %d ", mode);
 309
 310         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 311
 312         /* Dump the additional PADCFG registers if available */
 313         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 314         if (padcfg)
 315                 seq_printf(s, " 0x%08x", readl(padcfg));
 316
 317         locked = intel_pad_locked(pctrl, pin);
 318         acpi = intel_pad_acpi_mode(pctrl, pin);
 319
 320         if (locked || acpi) {
 321                 seq_puts(s, " [");
 322                 if (locked) {
 323                         seq_puts(s, "LOCKED");
 324                         if (acpi)
 325                                 seq_puts(s, ", ");
 326                 }
 327                 if (acpi)
 328                         seq_puts(s, "ACPI");
 329                 seq_puts(s, "]");
 330         }
 331 }
 332
 333 static const struct pinctrl_ops intel_pinctrl_ops = {
 334         .get_groups_count = intel_get_groups_count,
 335         .get_group_name = intel_get_group_name,
 336         .get_group_pins = intel_get_group_pins,
 337         .pin_dbg_show = intel_pin_dbg_show,
 338 };
 339
 340 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 341 {
 342         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 343
 344         return pctrl->soc->nfunctions;
 345 }
 346
 347 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 348                                            unsigned int function)
 349 {
 350         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 351
 352         return pctrl->soc->functions[function].name;
 353 }
 354
 355 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 356                                      unsigned int function,
 357                                      const char * const **groups,
 358                                      unsigned int * const ngroups)
 359 {
 360         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 361
 362         *groups = pctrl->soc->functions[function].groups;
 363         *ngroups = pctrl->soc->functions[function].ngroups;
 364         return 0;
 365 }
 366
 367 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 368                                 unsigned int function, unsigned int group)
 369 {
 370         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 371         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 372         unsigned long flags;
 373         int i;
 374
 375         raw_spin_lock_irqsave(&pctrl->lock, flags);
 376
 377         /*
 378          * All pins in the groups needs to be accessible and writable
 379          * before we can enable the mux for this group.
 380          */
 381         for (i = 0; i < grp->npins; i++) {
 382                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 383                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 384                         return -EBUSY;
 385                 }
 386         }
 387
 388         /* Now enable the mux setting for each pin in the group */
 389         for (i = 0; i < grp->npins; i++) {
 390                 void __iomem *padcfg0;
 391                 u32 value;
 392
 393                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 394                 value = readl(padcfg0);
 395
 396                 value &= ~PADCFG0_PMODE_MASK;
 397
 398                 if (grp->modes)
 399                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 400                 else
 401                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 402
 403                 writel(value, padcfg0);
 404         }
 405
 406         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 407
 408         return 0;
 409 }
 410
 411 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 412 {
 413         u32 value;
 414
 415         value = readl(padcfg0);
 416         if (input) {
 417                 value &= ~PADCFG0_GPIORXDIS;
 418                 value |= PADCFG0_GPIOTXDIS;
 419         } else {
 420                 value &= ~PADCFG0_GPIOTXDIS;
 421                 value |= PADCFG0_GPIORXDIS;
 422         }
 423         writel(value, padcfg0);
 424 }
 425
 426 static int __intel_gpio_get_gpio_mode(u32 value)
 427 {
 428         return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 429 }
 430
 431 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 432 {
 433         return __intel_gpio_get_gpio_mode(readl(padcfg0));
 434 }
 435
 436 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 437 {
 438         u32 value;
 439
 440         /* Put the pad into GPIO mode */
 441         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 442         /* Disable SCI/SMI/NMI generation */
 443         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 444         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 445         writel(value, padcfg0);
 446 }
 447
 448 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 449                                      struct pinctrl_gpio_range *range,
 450                                      unsigned int pin)
 451 {
 452         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 453         void __iomem *padcfg0;
 454         unsigned long flags;
 455
 456         raw_spin_lock_irqsave(&pctrl->lock, flags);
 457
 458         if (!intel_pad_usable(pctrl, pin)) {
 459                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 460                 return -EBUSY;
 461         }
 462
 463         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 464
 465         /*
 466          * If pin is already configured in GPIO mode, we assume that
 467          * firmware provides correct settings. In such case we avoid
 468          * potential glitches on the pin. Otherwise, for the pin in
 469          * alternative mode, consumer has to supply respective flags.
 470          */
 471         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
 472                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 473                 return 0;
 474         }
 475
 476         intel_gpio_set_gpio_mode(padcfg0);
 477
 478         /* Disable TX buffer and enable RX (this will be input) */
 479         __intel_gpio_set_direction(padcfg0, true);
 480
 481         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 482
 483         return 0;
 484 }
 485
 486 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 487                                     struct pinctrl_gpio_range *range,
 488                                     unsigned int pin, bool input)
 489 {
 490         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 491         void __iomem *padcfg0;
 492         unsigned long flags;
 493
 494         raw_spin_lock_irqsave(&pctrl->lock, flags);
 495
 496         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 497         __intel_gpio_set_direction(padcfg0, input);
 498
 499         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 500
 501         return 0;
 502 }
 503
 504 static const struct pinmux_ops intel_pinmux_ops = {
 505         .get_functions_count = intel_get_functions_count,
 506         .get_function_name = intel_get_function_name,
 507         .get_function_groups = intel_get_function_groups,
 508         .set_mux = intel_pinmux_set_mux,
 509         .gpio_request_enable = intel_gpio_request_enable,
 510         .gpio_set_direction = intel_gpio_set_direction,
 511 };
 512
 513 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 514                             unsigned long *config)
 515 {
 516         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 517         enum pin_config_param param = pinconf_to_config_param(*config);
 518         const struct intel_community *community;
 519         u32 value, term;
 520         u32 arg = 0;
 521
 522         if (!intel_pad_owned_by_host(pctrl, pin))
 523                 return -ENOTSUPP;
 524
 525         community = intel_get_community(pctrl, pin);
 526         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 527         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 528
 529         switch (param) {
 530         case PIN_CONFIG_BIAS_DISABLE:
 531                 if (term)
 532                         return -EINVAL;
 533                 break;
 534
 535         case PIN_CONFIG_BIAS_PULL_UP:
 536                 if (!term || !(value & PADCFG1_TERM_UP))
 537                         return -EINVAL;
 538
 539                 switch (term) {
 540                 case PADCFG1_TERM_1K:
 541                         arg = 1000;
 542                         break;
 543                 case PADCFG1_TERM_2K:
 544                         arg = 2000;
 545                         break;
 546                 case PADCFG1_TERM_5K:
 547                         arg = 5000;
 548                         break;
 549                 case PADCFG1_TERM_20K:
 550                         arg = 20000;
 551                         break;
 552                 }
 553
 554                 break;
 555
 556         case PIN_CONFIG_BIAS_PULL_DOWN:
 557                 if (!term || value & PADCFG1_TERM_UP)
 558                         return -EINVAL;
 559
 560                 switch (term) {
 561                 case PADCFG1_TERM_1K:
 562                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 563                                 return -EINVAL;
 564                         arg = 1000;
 565                         break;
 566                 case PADCFG1_TERM_5K:
 567                         arg = 5000;
 568                         break;
 569                 case PADCFG1_TERM_20K:
 570                         arg = 20000;
 571                         break;
 572                 }
 573
 574                 break;
 575
 576         case PIN_CONFIG_INPUT_DEBOUNCE: {
 577                 void __iomem *padcfg2;
 578                 u32 v;
 579
 580                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 581                 if (!padcfg2)
 582                         return -ENOTSUPP;
 583
 584                 v = readl(padcfg2);
 585                 if (!(v & PADCFG2_DEBEN))
 586                         return -EINVAL;
 587
 588                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 589                 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
 590
 591                 break;
 592         }
 593
 594         default:
 595                 return -ENOTSUPP;
 596         }
 597
 598         *config = pinconf_to_config_packed(param, arg);
 599         return 0;
 600 }
 601
 602 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 603                                  unsigned long config)
 604 {
 605         unsigned int param = pinconf_to_config_param(config);
 606         unsigned int arg = pinconf_to_config_argument(config);
 607         const struct intel_community *community;
 608         void __iomem *padcfg1;
 609         unsigned long flags;
 610         int ret = 0;
 611         u32 value;
 612
 613         raw_spin_lock_irqsave(&pctrl->lock, flags);
 614
 615         community = intel_get_community(pctrl, pin);
 616         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 617         value = readl(padcfg1);
 618
 619         switch (param) {
 620         case PIN_CONFIG_BIAS_DISABLE:
 621                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 622                 break;
 623
 624         case PIN_CONFIG_BIAS_PULL_UP:
 625                 value &= ~PADCFG1_TERM_MASK;
 626
 627                 value |= PADCFG1_TERM_UP;
 628
 629                 /* Set default strength value in case none is given */
 630                 if (arg == 1)
 631                         arg = 5000;
 632
 633                 switch (arg) {
 634                 case 20000:
 635                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 636                         break;
 637                 case 5000:
 638                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 639                         break;
 640                 case 2000:
 641                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 642                         break;
 643                 case 1000:
 644                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 645                         break;
 646                 default:
 647                         ret = -EINVAL;
 648                 }
 649
 650                 break;
 651
 652         case PIN_CONFIG_BIAS_PULL_DOWN:
 653                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 654
 655                 /* Set default strength value in case none is given */
 656                 if (arg == 1)
 657                         arg = 5000;
 658
 659                 switch (arg) {
 660                 case 20000:
 661                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 662                         break;
 663                 case 5000:
 664                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 665                         break;
 666                 case 1000:
 667                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 668                                 ret = -EINVAL;
 669                                 break;
 670                         }
 671                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 672                         break;
 673                 default:
 674                         ret = -EINVAL;
 675                 }
 676
 677                 break;
 678         }
 679
 680         if (!ret)
 681                 writel(value, padcfg1);
 682
 683         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 684
 685         return ret;
 686 }
 687
 688 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 689                                      unsigned int pin, unsigned int debounce)
 690 {
 691         void __iomem *padcfg0, *padcfg2;
 692         unsigned long flags;
 693         u32 value0, value2;
 694         int ret = 0;
 695
 696         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 697         if (!padcfg2)
 698                 return -ENOTSUPP;
 699
 700         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 701
 702         raw_spin_lock_irqsave(&pctrl->lock, flags);
 703
 704         value0 = readl(padcfg0);
 705         value2 = readl(padcfg2);
 706
 707         /* Disable glitch filter and debouncer */
 708         value0 &= ~PADCFG0_PREGFRXSEL;
 709         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 710
 711         if (debounce) {
 712                 unsigned long v;
 713
 714                 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
 715                 if (v < 3 || v > 15) {
 716                         ret = -EINVAL;
 717                         goto exit_unlock;
 718                 } else {
 719                         /* Enable glitch filter and debouncer */
 720                         value0 |= PADCFG0_PREGFRXSEL;
 721                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 722                         value2 |= PADCFG2_DEBEN;
 723                 }
 724         }
 725
 726         writel(value0, padcfg0);
 727         writel(value2, padcfg2);
 728
 729 exit_unlock:
 730         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 731
 732         return ret;
 733 }
 734
 735 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 736                           unsigned long *configs, unsigned int nconfigs)
 737 {
 738         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 739         int i, ret;
 740
 741         if (!intel_pad_usable(pctrl, pin))
 742                 return -ENOTSUPP;
 743
 744         for (i = 0; i < nconfigs; i++) {
 745                 switch (pinconf_to_config_param(configs[i])) {
 746                 case PIN_CONFIG_BIAS_DISABLE:
 747                 case PIN_CONFIG_BIAS_PULL_UP:
 748                 case PIN_CONFIG_BIAS_PULL_DOWN:
 749                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 750                         if (ret)
 751                                 return ret;
 752                         break;
 753
 754                 case PIN_CONFIG_INPUT_DEBOUNCE:
 755                         ret = intel_config_set_debounce(pctrl, pin,
 756                                 pinconf_to_config_argument(configs[i]));
 757                         if (ret)
 758                                 return ret;
 759                         break;
 760
 761                 default:
 762                         return -ENOTSUPP;
 763                 }
 764         }
 765
 766         return 0;
 767 }
 768
 769 static const struct pinconf_ops intel_pinconf_ops = {
 770         .is_generic = true,
 771         .pin_config_get = intel_config_get,
 772         .pin_config_set = intel_config_set,
 773 };
 774
 775 static const struct pinctrl_desc intel_pinctrl_desc = {
 776         .pctlops = &intel_pinctrl_ops,
 777         .pmxops = &intel_pinmux_ops,
 778         .confops = &intel_pinconf_ops,
 779         .owner = THIS_MODULE,
 780 };
 781
 782 /**
 783  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 784  * @pctrl: Pinctrl structure
 785  * @offset: GPIO offset from gpiolib
 786  * @commmunity: Community is filled here if not %NULL
 787  * @padgrp: Pad group is filled here if not %NULL
 788  *
 789  * When coming through gpiolib irqchip, the GPIO offset is not
 790  * automatically translated to pinctrl pin number. This function can be
 791  * used to find out the corresponding pinctrl pin.
 792  */
 793 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 794                              const struct intel_community **community,
 795                              const struct intel_padgroup **padgrp)
 796 {
 797         int i;
 798
 799         for (i = 0; i < pctrl->ncommunities; i++) {
 800                 const struct intel_community *comm = &pctrl->communities[i];
 801                 int j;
 802
 803                 for (j = 0; j < comm->ngpps; j++) {
 804                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 805
 806                         if (pgrp->gpio_base < 0)
 807                                 continue;
 808
 809                         if (offset >= pgrp->gpio_base &&
 810                             offset < pgrp->gpio_base + pgrp->size) {
 811                                 int pin;
 812
 813                                 pin = pgrp->base + offset - pgrp->gpio_base;
 814                                 if (community)
 815                                         *community = comm;
 816                                 if (padgrp)
 817                                         *padgrp = pgrp;
 818
 819                                 return pin;
 820                         }
 821                 }
 822         }
 823
 824         return -EINVAL;
 825 }
 826
 827 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 828 {
 829         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 830         void __iomem *reg;
 831         u32 padcfg0;
 832         int pin;
 833
 834         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 835         if (pin < 0)
 836                 return -EINVAL;
 837
 838         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 839         if (!reg)
 840                 return -EINVAL;
 841
 842         padcfg0 = readl(reg);
 843         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 844                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 845
 846         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 847 }
 848
 849 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 850                            int value)
 851 {
 852         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 853         unsigned long flags;
 854         void __iomem *reg;
 855         u32 padcfg0;
 856         int pin;
 857
 858         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 859         if (pin < 0)
 860                 return;
 861
 862         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 863         if (!reg)
 864                 return;
 865
 866         raw_spin_lock_irqsave(&pctrl->lock, flags);
 867         padcfg0 = readl(reg);
 868         if (value)
 869                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 870         else
 871                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 872         writel(padcfg0, reg);
 873         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 874 }
 875
 876 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 877 {
 878         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 879         void __iomem *reg;
 880         u32 padcfg0;
 881         int pin;
 882
 883         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 884         if (pin < 0)
 885                 return -EINVAL;
 886
 887         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 888         if (!reg)
 889                 return -EINVAL;
 890
 891         padcfg0 = readl(reg);
 892
 893         if (padcfg0 & PADCFG0_PMODE_MASK)
 894                 return -EINVAL;
 895
 896         return !!(padcfg0 & PADCFG0_GPIOTXDIS);
 897 }
 898
 899 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 900 {
 901         return pinctrl_gpio_direction_input(chip->base + offset);
 902 }
 903
 904 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
 905                                        int value)
 906 {
 907         intel_gpio_set(chip, offset, value);
 908         return pinctrl_gpio_direction_output(chip->base + offset);
 909 }
 910
 911 static const struct gpio_chip intel_gpio_chip = {
 912         .owner = THIS_MODULE,
 913         .request = gpiochip_generic_request,
 914         .free = gpiochip_generic_free,
 915         .get_direction = intel_gpio_get_direction,
 916         .direction_input = intel_gpio_direction_input,
 917         .direction_output = intel_gpio_direction_output,
 918         .get = intel_gpio_get,
 919         .set = intel_gpio_set,
 920         .set_config = gpiochip_generic_config,
 921 };
 922
 923 static void intel_gpio_irq_ack(struct irq_data *d)
 924 {
 925         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 926         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 927         const struct intel_community *community;
 928         const struct intel_padgroup *padgrp;
 929         int pin;
 930
 931         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 932         if (pin >= 0) {
 933                 unsigned int gpp, gpp_offset, is_offset;
 934
 935                 gpp = padgrp->reg_num;
 936                 gpp_offset = padgroup_offset(padgrp, pin);
 937                 is_offset = community->is_offset + gpp * 4;
 938
 939                 raw_spin_lock(&pctrl->lock);
 940                 writel(BIT(gpp_offset), community->regs + is_offset);
 941                 raw_spin_unlock(&pctrl->lock);
 942         }
 943 }
 944
 945 static void intel_gpio_irq_enable(struct irq_data *d)
 946 {
 947         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 948         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 949         const struct intel_community *community;
 950         const struct intel_padgroup *padgrp;
 951         int pin;
 952
 953         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 954         if (pin >= 0) {
 955                 unsigned int gpp, gpp_offset, is_offset;
 956                 unsigned long flags;
 957                 u32 value;
 958
 959                 gpp = padgrp->reg_num;
 960                 gpp_offset = padgroup_offset(padgrp, pin);
 961                 is_offset = community->is_offset + gpp * 4;
 962
 963                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 964                 /* Clear interrupt status first to avoid unexpected interrupt */
 965                 writel(BIT(gpp_offset), community->regs + is_offset);
 966
 967                 value = readl(community->regs + community->ie_offset + gpp * 4);
 968                 value |= BIT(gpp_offset);
 969                 writel(value, community->regs + community->ie_offset + gpp * 4);
 970                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 971         }
 972 }
 973
 974 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 975 {
 976         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 977         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 978         const struct intel_community *community;
 979         const struct intel_padgroup *padgrp;
 980         int pin;
 981
 982         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 983         if (pin >= 0) {
 984                 unsigned int gpp, gpp_offset;
 985                 unsigned long flags;
 986                 void __iomem *reg;
 987                 u32 value;
 988
 989                 gpp = padgrp->reg_num;
 990                 gpp_offset = padgroup_offset(padgrp, pin);
 991
 992                 reg = community->regs + community->ie_offset + gpp * 4;
 993
 994                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 995                 value = readl(reg);
 996                 if (mask)
 997                         value &= ~BIT(gpp_offset);
 998                 else
 999                         value |= BIT(gpp_offset);
1000                 writel(value, reg);
1001                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1002         }
1003 }
1004
1005 static void intel_gpio_irq_mask(struct irq_data *d)
1006 {
1007         intel_gpio_irq_mask_unmask(d, true);
1008 }
1009
1010 static void intel_gpio_irq_unmask(struct irq_data *d)
1011 {
1012         intel_gpio_irq_mask_unmask(d, false);
1013 }
1014
1015 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1016 {
1017         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1018         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1019         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1020         unsigned long flags;
1021         void __iomem *reg;
1022         u32 value;
1023
1024         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1025         if (!reg)
1026                 return -EINVAL;
1027
1028         /*
1029          * If the pin is in ACPI mode it is still usable as a GPIO but it
1030          * cannot be used as IRQ because GPI_IS status bit will not be
1031          * updated by the host controller hardware.
1032          */
1033         if (intel_pad_acpi_mode(pctrl, pin)) {
1034                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1035                 return -EPERM;
1036         }
1037
1038         raw_spin_lock_irqsave(&pctrl->lock, flags);
1039
1040         intel_gpio_set_gpio_mode(reg);
1041
1042         value = readl(reg);
1043
1044         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1045
1046         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1047                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1048         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1049                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1050                 value |= PADCFG0_RXINV;
1051         } else if (type & IRQ_TYPE_EDGE_RISING) {
1052                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1053         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1054                 if (type & IRQ_TYPE_LEVEL_LOW)
1055                         value |= PADCFG0_RXINV;
1056         } else {
1057                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1058         }
1059
1060         writel(value, reg);
1061
1062         if (type & IRQ_TYPE_EDGE_BOTH)
1063                 irq_set_handler_locked(d, handle_edge_irq);
1064         else if (type & IRQ_TYPE_LEVEL_MASK)
1065                 irq_set_handler_locked(d, handle_level_irq);
1066
1067         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1068
1069         return 0;
1070 }
1071
1072 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1073 {
1074         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1075         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1076         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1077
1078         if (on)
1079                 enable_irq_wake(pctrl->irq);
1080         else
1081                 disable_irq_wake(pctrl->irq);
1082
1083         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1084         return 0;
1085 }
1086
1087 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1088         const struct intel_community *community)
1089 {
1090         struct gpio_chip *gc = &pctrl->chip;
1091         irqreturn_t ret = IRQ_NONE;
1092         int gpp;
1093
1094         for (gpp = 0; gpp < community->ngpps; gpp++) {
1095                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1096                 unsigned long pending, enabled, gpp_offset;
1097
1098                 pending = readl(community->regs + community->is_offset +
1099                                 padgrp->reg_num * 4);
1100                 enabled = readl(community->regs + community->ie_offset +
1101                                 padgrp->reg_num * 4);
1102
1103                 /* Only interrupts that are enabled */
1104                 pending &= enabled;
1105
1106                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1107                         unsigned irq;
1108
1109                         irq = irq_find_mapping(gc->irq.domain,
1110                                                padgrp->gpio_base + gpp_offset);
1111                         generic_handle_irq(irq);
1112
1113                         ret |= IRQ_HANDLED;
1114                 }
1115         }
1116
1117         return ret;
1118 }
1119
1120 static irqreturn_t intel_gpio_irq(int irq, void *data)
1121 {
1122         const struct intel_community *community;
1123         struct intel_pinctrl *pctrl = data;
1124         irqreturn_t ret = IRQ_NONE;
1125         int i;
1126
1127         /* Need to check all communities for pending interrupts */
1128         for (i = 0; i < pctrl->ncommunities; i++) {
1129                 community = &pctrl->communities[i];
1130                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1131         }
1132
1133         return ret;
1134 }
1135
1136 static struct irq_chip intel_gpio_irqchip = {
1137         .name = "intel-gpio",
1138         .irq_enable = intel_gpio_irq_enable,
1139         .irq_ack = intel_gpio_irq_ack,
1140         .irq_mask = intel_gpio_irq_mask,
1141         .irq_unmask = intel_gpio_irq_unmask,
1142         .irq_set_type = intel_gpio_irq_type,
1143         .irq_set_wake = intel_gpio_irq_wake,
1144         .flags = IRQCHIP_MASK_ON_SUSPEND,
1145 };
1146
1147 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1148                                      const struct intel_community *community)
1149 {
1150         int ret = 0, i;
1151
1152         for (i = 0; i < community->ngpps; i++) {
1153                 const struct intel_padgroup *gpp = &community->gpps[i];
1154
1155                 if (gpp->gpio_base < 0)
1156                         continue;
1157
1158                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1159                                              gpp->gpio_base, gpp->base,
1160                                              gpp->size);
1161                 if (ret)
1162                         return ret;
1163         }
1164
1165         return ret;
1166 }
1167
1168 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1169 {
1170         const struct intel_community *community;
1171         unsigned int ngpio = 0;
1172         int i, j;
1173
1174         for (i = 0; i < pctrl->ncommunities; i++) {
1175                 community = &pctrl->communities[i];
1176                 for (j = 0; j < community->ngpps; j++) {
1177                         const struct intel_padgroup *gpp = &community->gpps[j];
1178
1179                         if (gpp->gpio_base < 0)
1180                                 continue;
1181
1182                         if (gpp->gpio_base + gpp->size > ngpio)
1183                                 ngpio = gpp->gpio_base + gpp->size;
1184                 }
1185         }
1186
1187         return ngpio;
1188 }
1189
1190 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1191 {
1192         int ret, i;
1193
1194         pctrl->chip = intel_gpio_chip;
1195
1196         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1197         pctrl->chip.label = dev_name(pctrl->dev);
1198         pctrl->chip.parent = pctrl->dev;
1199         pctrl->chip.base = -1;
1200         pctrl->irq = irq;
1201
1202         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1203         if (ret) {
1204                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1205                 return ret;
1206         }
1207
1208         for (i = 0; i < pctrl->ncommunities; i++) {
1209                 struct intel_community *community = &pctrl->communities[i];
1210
1211                 ret = intel_gpio_add_pin_ranges(pctrl, community);
1212                 if (ret) {
1213                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1214                         return ret;
1215                 }
1216         }
1217
1218         /*
1219          * We need to request the interrupt here (instead of providing chip
1220          * to the irq directly) because on some platforms several GPIO
1221          * controllers share the same interrupt line.
1222          */
1223         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1224                                IRQF_SHARED | IRQF_NO_THREAD,
1225                                dev_name(pctrl->dev), pctrl);
1226         if (ret) {
1227                 dev_err(pctrl->dev, "failed to request interrupt\n");
1228                 return ret;
1229         }
1230
1231         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1232                                    handle_bad_irq, IRQ_TYPE_NONE);
1233         if (ret) {
1234                 dev_err(pctrl->dev, "failed to add irqchip\n");
1235                 return ret;
1236         }
1237
1238         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1239                                      NULL);
1240         return 0;
1241 }
1242
1243 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1244                                        struct intel_community *community)
1245 {
1246         struct intel_padgroup *gpps;
1247         unsigned int npins = community->npins;
1248         unsigned int padown_num = 0;
1249         size_t ngpps, i;
1250
1251         if (community->gpps)
1252                 ngpps = community->ngpps;
1253         else
1254                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1255
1256         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1257         if (!gpps)
1258                 return -ENOMEM;
1259
1260         for (i = 0; i < ngpps; i++) {
1261                 if (community->gpps) {
1262                         gpps[i] = community->gpps[i];
1263                 } else {
1264                         unsigned int gpp_size = community->gpp_size;
1265
1266                         gpps[i].reg_num = i;
1267                         gpps[i].base = community->pin_base + i * gpp_size;
1268                         gpps[i].size = min(gpp_size, npins);
1269                         npins -= gpps[i].size;
1270                 }
1271
1272                 if (gpps[i].size > 32)
1273                         return -EINVAL;
1274
1275                 if (!gpps[i].gpio_base)
1276                         gpps[i].gpio_base = gpps[i].base;
1277
1278                 gpps[i].padown_num = padown_num;
1279
1280                 /*
1281                  * In older hardware the number of padown registers per
1282                  * group is fixed regardless of the group size.
1283                  */
1284                 if (community->gpp_num_padown_regs)
1285                         padown_num += community->gpp_num_padown_regs;
1286                 else
1287                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1288         }
1289
1290         community->ngpps = ngpps;
1291         community->gpps = gpps;
1292
1293         return 0;
1294 }
1295
1296 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1297 {
1298 #ifdef CONFIG_PM_SLEEP
1299         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1300         struct intel_community_context *communities;
1301         struct intel_pad_context *pads;
1302         int i;
1303
1304         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1305         if (!pads)
1306                 return -ENOMEM;
1307
1308         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1309                                    sizeof(*communities), GFP_KERNEL);
1310         if (!communities)
1311                 return -ENOMEM;
1312
1313
1314         for (i = 0; i < pctrl->ncommunities; i++) {
1315                 struct intel_community *community = &pctrl->communities[i];
1316                 u32 *intmask;
1317
1318                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1319                                        sizeof(*intmask), GFP_KERNEL);
1320                 if (!intmask)
1321                         return -ENOMEM;
1322
1323                 communities[i].intmask = intmask;
1324         }
1325
1326         pctrl->context.pads = pads;
1327         pctrl->context.communities = communities;
1328 #endif
1329
1330         return 0;
1331 }
1332
1333 int intel_pinctrl_probe(struct platform_device *pdev,
1334                         const struct intel_pinctrl_soc_data *soc_data)
1335 {
1336         struct intel_pinctrl *pctrl;
1337         int i, ret, irq;
1338
1339         if (!soc_data)
1340                 return -EINVAL;
1341
1342         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1343         if (!pctrl)
1344                 return -ENOMEM;
1345
1346         pctrl->dev = &pdev->dev;
1347         pctrl->soc = soc_data;
1348         raw_spin_lock_init(&pctrl->lock);
1349
1350         /*
1351          * Make a copy of the communities which we can use to hold pointers
1352          * to the registers.
1353          */
1354         pctrl->ncommunities = pctrl->soc->ncommunities;
1355         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1356                                   sizeof(*pctrl->communities), GFP_KERNEL);
1357         if (!pctrl->communities)
1358                 return -ENOMEM;
1359
1360         for (i = 0; i < pctrl->ncommunities; i++) {
1361                 struct intel_community *community = &pctrl->communities[i];
1362                 struct resource *res;
1363                 void __iomem *regs;
1364                 u32 padbar;
1365
1366                 *community = pctrl->soc->communities[i];
1367
1368                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1369                                             community->barno);
1370                 regs = devm_ioremap_resource(&pdev->dev, res);
1371                 if (IS_ERR(regs))
1372                         return PTR_ERR(regs);
1373
1374                 /*
1375                  * Determine community features based on the revision if
1376                  * not specified already.
1377                  */
1378                 if (!community->features) {
1379                         u32 rev;
1380
1381                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1382                         if (rev >= 0x94) {
1383                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1384                                 community->features |= PINCTRL_FEATURE_1K_PD;
1385                         }
1386                 }
1387
1388                 /* Read offset of the pad configuration registers */
1389                 padbar = readl(regs + PADBAR);
1390
1391                 community->regs = regs;
1392                 community->pad_regs = regs + padbar;
1393
1394                 if (!community->is_offset)
1395                         community->is_offset = GPI_IS;
1396
1397                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1398                 if (ret)
1399                         return ret;
1400         }
1401
1402         irq = platform_get_irq(pdev, 0);
1403         if (irq < 0) {
1404                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1405                 return irq;
1406         }
1407
1408         ret = intel_pinctrl_pm_init(pctrl);
1409         if (ret)
1410                 return ret;
1411
1412         pctrl->pctldesc = intel_pinctrl_desc;
1413         pctrl->pctldesc.name = dev_name(&pdev->dev);
1414         pctrl->pctldesc.pins = pctrl->soc->pins;
1415         pctrl->pctldesc.npins = pctrl->soc->npins;
1416
1417         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1418                                                pctrl);
1419         if (IS_ERR(pctrl->pctldev)) {
1420                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1421                 return PTR_ERR(pctrl->pctldev);
1422         }
1423
1424         ret = intel_gpio_probe(pctrl, irq);
1425         if (ret)
1426                 return ret;
1427
1428         platform_set_drvdata(pdev, pctrl);
1429
1430         return 0;
1431 }
1432 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1433
1434 #ifdef CONFIG_PM_SLEEP
1435 static bool __intel_gpio_is_direct_irq(u32 value)
1436 {
1437         return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1438                (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1439 }
1440
1441 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1442 {
1443         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1444         u32 value;
1445
1446         if (!pd || !intel_pad_usable(pctrl, pin))
1447                 return false;
1448
1449         /*
1450          * Only restore the pin if it is actually in use by the kernel (or
1451          * by userspace). It is possible that some pins are used by the
1452          * BIOS during resume and those are not always locked down so leave
1453          * them alone.
1454          */
1455         if (pd->mux_owner || pd->gpio_owner ||
1456             gpiochip_line_is_irq(&pctrl->chip, pin))
1457                 return true;
1458
1459         /*
1460          * The firmware on some systems may configure GPIO pins to be
1461          * an interrupt source in so called "direct IRQ" mode. In such
1462          * cases the GPIO controller driver has no idea if those pins
1463          * are being used or not. At the same time, there is a known bug
1464          * in the firmwares that don't restore the pin settings correctly
1465          * after suspend, i.e. by an unknown reason the Rx value becomes
1466          * inverted.
1467          *
1468          * Hence, let's save and restore the pins that are configured
1469          * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1470          *
1471          * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1472          */
1473         value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1474         if (__intel_gpio_is_direct_irq(value))
1475                 return true;
1476
1477         return false;
1478 }
1479
1480 int intel_pinctrl_suspend(struct device *dev)
1481 {
1482         struct platform_device *pdev = to_platform_device(dev);
1483         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1484         struct intel_community_context *communities;
1485         struct intel_pad_context *pads;
1486         int i;
1487
1488         pads = pctrl->context.pads;
1489         for (i = 0; i < pctrl->soc->npins; i++) {
1490                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1491                 void __iomem *padcfg;
1492                 u32 val;
1493
1494                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1495                         continue;
1496
1497                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1498                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1499                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1500                 pads[i].padcfg1 = val;
1501
1502                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1503                 if (padcfg)
1504                         pads[i].padcfg2 = readl(padcfg);
1505         }
1506
1507         communities = pctrl->context.communities;
1508         for (i = 0; i < pctrl->ncommunities; i++) {
1509                 struct intel_community *community = &pctrl->communities[i];
1510                 void __iomem *base;
1511                 unsigned int gpp;
1512
1513                 base = community->regs + community->ie_offset;
1514                 for (gpp = 0; gpp < community->ngpps; gpp++)
1515                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1516         }
1517
1518         return 0;
1519 }
1520 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1521
1522 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1523 {
1524         size_t i;
1525
1526         for (i = 0; i < pctrl->ncommunities; i++) {
1527                 const struct intel_community *community;
1528                 void __iomem *base;
1529                 unsigned int gpp;
1530
1531                 community = &pctrl->communities[i];
1532                 base = community->regs;
1533
1534                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1535                         /* Mask and clear all interrupts */
1536                         writel(0, base + community->ie_offset + gpp * 4);
1537                         writel(0xffff, base + community->is_offset + gpp * 4);
1538                 }
1539         }
1540 }
1541
1542 int intel_pinctrl_resume(struct device *dev)
1543 {
1544         struct platform_device *pdev = to_platform_device(dev);
1545         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1546         const struct intel_community_context *communities;
1547         const struct intel_pad_context *pads;
1548         int i;
1549
1550         /* Mask all interrupts */
1551         intel_gpio_irq_init(pctrl);
1552
1553         pads = pctrl->context.pads;
1554         for (i = 0; i < pctrl->soc->npins; i++) {
1555                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1556                 void __iomem *padcfg;
1557                 u32 val;
1558
1559                 if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1560                       /*
1561                        * If the firmware mangled the register contents too much,
1562                        * check the saved value for the Direct IRQ mode.
1563                        */
1564                       __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1565                         continue;
1566
1567                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1568                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1569                 if (val != pads[i].padcfg0) {
1570                         writel(pads[i].padcfg0, padcfg);
1571                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1572                                 desc->number, readl(padcfg));
1573                 }
1574
1575                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1576                 val = readl(padcfg);
1577                 if (val != pads[i].padcfg1) {
1578                         writel(pads[i].padcfg1, padcfg);
1579                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1580                                 desc->number, readl(padcfg));
1581                 }
1582
1583                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1584                 if (padcfg) {
1585                         val = readl(padcfg);
1586                         if (val != pads[i].padcfg2) {
1587                                 writel(pads[i].padcfg2, padcfg);
1588                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1589                                         desc->number, readl(padcfg));
1590                         }
1591                 }
1592         }
1593
1594         communities = pctrl->context.communities;
1595         for (i = 0; i < pctrl->ncommunities; i++) {
1596                 struct intel_community *community = &pctrl->communities[i];
1597                 void __iomem *base;
1598                 unsigned int gpp;
1599
1600                 base = community->regs + community->ie_offset;
1601                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1602                         writel(communities[i].intmask[gpp], base + gpp * 4);
1603                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1604                                 readl(base + gpp * 4));
1605                 }
1606         }
1607
1608         return 0;
1609 }
1610 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1611 #endif
1612
1613 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1614 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1615 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1616 MODULE_LICENSE("GPL v2");