1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #include <linux/acpi.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/time.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-intel.h"
27 /* Offset from regs */
29 #define REVID_SHIFT 16
30 #define REVID_MASK GENMASK(31, 16)
33 #define CAPLIST_ID_SHIFT 16
34 #define CAPLIST_ID_MASK GENMASK(23, 16)
35 #define CAPLIST_ID_GPIO_HW_INFO 1
36 #define CAPLIST_ID_PWM 2
37 #define CAPLIST_ID_BLINK 3
38 #define CAPLIST_ID_EXP 4
39 #define CAPLIST_NEXT_SHIFT 0
40 #define CAPLIST_NEXT_MASK GENMASK(15, 0)
45 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
46 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
47 #define PADOWN_GPP(p) ((p) / 8)
49 /* Offset from pad_regs */
51 #define PADCFG0_RXEVCFG_SHIFT 25
52 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
53 #define PADCFG0_RXEVCFG_LEVEL 0
54 #define PADCFG0_RXEVCFG_EDGE 1
55 #define PADCFG0_RXEVCFG_DISABLED 2
56 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
57 #define PADCFG0_PREGFRXSEL BIT(24)
58 #define PADCFG0_RXINV BIT(23)
59 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
60 #define PADCFG0_GPIROUTSCI BIT(19)
61 #define PADCFG0_GPIROUTSMI BIT(18)
62 #define PADCFG0_GPIROUTNMI BIT(17)
63 #define PADCFG0_PMODE_SHIFT 10
64 #define PADCFG0_PMODE_MASK GENMASK(13, 10)
65 #define PADCFG0_PMODE_GPIO 0
66 #define PADCFG0_GPIORXDIS BIT(9)
67 #define PADCFG0_GPIOTXDIS BIT(8)
68 #define PADCFG0_GPIORXSTATE BIT(1)
69 #define PADCFG0_GPIOTXSTATE BIT(0)
72 #define PADCFG1_TERM_UP BIT(13)
73 #define PADCFG1_TERM_SHIFT 10
74 #define PADCFG1_TERM_MASK GENMASK(12, 10)
75 #define PADCFG1_TERM_20K BIT(2)
76 #define PADCFG1_TERM_5K BIT(1)
77 #define PADCFG1_TERM_1K BIT(0)
78 #define PADCFG1_TERM_833 (BIT(1) | BIT(0))
81 #define PADCFG2_DEBEN BIT(0)
82 #define PADCFG2_DEBOUNCE_SHIFT 1
83 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
85 #define DEBOUNCE_PERIOD_NSEC 31250
87 struct intel_pad_context {
93 struct intel_community_context {
98 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
99 #define padgroup_offset(g, p) ((p) - (g)->base)
101 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
104 struct intel_community *community;
107 for (i = 0; i < pctrl->ncommunities; i++) {
108 community = &pctrl->communities[i];
109 if (pin >= community->pin_base &&
110 pin < community->pin_base + community->npins)
114 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
118 static const struct intel_padgroup *
119 intel_community_get_padgroup(const struct intel_community *community,
124 for (i = 0; i < community->ngpps; i++) {
125 const struct intel_padgroup *padgrp = &community->gpps[i];
127 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
134 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
135 unsigned int pin, unsigned int reg)
137 const struct intel_community *community;
141 community = intel_get_community(pctrl, pin);
145 padno = pin_to_padno(community, pin);
146 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
148 if (reg >= nregs * 4)
151 return community->pad_regs + reg + padno * nregs * 4;
154 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
156 const struct intel_community *community;
157 const struct intel_padgroup *padgrp;
158 unsigned int gpp, offset, gpp_offset;
159 void __iomem *padown;
161 community = intel_get_community(pctrl, pin);
164 if (!community->padown_offset)
167 padgrp = intel_community_get_padgroup(community, pin);
171 gpp_offset = padgroup_offset(padgrp, pin);
172 gpp = PADOWN_GPP(gpp_offset);
173 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
174 padown = community->regs + offset;
176 return !(readl(padown) & PADOWN_MASK(gpp_offset));
179 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
181 const struct intel_community *community;
182 const struct intel_padgroup *padgrp;
183 unsigned int offset, gpp_offset;
184 void __iomem *hostown;
186 community = intel_get_community(pctrl, pin);
189 if (!community->hostown_offset)
192 padgrp = intel_community_get_padgroup(community, pin);
196 gpp_offset = padgroup_offset(padgrp, pin);
197 offset = community->hostown_offset + padgrp->reg_num * 4;
198 hostown = community->regs + offset;
200 return !(readl(hostown) & BIT(gpp_offset));
204 * enum - Locking variants of the pad configuration
206 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers
207 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
208 * @PAD_LOCKED_TX: pad configuration TX state is locked
209 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
211 * Locking is considered as read-only mode for corresponding registers and
212 * their respective fields. That said, TX state bit is locked separately from
213 * the main locking scheme.
219 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
222 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
224 struct intel_community *community;
225 const struct intel_padgroup *padgrp;
226 unsigned int offset, gpp_offset;
228 int ret = PAD_UNLOCKED;
230 community = intel_get_community(pctrl, pin);
232 return PAD_LOCKED_FULL;
233 if (!community->padcfglock_offset)
236 padgrp = intel_community_get_padgroup(community, pin);
238 return PAD_LOCKED_FULL;
240 gpp_offset = padgroup_offset(padgrp, pin);
243 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
244 * the pad is considered unlocked. Any other case means that it is
245 * either fully or partially locked.
247 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
248 value = readl(community->regs + offset);
249 if (value & BIT(gpp_offset))
252 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
253 value = readl(community->regs + offset);
254 if (value & BIT(gpp_offset))
255 ret |= PAD_LOCKED_TX;
260 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
262 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
265 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
267 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
270 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
272 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
274 return pctrl->soc->ngroups;
277 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
280 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
282 return pctrl->soc->groups[group].name;
285 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
286 const unsigned int **pins, unsigned int *npins)
288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
290 *pins = pctrl->soc->groups[group].pins;
291 *npins = pctrl->soc->groups[group].npins;
295 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
298 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
299 void __iomem *padcfg;
300 u32 cfg0, cfg1, mode;
304 if (!intel_pad_owned_by_host(pctrl, pin)) {
305 seq_puts(s, "not available");
309 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
310 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
312 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
313 if (mode == PADCFG0_PMODE_GPIO)
314 seq_puts(s, "GPIO ");
316 seq_printf(s, "mode %d ", mode);
318 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
320 /* Dump the additional PADCFG registers if available */
321 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
323 seq_printf(s, " 0x%08x", readl(padcfg));
325 locked = intel_pad_locked(pctrl, pin);
326 acpi = intel_pad_acpi_mode(pctrl, pin);
328 if (locked || acpi) {
331 seq_puts(s, "LOCKED");
332 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
334 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
335 seq_puts(s, " full");
346 static const struct pinctrl_ops intel_pinctrl_ops = {
347 .get_groups_count = intel_get_groups_count,
348 .get_group_name = intel_get_group_name,
349 .get_group_pins = intel_get_group_pins,
350 .pin_dbg_show = intel_pin_dbg_show,
353 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
355 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
357 return pctrl->soc->nfunctions;
360 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
361 unsigned int function)
363 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
365 return pctrl->soc->functions[function].name;
368 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
369 unsigned int function,
370 const char * const **groups,
371 unsigned int * const ngroups)
373 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
375 *groups = pctrl->soc->functions[function].groups;
376 *ngroups = pctrl->soc->functions[function].ngroups;
380 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
381 unsigned int function, unsigned int group)
383 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
384 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
388 raw_spin_lock_irqsave(&pctrl->lock, flags);
391 * All pins in the groups needs to be accessible and writable
392 * before we can enable the mux for this group.
394 for (i = 0; i < grp->npins; i++) {
395 if (!intel_pad_usable(pctrl, grp->pins[i])) {
396 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
401 /* Now enable the mux setting for each pin in the group */
402 for (i = 0; i < grp->npins; i++) {
403 void __iomem *padcfg0;
406 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
407 value = readl(padcfg0);
409 value &= ~PADCFG0_PMODE_MASK;
412 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
414 value |= grp->mode << PADCFG0_PMODE_SHIFT;
416 writel(value, padcfg0);
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
424 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
428 value = readl(padcfg0);
430 value &= ~PADCFG0_GPIORXDIS;
431 value |= PADCFG0_GPIOTXDIS;
433 value &= ~PADCFG0_GPIOTXDIS;
434 value |= PADCFG0_GPIORXDIS;
436 writel(value, padcfg0);
439 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
441 return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
444 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
448 value = readl(padcfg0);
450 /* Put the pad into GPIO mode */
451 value &= ~PADCFG0_PMODE_MASK;
452 value |= PADCFG0_PMODE_GPIO;
454 /* Disable TX buffer and enable RX (this will be input) */
455 value &= ~PADCFG0_GPIORXDIS;
456 value |= PADCFG0_GPIOTXDIS;
458 /* Disable SCI/SMI/NMI generation */
459 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
460 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
462 writel(value, padcfg0);
465 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
466 struct pinctrl_gpio_range *range,
469 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
470 void __iomem *padcfg0;
473 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
475 raw_spin_lock_irqsave(&pctrl->lock, flags);
477 if (!intel_pad_owned_by_host(pctrl, pin)) {
478 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
482 if (!intel_pad_is_unlocked(pctrl, pin)) {
483 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
488 * If pin is already configured in GPIO mode, we assume that
489 * firmware provides correct settings. In such case we avoid
490 * potential glitches on the pin. Otherwise, for the pin in
491 * alternative mode, consumer has to supply respective flags.
493 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
494 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
498 intel_gpio_set_gpio_mode(padcfg0);
500 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
505 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
506 struct pinctrl_gpio_range *range,
507 unsigned int pin, bool input)
509 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
510 void __iomem *padcfg0;
513 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
515 raw_spin_lock_irqsave(&pctrl->lock, flags);
516 __intel_gpio_set_direction(padcfg0, input);
517 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
522 static const struct pinmux_ops intel_pinmux_ops = {
523 .get_functions_count = intel_get_functions_count,
524 .get_function_name = intel_get_function_name,
525 .get_function_groups = intel_get_function_groups,
526 .set_mux = intel_pinmux_set_mux,
527 .gpio_request_enable = intel_gpio_request_enable,
528 .gpio_set_direction = intel_gpio_set_direction,
531 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
532 enum pin_config_param param, u32 *arg)
534 const struct intel_community *community;
535 void __iomem *padcfg1;
539 community = intel_get_community(pctrl, pin);
540 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
542 raw_spin_lock_irqsave(&pctrl->lock, flags);
543 value = readl(padcfg1);
544 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
546 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
549 case PIN_CONFIG_BIAS_DISABLE:
554 case PIN_CONFIG_BIAS_PULL_UP:
555 if (!term || !(value & PADCFG1_TERM_UP))
559 case PADCFG1_TERM_833:
562 case PADCFG1_TERM_1K:
565 case PADCFG1_TERM_5K:
568 case PADCFG1_TERM_20K:
575 case PIN_CONFIG_BIAS_PULL_DOWN:
576 if (!term || value & PADCFG1_TERM_UP)
580 case PADCFG1_TERM_833:
581 if (!(community->features & PINCTRL_FEATURE_1K_PD))
585 case PADCFG1_TERM_1K:
586 if (!(community->features & PINCTRL_FEATURE_1K_PD))
590 case PADCFG1_TERM_5K:
593 case PADCFG1_TERM_20K:
607 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
608 enum pin_config_param param, u32 *arg)
610 void __iomem *padcfg2;
615 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
619 raw_spin_lock_irqsave(&pctrl->lock, flags);
620 value2 = readl(padcfg2);
621 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
622 if (!(value2 & PADCFG2_DEBEN))
625 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
626 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
631 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
632 unsigned long *config)
634 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
635 enum pin_config_param param = pinconf_to_config_param(*config);
639 if (!intel_pad_owned_by_host(pctrl, pin))
643 case PIN_CONFIG_BIAS_DISABLE:
644 case PIN_CONFIG_BIAS_PULL_UP:
645 case PIN_CONFIG_BIAS_PULL_DOWN:
646 ret = intel_config_get_pull(pctrl, pin, param, &arg);
651 case PIN_CONFIG_INPUT_DEBOUNCE:
652 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
661 *config = pinconf_to_config_packed(param, arg);
665 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
666 unsigned long config)
668 unsigned int param = pinconf_to_config_param(config);
669 unsigned int arg = pinconf_to_config_argument(config);
670 const struct intel_community *community;
671 void __iomem *padcfg1;
676 community = intel_get_community(pctrl, pin);
677 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
679 raw_spin_lock_irqsave(&pctrl->lock, flags);
681 value = readl(padcfg1);
684 case PIN_CONFIG_BIAS_DISABLE:
685 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
688 case PIN_CONFIG_BIAS_PULL_UP:
689 value &= ~PADCFG1_TERM_MASK;
691 value |= PADCFG1_TERM_UP;
693 /* Set default strength value in case none is given */
699 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
702 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
705 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
708 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
716 case PIN_CONFIG_BIAS_PULL_DOWN:
717 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
719 /* Set default strength value in case none is given */
725 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
728 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
731 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
735 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
738 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
742 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
752 writel(value, padcfg1);
754 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
759 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
760 unsigned int pin, unsigned int debounce)
762 void __iomem *padcfg0, *padcfg2;
766 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
770 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
772 raw_spin_lock_irqsave(&pctrl->lock, flags);
774 value0 = readl(padcfg0);
775 value2 = readl(padcfg2);
777 /* Disable glitch filter and debouncer */
778 value0 &= ~PADCFG0_PREGFRXSEL;
779 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
784 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
785 if (v < 3 || v > 15) {
786 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
790 /* Enable glitch filter and debouncer */
791 value0 |= PADCFG0_PREGFRXSEL;
792 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
793 value2 |= PADCFG2_DEBEN;
796 writel(value0, padcfg0);
797 writel(value2, padcfg2);
799 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
804 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
805 unsigned long *configs, unsigned int nconfigs)
807 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
810 if (!intel_pad_usable(pctrl, pin))
813 for (i = 0; i < nconfigs; i++) {
814 switch (pinconf_to_config_param(configs[i])) {
815 case PIN_CONFIG_BIAS_DISABLE:
816 case PIN_CONFIG_BIAS_PULL_UP:
817 case PIN_CONFIG_BIAS_PULL_DOWN:
818 ret = intel_config_set_pull(pctrl, pin, configs[i]);
823 case PIN_CONFIG_INPUT_DEBOUNCE:
824 ret = intel_config_set_debounce(pctrl, pin,
825 pinconf_to_config_argument(configs[i]));
838 static const struct pinconf_ops intel_pinconf_ops = {
840 .pin_config_get = intel_config_get,
841 .pin_config_set = intel_config_set,
844 static const struct pinctrl_desc intel_pinctrl_desc = {
845 .pctlops = &intel_pinctrl_ops,
846 .pmxops = &intel_pinmux_ops,
847 .confops = &intel_pinconf_ops,
848 .owner = THIS_MODULE,
852 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
853 * @pctrl: Pinctrl structure
854 * @offset: GPIO offset from gpiolib
855 * @community: Community is filled here if not %NULL
856 * @padgrp: Pad group is filled here if not %NULL
858 * When coming through gpiolib irqchip, the GPIO offset is not
859 * automatically translated to pinctrl pin number. This function can be
860 * used to find out the corresponding pinctrl pin.
862 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
863 const struct intel_community **community,
864 const struct intel_padgroup **padgrp)
868 for (i = 0; i < pctrl->ncommunities; i++) {
869 const struct intel_community *comm = &pctrl->communities[i];
872 for (j = 0; j < comm->ngpps; j++) {
873 const struct intel_padgroup *pgrp = &comm->gpps[j];
875 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
878 if (offset >= pgrp->gpio_base &&
879 offset < pgrp->gpio_base + pgrp->size) {
882 pin = pgrp->base + offset - pgrp->gpio_base;
897 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
898 * @pctrl: Pinctrl structure
901 * Translate the pin number of pinctrl to GPIO offset
903 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
905 const struct intel_community *community;
906 const struct intel_padgroup *padgrp;
908 community = intel_get_community(pctrl, pin);
912 padgrp = intel_community_get_padgroup(community, pin);
916 return pin - padgrp->base + padgrp->gpio_base;
919 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
921 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
926 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
930 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
934 padcfg0 = readl(reg);
935 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
936 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
938 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
941 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
944 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
950 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
954 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
958 raw_spin_lock_irqsave(&pctrl->lock, flags);
959 padcfg0 = readl(reg);
961 padcfg0 |= PADCFG0_GPIOTXSTATE;
963 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
964 writel(padcfg0, reg);
965 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
968 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
970 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
976 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
980 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
984 raw_spin_lock_irqsave(&pctrl->lock, flags);
985 padcfg0 = readl(reg);
986 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
987 if (padcfg0 & PADCFG0_PMODE_MASK)
990 if (padcfg0 & PADCFG0_GPIOTXDIS)
991 return GPIO_LINE_DIRECTION_IN;
993 return GPIO_LINE_DIRECTION_OUT;
996 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
998 return pinctrl_gpio_direction_input(chip->base + offset);
1001 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1004 intel_gpio_set(chip, offset, value);
1005 return pinctrl_gpio_direction_output(chip->base + offset);
1008 static const struct gpio_chip intel_gpio_chip = {
1009 .owner = THIS_MODULE,
1010 .request = gpiochip_generic_request,
1011 .free = gpiochip_generic_free,
1012 .get_direction = intel_gpio_get_direction,
1013 .direction_input = intel_gpio_direction_input,
1014 .direction_output = intel_gpio_direction_output,
1015 .get = intel_gpio_get,
1016 .set = intel_gpio_set,
1017 .set_config = gpiochip_generic_config,
1020 static void intel_gpio_irq_ack(struct irq_data *d)
1022 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1023 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1024 const struct intel_community *community;
1025 const struct intel_padgroup *padgrp;
1028 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1030 unsigned int gpp, gpp_offset, is_offset;
1032 gpp = padgrp->reg_num;
1033 gpp_offset = padgroup_offset(padgrp, pin);
1034 is_offset = community->is_offset + gpp * 4;
1036 raw_spin_lock(&pctrl->lock);
1037 writel(BIT(gpp_offset), community->regs + is_offset);
1038 raw_spin_unlock(&pctrl->lock);
1042 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1044 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1045 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1046 const struct intel_community *community;
1047 const struct intel_padgroup *padgrp;
1050 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1052 unsigned int gpp, gpp_offset;
1053 unsigned long flags;
1054 void __iomem *reg, *is;
1057 gpp = padgrp->reg_num;
1058 gpp_offset = padgroup_offset(padgrp, pin);
1060 reg = community->regs + community->ie_offset + gpp * 4;
1061 is = community->regs + community->is_offset + gpp * 4;
1063 raw_spin_lock_irqsave(&pctrl->lock, flags);
1065 /* Clear interrupt status first to avoid unexpected interrupt */
1066 writel(BIT(gpp_offset), is);
1070 value &= ~BIT(gpp_offset);
1072 value |= BIT(gpp_offset);
1074 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1078 static void intel_gpio_irq_mask(struct irq_data *d)
1080 intel_gpio_irq_mask_unmask(d, true);
1083 static void intel_gpio_irq_unmask(struct irq_data *d)
1085 intel_gpio_irq_mask_unmask(d, false);
1088 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1090 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1091 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1092 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1093 unsigned long flags;
1097 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1102 * If the pin is in ACPI mode it is still usable as a GPIO but it
1103 * cannot be used as IRQ because GPI_IS status bit will not be
1104 * updated by the host controller hardware.
1106 if (intel_pad_acpi_mode(pctrl, pin)) {
1107 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1111 raw_spin_lock_irqsave(&pctrl->lock, flags);
1113 intel_gpio_set_gpio_mode(reg);
1117 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1119 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1120 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1121 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1122 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1123 value |= PADCFG0_RXINV;
1124 } else if (type & IRQ_TYPE_EDGE_RISING) {
1125 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1126 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1127 if (type & IRQ_TYPE_LEVEL_LOW)
1128 value |= PADCFG0_RXINV;
1130 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1135 if (type & IRQ_TYPE_EDGE_BOTH)
1136 irq_set_handler_locked(d, handle_edge_irq);
1137 else if (type & IRQ_TYPE_LEVEL_MASK)
1138 irq_set_handler_locked(d, handle_level_irq);
1140 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1145 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1148 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1149 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1152 enable_irq_wake(pctrl->irq);
1154 disable_irq_wake(pctrl->irq);
1156 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1160 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1161 const struct intel_community *community)
1163 struct gpio_chip *gc = &pctrl->chip;
1167 for (gpp = 0; gpp < community->ngpps; gpp++) {
1168 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1169 unsigned long pending, enabled, gpp_offset;
1171 raw_spin_lock(&pctrl->lock);
1173 pending = readl(community->regs + community->is_offset +
1174 padgrp->reg_num * 4);
1175 enabled = readl(community->regs + community->ie_offset +
1176 padgrp->reg_num * 4);
1178 raw_spin_unlock(&pctrl->lock);
1180 /* Only interrupts that are enabled */
1183 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1186 irq = irq_find_mapping(gc->irq.domain,
1187 padgrp->gpio_base + gpp_offset);
1188 generic_handle_irq(irq);
1191 ret += pending ? 1 : 0;
1197 static irqreturn_t intel_gpio_irq(int irq, void *data)
1199 const struct intel_community *community;
1200 struct intel_pinctrl *pctrl = data;
1204 /* Need to check all communities for pending interrupts */
1205 for (i = 0; i < pctrl->ncommunities; i++) {
1206 community = &pctrl->communities[i];
1207 ret += intel_gpio_community_irq_handler(pctrl, community);
1210 return IRQ_RETVAL(ret);
1213 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1217 for (i = 0; i < pctrl->ncommunities; i++) {
1218 const struct intel_community *community;
1222 community = &pctrl->communities[i];
1223 base = community->regs;
1225 for (gpp = 0; gpp < community->ngpps; gpp++) {
1226 /* Mask and clear all interrupts */
1227 writel(0, base + community->ie_offset + gpp * 4);
1228 writel(0xffff, base + community->is_offset + gpp * 4);
1233 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1235 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1238 * Make sure the interrupt lines are in a proper state before
1239 * further configuration.
1241 intel_gpio_irq_init(pctrl);
1246 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1247 const struct intel_community *community)
1251 for (i = 0; i < community->ngpps; i++) {
1252 const struct intel_padgroup *gpp = &community->gpps[i];
1254 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1257 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1258 gpp->gpio_base, gpp->base,
1267 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1269 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1272 for (i = 0; i < pctrl->ncommunities; i++) {
1273 struct intel_community *community = &pctrl->communities[i];
1275 ret = intel_gpio_add_community_ranges(pctrl, community);
1277 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1285 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1287 const struct intel_community *community;
1288 unsigned int ngpio = 0;
1291 for (i = 0; i < pctrl->ncommunities; i++) {
1292 community = &pctrl->communities[i];
1293 for (j = 0; j < community->ngpps; j++) {
1294 const struct intel_padgroup *gpp = &community->gpps[j];
1296 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1299 if (gpp->gpio_base + gpp->size > ngpio)
1300 ngpio = gpp->gpio_base + gpp->size;
1307 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1310 struct gpio_irq_chip *girq;
1312 pctrl->chip = intel_gpio_chip;
1314 /* Setup GPIO chip */
1315 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1316 pctrl->chip.label = dev_name(pctrl->dev);
1317 pctrl->chip.parent = pctrl->dev;
1318 pctrl->chip.base = -1;
1319 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1322 /* Setup IRQ chip */
1323 pctrl->irqchip.name = dev_name(pctrl->dev);
1324 pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1325 pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1326 pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1327 pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1328 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1329 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1332 * On some platforms several GPIO controllers share the same interrupt
1335 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1336 IRQF_SHARED | IRQF_NO_THREAD,
1337 dev_name(pctrl->dev), pctrl);
1339 dev_err(pctrl->dev, "failed to request interrupt\n");
1343 girq = &pctrl->chip.irq;
1344 girq->chip = &pctrl->irqchip;
1345 /* This will let us handle the IRQ in the driver */
1346 girq->parent_handler = NULL;
1347 girq->num_parents = 0;
1348 girq->default_type = IRQ_TYPE_NONE;
1349 girq->handler = handle_bad_irq;
1350 girq->init_hw = intel_gpio_irq_init_hw;
1352 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1354 dev_err(pctrl->dev, "failed to register gpiochip\n");
1361 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1362 struct intel_community *community)
1364 struct intel_padgroup *gpps;
1365 unsigned int padown_num = 0;
1366 size_t i, ngpps = community->ngpps;
1368 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1372 for (i = 0; i < ngpps; i++) {
1373 gpps[i] = community->gpps[i];
1375 if (gpps[i].size > 32)
1378 /* Special treatment for GPIO base */
1379 switch (gpps[i].gpio_base) {
1380 case INTEL_GPIO_BASE_MATCH:
1381 gpps[i].gpio_base = gpps[i].base;
1383 case INTEL_GPIO_BASE_ZERO:
1384 gpps[i].gpio_base = 0;
1386 case INTEL_GPIO_BASE_NOMAP:
1392 gpps[i].padown_num = padown_num;
1393 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1396 community->gpps = gpps;
1401 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1402 struct intel_community *community)
1404 struct intel_padgroup *gpps;
1405 unsigned int npins = community->npins;
1406 unsigned int padown_num = 0;
1407 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1409 if (community->gpp_size > 32)
1412 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1416 for (i = 0; i < ngpps; i++) {
1417 unsigned int gpp_size = community->gpp_size;
1419 gpps[i].reg_num = i;
1420 gpps[i].base = community->pin_base + i * gpp_size;
1421 gpps[i].size = min(gpp_size, npins);
1422 npins -= gpps[i].size;
1424 gpps[i].gpio_base = gpps[i].base;
1425 gpps[i].padown_num = padown_num;
1428 * In older hardware the number of padown registers per
1429 * group is fixed regardless of the group size.
1431 if (community->gpp_num_padown_regs)
1432 padown_num += community->gpp_num_padown_regs;
1434 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1437 community->ngpps = ngpps;
1438 community->gpps = gpps;
1443 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1445 #ifdef CONFIG_PM_SLEEP
1446 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1447 struct intel_community_context *communities;
1448 struct intel_pad_context *pads;
1451 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1455 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1456 sizeof(*communities), GFP_KERNEL);
1461 for (i = 0; i < pctrl->ncommunities; i++) {
1462 struct intel_community *community = &pctrl->communities[i];
1463 u32 *intmask, *hostown;
1465 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1466 sizeof(*intmask), GFP_KERNEL);
1470 communities[i].intmask = intmask;
1472 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1473 sizeof(*hostown), GFP_KERNEL);
1477 communities[i].hostown = hostown;
1480 pctrl->context.pads = pads;
1481 pctrl->context.communities = communities;
1487 static int intel_pinctrl_probe(struct platform_device *pdev,
1488 const struct intel_pinctrl_soc_data *soc_data)
1490 struct intel_pinctrl *pctrl;
1493 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1497 pctrl->dev = &pdev->dev;
1498 pctrl->soc = soc_data;
1499 raw_spin_lock_init(&pctrl->lock);
1502 * Make a copy of the communities which we can use to hold pointers
1505 pctrl->ncommunities = pctrl->soc->ncommunities;
1506 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1507 sizeof(*pctrl->communities), GFP_KERNEL);
1508 if (!pctrl->communities)
1511 for (i = 0; i < pctrl->ncommunities; i++) {
1512 struct intel_community *community = &pctrl->communities[i];
1517 *community = pctrl->soc->communities[i];
1519 regs = devm_platform_ioremap_resource(pdev, community->barno);
1521 return PTR_ERR(regs);
1524 * Determine community features based on the revision.
1525 * A value of all ones means the device is not present.
1527 value = readl(regs + REVID);
1530 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1531 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1532 community->features |= PINCTRL_FEATURE_1K_PD;
1535 /* Determine community features based on the capabilities */
1538 value = readl(regs + offset);
1539 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1540 case CAPLIST_ID_GPIO_HW_INFO:
1541 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1543 case CAPLIST_ID_PWM:
1544 community->features |= PINCTRL_FEATURE_PWM;
1546 case CAPLIST_ID_BLINK:
1547 community->features |= PINCTRL_FEATURE_BLINK;
1549 case CAPLIST_ID_EXP:
1550 community->features |= PINCTRL_FEATURE_EXP;
1555 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1558 dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
1560 /* Read offset of the pad configuration registers */
1561 offset = readl(regs + PADBAR);
1563 community->regs = regs;
1564 community->pad_regs = regs + offset;
1566 if (community->gpps)
1567 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1569 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1574 irq = platform_get_irq(pdev, 0);
1578 ret = intel_pinctrl_pm_init(pctrl);
1582 pctrl->pctldesc = intel_pinctrl_desc;
1583 pctrl->pctldesc.name = dev_name(&pdev->dev);
1584 pctrl->pctldesc.pins = pctrl->soc->pins;
1585 pctrl->pctldesc.npins = pctrl->soc->npins;
1587 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1589 if (IS_ERR(pctrl->pctldev)) {
1590 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1591 return PTR_ERR(pctrl->pctldev);
1594 ret = intel_gpio_probe(pctrl, irq);
1598 platform_set_drvdata(pdev, pctrl);
1603 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1605 const struct intel_pinctrl_soc_data *data;
1607 data = device_get_match_data(&pdev->dev);
1611 return intel_pinctrl_probe(pdev, data);
1613 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1615 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1617 const struct intel_pinctrl_soc_data *data;
1619 data = intel_pinctrl_get_soc_data(pdev);
1621 return PTR_ERR(data);
1623 return intel_pinctrl_probe(pdev, data);
1625 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1627 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1629 const struct intel_pinctrl_soc_data *data = NULL;
1630 const struct intel_pinctrl_soc_data **table;
1631 struct acpi_device *adev;
1634 adev = ACPI_COMPANION(&pdev->dev);
1636 const void *match = device_get_match_data(&pdev->dev);
1638 table = (const struct intel_pinctrl_soc_data **)match;
1639 for (i = 0; table[i]; i++) {
1640 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1646 const struct platform_device_id *id;
1648 id = platform_get_device_id(pdev);
1650 return ERR_PTR(-ENODEV);
1652 table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1653 data = table[pdev->id];
1656 return data ?: ERR_PTR(-ENODATA);
1658 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
1660 #ifdef CONFIG_PM_SLEEP
1661 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1663 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1665 if (!pd || !intel_pad_usable(pctrl, pin))
1669 * Only restore the pin if it is actually in use by the kernel (or
1670 * by userspace). It is possible that some pins are used by the
1671 * BIOS during resume and those are not always locked down so leave
1674 if (pd->mux_owner || pd->gpio_owner ||
1675 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1681 int intel_pinctrl_suspend_noirq(struct device *dev)
1683 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1684 struct intel_community_context *communities;
1685 struct intel_pad_context *pads;
1688 pads = pctrl->context.pads;
1689 for (i = 0; i < pctrl->soc->npins; i++) {
1690 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1691 void __iomem *padcfg;
1694 if (!intel_pinctrl_should_save(pctrl, desc->number))
1697 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1698 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1699 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1700 pads[i].padcfg1 = val;
1702 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1704 pads[i].padcfg2 = readl(padcfg);
1707 communities = pctrl->context.communities;
1708 for (i = 0; i < pctrl->ncommunities; i++) {
1709 struct intel_community *community = &pctrl->communities[i];
1713 base = community->regs + community->ie_offset;
1714 for (gpp = 0; gpp < community->ngpps; gpp++)
1715 communities[i].intmask[gpp] = readl(base + gpp * 4);
1717 base = community->regs + community->hostown_offset;
1718 for (gpp = 0; gpp < community->ngpps; gpp++)
1719 communities[i].hostown[gpp] = readl(base + gpp * 4);
1724 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1726 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1732 updated = (curr & ~mask) | (value & mask);
1733 if (curr == updated)
1736 writel(updated, reg);
1740 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1741 void __iomem *base, unsigned int gpp, u32 saved)
1743 const struct intel_community *community = &pctrl->communities[c];
1744 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1745 struct device *dev = pctrl->dev;
1750 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1753 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1754 requested |= BIT(i);
1756 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1759 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1762 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1763 void __iomem *base, unsigned int gpp, u32 saved)
1765 struct device *dev = pctrl->dev;
1767 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1770 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1773 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1774 unsigned int reg, u32 saved)
1776 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1777 unsigned int n = reg / sizeof(u32);
1778 struct device *dev = pctrl->dev;
1779 void __iomem *padcfg;
1781 padcfg = intel_get_padcfg(pctrl, pin, reg);
1785 if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1788 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1791 int intel_pinctrl_resume_noirq(struct device *dev)
1793 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1794 const struct intel_community_context *communities;
1795 const struct intel_pad_context *pads;
1798 /* Mask all interrupts */
1799 intel_gpio_irq_init(pctrl);
1801 pads = pctrl->context.pads;
1802 for (i = 0; i < pctrl->soc->npins; i++) {
1803 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1805 if (!intel_pinctrl_should_save(pctrl, desc->number))
1808 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1809 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1810 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1813 communities = pctrl->context.communities;
1814 for (i = 0; i < pctrl->ncommunities; i++) {
1815 struct intel_community *community = &pctrl->communities[i];
1819 base = community->regs + community->ie_offset;
1820 for (gpp = 0; gpp < community->ngpps; gpp++)
1821 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1823 base = community->regs + community->hostown_offset;
1824 for (gpp = 0; gpp < community->ngpps; gpp++)
1825 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1830 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1833 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1834 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1835 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1836 MODULE_LICENSE("GPL v2");