drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/log2.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/property.h>
  17 #include <linux/time.h>
  18
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23
  24 #include "../core.h"
  25 #include "pinctrl-intel.h"
  26
  27 /* Offset from regs */
  28 #define REVID                           0x000
  29 #define REVID_SHIFT                     16
  30 #define REVID_MASK                      GENMASK(31, 16)
  31
  32 #define PADBAR                          0x00c
  33
  34 #define PADOWN_BITS                     4
  35 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  36 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  37 #define PADOWN_GPP(p)                   ((p) / 8)
  38
  39 /* Offset from pad_regs */
  40 #define PADCFG0                         0x000
  41 #define PADCFG0_RXEVCFG_SHIFT           25
  42 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  43 #define PADCFG0_RXEVCFG_LEVEL           0
  44 #define PADCFG0_RXEVCFG_EDGE            1
  45 #define PADCFG0_RXEVCFG_DISABLED        2
  46 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  47 #define PADCFG0_PREGFRXSEL              BIT(24)
  48 #define PADCFG0_RXINV                   BIT(23)
  49 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  50 #define PADCFG0_GPIROUTSCI              BIT(19)
  51 #define PADCFG0_GPIROUTSMI              BIT(18)
  52 #define PADCFG0_GPIROUTNMI              BIT(17)
  53 #define PADCFG0_PMODE_SHIFT             10
  54 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  55 #define PADCFG0_PMODE_GPIO              0
  56 #define PADCFG0_GPIORXDIS               BIT(9)
  57 #define PADCFG0_GPIOTXDIS               BIT(8)
  58 #define PADCFG0_GPIORXSTATE             BIT(1)
  59 #define PADCFG0_GPIOTXSTATE             BIT(0)
  60
  61 #define PADCFG1                         0x004
  62 #define PADCFG1_TERM_UP                 BIT(13)
  63 #define PADCFG1_TERM_SHIFT              10
  64 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  65 #define PADCFG1_TERM_20K                BIT(2)
  66 #define PADCFG1_TERM_5K                 BIT(1)
  67 #define PADCFG1_TERM_1K                 BIT(0)
  68 #define PADCFG1_TERM_833                (BIT(1) | BIT(0))
  69
  70 #define PADCFG2                         0x008
  71 #define PADCFG2_DEBEN                   BIT(0)
  72 #define PADCFG2_DEBOUNCE_SHIFT          1
  73 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  74
  75 #define DEBOUNCE_PERIOD_NSEC            31250
  76
  77 struct intel_pad_context {
  78         u32 padcfg0;
  79         u32 padcfg1;
  80         u32 padcfg2;
  81 };
  82
  83 struct intel_community_context {
  84         u32 *intmask;
  85         u32 *hostown;
  86 };
  87
  88 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
  89 #define padgroup_offset(g, p)   ((p) - (g)->base)
  90
  91 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
  92                                                    unsigned int pin)
  93 {
  94         struct intel_community *community;
  95         int i;
  96
  97         for (i = 0; i < pctrl->ncommunities; i++) {
  98                 community = &pctrl->communities[i];
  99                 if (pin >= community->pin_base &&
 100                     pin < community->pin_base + community->npins)
 101                         return community;
 102         }
 103
 104         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 105         return NULL;
 106 }
 107
 108 static const struct intel_padgroup *
 109 intel_community_get_padgroup(const struct intel_community *community,
 110                              unsigned int pin)
 111 {
 112         int i;
 113
 114         for (i = 0; i < community->ngpps; i++) {
 115                 const struct intel_padgroup *padgrp = &community->gpps[i];
 116
 117                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 118                         return padgrp;
 119         }
 120
 121         return NULL;
 122 }
 123
 124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 125                                       unsigned int pin, unsigned int reg)
 126 {
 127         const struct intel_community *community;
 128         unsigned int padno;
 129         size_t nregs;
 130
 131         community = intel_get_community(pctrl, pin);
 132         if (!community)
 133                 return NULL;
 134
 135         padno = pin_to_padno(community, pin);
 136         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 137
 138         if (reg >= nregs * 4)
 139                 return NULL;
 140
 141         return community->pad_regs + reg + padno * nregs * 4;
 142 }
 143
 144 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 145 {
 146         const struct intel_community *community;
 147         const struct intel_padgroup *padgrp;
 148         unsigned int gpp, offset, gpp_offset;
 149         void __iomem *padown;
 150
 151         community = intel_get_community(pctrl, pin);
 152         if (!community)
 153                 return false;
 154         if (!community->padown_offset)
 155                 return true;
 156
 157         padgrp = intel_community_get_padgroup(community, pin);
 158         if (!padgrp)
 159                 return false;
 160
 161         gpp_offset = padgroup_offset(padgrp, pin);
 162         gpp = PADOWN_GPP(gpp_offset);
 163         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 164         padown = community->regs + offset;
 165
 166         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 167 }
 168
 169 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 170 {
 171         const struct intel_community *community;
 172         const struct intel_padgroup *padgrp;
 173         unsigned int offset, gpp_offset;
 174         void __iomem *hostown;
 175
 176         community = intel_get_community(pctrl, pin);
 177         if (!community)
 178                 return true;
 179         if (!community->hostown_offset)
 180                 return false;
 181
 182         padgrp = intel_community_get_padgroup(community, pin);
 183         if (!padgrp)
 184                 return true;
 185
 186         gpp_offset = padgroup_offset(padgrp, pin);
 187         offset = community->hostown_offset + padgrp->reg_num * 4;
 188         hostown = community->regs + offset;
 189
 190         return !(readl(hostown) & BIT(gpp_offset));
 191 }
 192
 193 /**
 194  * enum - Locking variants of the pad configuration
 195  *
 196  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 197  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 198  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 199  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 200  *
 201  * Locking is considered as read-only mode for corresponding registers and
 202  * their respective fields. That said, TX state bit is locked separately from
 203  * the main locking scheme.
 204  */
 205 enum {
 206         PAD_UNLOCKED    = 0,
 207         PAD_LOCKED      = 1,
 208         PAD_LOCKED_TX   = 2,
 209         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 210 };
 211
 212 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 213 {
 214         struct intel_community *community;
 215         const struct intel_padgroup *padgrp;
 216         unsigned int offset, gpp_offset;
 217         u32 value;
 218         int ret = PAD_UNLOCKED;
 219
 220         community = intel_get_community(pctrl, pin);
 221         if (!community)
 222                 return PAD_LOCKED_FULL;
 223         if (!community->padcfglock_offset)
 224                 return PAD_UNLOCKED;
 225
 226         padgrp = intel_community_get_padgroup(community, pin);
 227         if (!padgrp)
 228                 return PAD_LOCKED_FULL;
 229
 230         gpp_offset = padgroup_offset(padgrp, pin);
 231
 232         /*
 233          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 234          * the pad is considered unlocked. Any other case means that it is
 235          * either fully or partially locked.
 236          */
 237         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 238         value = readl(community->regs + offset);
 239         if (value & BIT(gpp_offset))
 240                 ret |= PAD_LOCKED;
 241
 242         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 243         value = readl(community->regs + offset);
 244         if (value & BIT(gpp_offset))
 245                 ret |= PAD_LOCKED_TX;
 246
 247         return ret;
 248 }
 249
 250 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
 251 {
 252         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 253 }
 254
 255 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 256 {
 257         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 258 }
 259
 260 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 261 {
 262         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 263
 264         return pctrl->soc->ngroups;
 265 }
 266
 267 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 268                                       unsigned int group)
 269 {
 270         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 271
 272         return pctrl->soc->groups[group].name;
 273 }
 274
 275 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 276                               const unsigned int **pins, unsigned int *npins)
 277 {
 278         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 279
 280         *pins = pctrl->soc->groups[group].pins;
 281         *npins = pctrl->soc->groups[group].npins;
 282         return 0;
 283 }
 284
 285 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 286                                unsigned int pin)
 287 {
 288         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 289         void __iomem *padcfg;
 290         u32 cfg0, cfg1, mode;
 291         int locked;
 292         bool acpi;
 293
 294         if (!intel_pad_owned_by_host(pctrl, pin)) {
 295                 seq_puts(s, "not available");
 296                 return;
 297         }
 298
 299         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 300         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 301
 302         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 303         if (mode == PADCFG0_PMODE_GPIO)
 304                 seq_puts(s, "GPIO ");
 305         else
 306                 seq_printf(s, "mode %d ", mode);
 307
 308         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 309
 310         /* Dump the additional PADCFG registers if available */
 311         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 312         if (padcfg)
 313                 seq_printf(s, " 0x%08x", readl(padcfg));
 314
 315         locked = intel_pad_locked(pctrl, pin);
 316         acpi = intel_pad_acpi_mode(pctrl, pin);
 317
 318         if (locked || acpi) {
 319                 seq_puts(s, " [");
 320                 if (locked)
 321                         seq_puts(s, "LOCKED");
 322                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 323                         seq_puts(s, " tx");
 324                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 325                         seq_puts(s, " full");
 326
 327                 if (locked && acpi)
 328                         seq_puts(s, ", ");
 329
 330                 if (acpi)
 331                         seq_puts(s, "ACPI");
 332                 seq_puts(s, "]");
 333         }
 334 }
 335
 336 static const struct pinctrl_ops intel_pinctrl_ops = {
 337         .get_groups_count = intel_get_groups_count,
 338         .get_group_name = intel_get_group_name,
 339         .get_group_pins = intel_get_group_pins,
 340         .pin_dbg_show = intel_pin_dbg_show,
 341 };
 342
 343 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 344 {
 345         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 346
 347         return pctrl->soc->nfunctions;
 348 }
 349
 350 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 351                                            unsigned int function)
 352 {
 353         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 354
 355         return pctrl->soc->functions[function].name;
 356 }
 357
 358 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 359                                      unsigned int function,
 360                                      const char * const **groups,
 361                                      unsigned int * const ngroups)
 362 {
 363         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 364
 365         *groups = pctrl->soc->functions[function].groups;
 366         *ngroups = pctrl->soc->functions[function].ngroups;
 367         return 0;
 368 }
 369
 370 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 371                                 unsigned int function, unsigned int group)
 372 {
 373         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 374         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 375         unsigned long flags;
 376         int i;
 377
 378         raw_spin_lock_irqsave(&pctrl->lock, flags);
 379
 380         /*
 381          * All pins in the groups needs to be accessible and writable
 382          * before we can enable the mux for this group.
 383          */
 384         for (i = 0; i < grp->npins; i++) {
 385                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 386                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 387                         return -EBUSY;
 388                 }
 389         }
 390
 391         /* Now enable the mux setting for each pin in the group */
 392         for (i = 0; i < grp->npins; i++) {
 393                 void __iomem *padcfg0;
 394                 u32 value;
 395
 396                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 397                 value = readl(padcfg0);
 398
 399                 value &= ~PADCFG0_PMODE_MASK;
 400
 401                 if (grp->modes)
 402                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 403                 else
 404                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 405
 406                 writel(value, padcfg0);
 407         }
 408
 409         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 410
 411         return 0;
 412 }
 413
 414 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 415 {
 416         u32 value;
 417
 418         value = readl(padcfg0);
 419         if (input) {
 420                 value &= ~PADCFG0_GPIORXDIS;
 421                 value |= PADCFG0_GPIOTXDIS;
 422         } else {
 423                 value &= ~PADCFG0_GPIOTXDIS;
 424                 value |= PADCFG0_GPIORXDIS;
 425         }
 426         writel(value, padcfg0);
 427 }
 428
 429 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 430 {
 431         return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 432 }
 433
 434 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 435 {
 436         u32 value;
 437
 438         value = readl(padcfg0);
 439
 440         /* Put the pad into GPIO mode */
 441         value &= ~PADCFG0_PMODE_MASK;
 442         value |= PADCFG0_PMODE_GPIO;
 443
 444         /* Disable TX buffer and enable RX (this will be input) */
 445         value &= ~PADCFG0_GPIORXDIS;
 446         value |= PADCFG0_GPIOTXDIS;
 447
 448         /* Disable SCI/SMI/NMI generation */
 449         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 450         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 451
 452         writel(value, padcfg0);
 453 }
 454
 455 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 456                                      struct pinctrl_gpio_range *range,
 457                                      unsigned int pin)
 458 {
 459         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 460         void __iomem *padcfg0;
 461         unsigned long flags;
 462
 463         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 464
 465         raw_spin_lock_irqsave(&pctrl->lock, flags);
 466
 467         if (!intel_pad_owned_by_host(pctrl, pin)) {
 468                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 469                 return -EBUSY;
 470         }
 471
 472         if (!intel_pad_is_unlocked(pctrl, pin)) {
 473                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 474                 return 0;
 475         }
 476
 477         /*
 478          * If pin is already configured in GPIO mode, we assume that
 479          * firmware provides correct settings. In such case we avoid
 480          * potential glitches on the pin. Otherwise, for the pin in
 481          * alternative mode, consumer has to supply respective flags.
 482          */
 483         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
 484                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 485                 return 0;
 486         }
 487
 488         intel_gpio_set_gpio_mode(padcfg0);
 489
 490         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 491
 492         return 0;
 493 }
 494
 495 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 496                                     struct pinctrl_gpio_range *range,
 497                                     unsigned int pin, bool input)
 498 {
 499         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 500         void __iomem *padcfg0;
 501         unsigned long flags;
 502
 503         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 504
 505         raw_spin_lock_irqsave(&pctrl->lock, flags);
 506         __intel_gpio_set_direction(padcfg0, input);
 507         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 508
 509         return 0;
 510 }
 511
 512 static const struct pinmux_ops intel_pinmux_ops = {
 513         .get_functions_count = intel_get_functions_count,
 514         .get_function_name = intel_get_function_name,
 515         .get_function_groups = intel_get_function_groups,
 516         .set_mux = intel_pinmux_set_mux,
 517         .gpio_request_enable = intel_gpio_request_enable,
 518         .gpio_set_direction = intel_gpio_set_direction,
 519 };
 520
 521 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 522                                  enum pin_config_param param, u32 *arg)
 523 {
 524         const struct intel_community *community;
 525         void __iomem *padcfg1;
 526         unsigned long flags;
 527         u32 value, term;
 528
 529         community = intel_get_community(pctrl, pin);
 530         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 531
 532         raw_spin_lock_irqsave(&pctrl->lock, flags);
 533         value = readl(padcfg1);
 534         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 535
 536         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 537
 538         switch (param) {
 539         case PIN_CONFIG_BIAS_DISABLE:
 540                 if (term)
 541                         return -EINVAL;
 542                 break;
 543
 544         case PIN_CONFIG_BIAS_PULL_UP:
 545                 if (!term || !(value & PADCFG1_TERM_UP))
 546                         return -EINVAL;
 547
 548                 switch (term) {
 549                 case PADCFG1_TERM_833:
 550                         *arg = 833;
 551                         break;
 552                 case PADCFG1_TERM_1K:
 553                         *arg = 1000;
 554                         break;
 555                 case PADCFG1_TERM_5K:
 556                         *arg = 5000;
 557                         break;
 558                 case PADCFG1_TERM_20K:
 559                         *arg = 20000;
 560                         break;
 561                 }
 562
 563                 break;
 564
 565         case PIN_CONFIG_BIAS_PULL_DOWN:
 566                 if (!term || value & PADCFG1_TERM_UP)
 567                         return -EINVAL;
 568
 569                 switch (term) {
 570                 case PADCFG1_TERM_833:
 571                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 572                                 return -EINVAL;
 573                         *arg = 833;
 574                         break;
 575                 case PADCFG1_TERM_1K:
 576                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 577                                 return -EINVAL;
 578                         *arg = 1000;
 579                         break;
 580                 case PADCFG1_TERM_5K:
 581                         *arg = 5000;
 582                         break;
 583                 case PADCFG1_TERM_20K:
 584                         *arg = 20000;
 585                         break;
 586                 }
 587
 588                 break;
 589
 590         default:
 591                 return -EINVAL;
 592         }
 593
 594         return 0;
 595 }
 596
 597 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
 598                                      enum pin_config_param param, u32 *arg)
 599 {
 600         void __iomem *padcfg2;
 601         unsigned long flags;
 602         unsigned long v;
 603         u32 value2;
 604
 605         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 606         if (!padcfg2)
 607                 return -ENOTSUPP;
 608
 609         raw_spin_lock_irqsave(&pctrl->lock, flags);
 610         value2 = readl(padcfg2);
 611         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 612         if (!(value2 & PADCFG2_DEBEN))
 613                 return -EINVAL;
 614
 615         v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 616         *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 617
 618         return 0;
 619 }
 620
 621 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 622                             unsigned long *config)
 623 {
 624         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 625         enum pin_config_param param = pinconf_to_config_param(*config);
 626         u32 arg = 0;
 627         int ret;
 628
 629         if (!intel_pad_owned_by_host(pctrl, pin))
 630                 return -ENOTSUPP;
 631
 632         switch (param) {
 633         case PIN_CONFIG_BIAS_DISABLE:
 634         case PIN_CONFIG_BIAS_PULL_UP:
 635         case PIN_CONFIG_BIAS_PULL_DOWN:
 636                 ret = intel_config_get_pull(pctrl, pin, param, &arg);
 637                 if (ret)
 638                         return ret;
 639                 break;
 640
 641         case PIN_CONFIG_INPUT_DEBOUNCE:
 642                 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
 643                 if (ret)
 644                         return ret;
 645                 break;
 646
 647         default:
 648                 return -ENOTSUPP;
 649         }
 650
 651         *config = pinconf_to_config_packed(param, arg);
 652         return 0;
 653 }
 654
 655 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 656                                  unsigned long config)
 657 {
 658         unsigned int param = pinconf_to_config_param(config);
 659         unsigned int arg = pinconf_to_config_argument(config);
 660         const struct intel_community *community;
 661         void __iomem *padcfg1;
 662         unsigned long flags;
 663         int ret = 0;
 664         u32 value;
 665
 666         community = intel_get_community(pctrl, pin);
 667         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 668
 669         raw_spin_lock_irqsave(&pctrl->lock, flags);
 670
 671         value = readl(padcfg1);
 672
 673         switch (param) {
 674         case PIN_CONFIG_BIAS_DISABLE:
 675                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 676                 break;
 677
 678         case PIN_CONFIG_BIAS_PULL_UP:
 679                 value &= ~PADCFG1_TERM_MASK;
 680
 681                 value |= PADCFG1_TERM_UP;
 682
 683                 /* Set default strength value in case none is given */
 684                 if (arg == 1)
 685                         arg = 5000;
 686
 687                 switch (arg) {
 688                 case 20000:
 689                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 690                         break;
 691                 case 5000:
 692                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 693                         break;
 694                 case 1000:
 695                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 696                         break;
 697                 case 833:
 698                         value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
 699                         break;
 700                 default:
 701                         ret = -EINVAL;
 702                 }
 703
 704                 break;
 705
 706         case PIN_CONFIG_BIAS_PULL_DOWN:
 707                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 708
 709                 /* Set default strength value in case none is given */
 710                 if (arg == 1)
 711                         arg = 5000;
 712
 713                 switch (arg) {
 714                 case 20000:
 715                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 716                         break;
 717                 case 5000:
 718                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 719                         break;
 720                 case 1000:
 721                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 722                                 ret = -EINVAL;
 723                                 break;
 724                         }
 725                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 726                         break;
 727                 case 833:
 728                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 729                                 ret = -EINVAL;
 730                                 break;
 731                         }
 732                         value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
 733                         break;
 734                 default:
 735                         ret = -EINVAL;
 736                 }
 737
 738                 break;
 739         }
 740
 741         if (!ret)
 742                 writel(value, padcfg1);
 743
 744         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 745
 746         return ret;
 747 }
 748
 749 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 750                                      unsigned int pin, unsigned int debounce)
 751 {
 752         void __iomem *padcfg0, *padcfg2;
 753         unsigned long flags;
 754         u32 value0, value2;
 755
 756         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 757         if (!padcfg2)
 758                 return -ENOTSUPP;
 759
 760         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 761
 762         raw_spin_lock_irqsave(&pctrl->lock, flags);
 763
 764         value0 = readl(padcfg0);
 765         value2 = readl(padcfg2);
 766
 767         /* Disable glitch filter and debouncer */
 768         value0 &= ~PADCFG0_PREGFRXSEL;
 769         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 770
 771         if (debounce) {
 772                 unsigned long v;
 773
 774                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 775                 if (v < 3 || v > 15) {
 776                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 777                         return -EINVAL;
 778                 }
 779
 780                 /* Enable glitch filter and debouncer */
 781                 value0 |= PADCFG0_PREGFRXSEL;
 782                 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 783                 value2 |= PADCFG2_DEBEN;
 784         }
 785
 786         writel(value0, padcfg0);
 787         writel(value2, padcfg2);
 788
 789         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 790
 791         return 0;
 792 }
 793
 794 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 795                           unsigned long *configs, unsigned int nconfigs)
 796 {
 797         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 798         int i, ret;
 799
 800         if (!intel_pad_usable(pctrl, pin))
 801                 return -ENOTSUPP;
 802
 803         for (i = 0; i < nconfigs; i++) {
 804                 switch (pinconf_to_config_param(configs[i])) {
 805                 case PIN_CONFIG_BIAS_DISABLE:
 806                 case PIN_CONFIG_BIAS_PULL_UP:
 807                 case PIN_CONFIG_BIAS_PULL_DOWN:
 808                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 809                         if (ret)
 810                                 return ret;
 811                         break;
 812
 813                 case PIN_CONFIG_INPUT_DEBOUNCE:
 814                         ret = intel_config_set_debounce(pctrl, pin,
 815                                 pinconf_to_config_argument(configs[i]));
 816                         if (ret)
 817                                 return ret;
 818                         break;
 819
 820                 default:
 821                         return -ENOTSUPP;
 822                 }
 823         }
 824
 825         return 0;
 826 }
 827
 828 static const struct pinconf_ops intel_pinconf_ops = {
 829         .is_generic = true,
 830         .pin_config_get = intel_config_get,
 831         .pin_config_set = intel_config_set,
 832 };
 833
 834 static const struct pinctrl_desc intel_pinctrl_desc = {
 835         .pctlops = &intel_pinctrl_ops,
 836         .pmxops = &intel_pinmux_ops,
 837         .confops = &intel_pinconf_ops,
 838         .owner = THIS_MODULE,
 839 };
 840
 841 /**
 842  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 843  * @pctrl: Pinctrl structure
 844  * @offset: GPIO offset from gpiolib
 845  * @community: Community is filled here if not %NULL
 846  * @padgrp: Pad group is filled here if not %NULL
 847  *
 848  * When coming through gpiolib irqchip, the GPIO offset is not
 849  * automatically translated to pinctrl pin number. This function can be
 850  * used to find out the corresponding pinctrl pin.
 851  */
 852 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 853                              const struct intel_community **community,
 854                              const struct intel_padgroup **padgrp)
 855 {
 856         int i;
 857
 858         for (i = 0; i < pctrl->ncommunities; i++) {
 859                 const struct intel_community *comm = &pctrl->communities[i];
 860                 int j;
 861
 862                 for (j = 0; j < comm->ngpps; j++) {
 863                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 864
 865                         if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
 866                                 continue;
 867
 868                         if (offset >= pgrp->gpio_base &&
 869                             offset < pgrp->gpio_base + pgrp->size) {
 870                                 int pin;
 871
 872                                 pin = pgrp->base + offset - pgrp->gpio_base;
 873                                 if (community)
 874                                         *community = comm;
 875                                 if (padgrp)
 876                                         *padgrp = pgrp;
 877
 878                                 return pin;
 879                         }
 880                 }
 881         }
 882
 883         return -EINVAL;
 884 }
 885
 886 /**
 887  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 888  * @pctrl: Pinctrl structure
 889  * @pin: pin number
 890  *
 891  * Translate the pin number of pinctrl to GPIO offset
 892  */
 893 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
 894 {
 895         const struct intel_community *community;
 896         const struct intel_padgroup *padgrp;
 897
 898         community = intel_get_community(pctrl, pin);
 899         if (!community)
 900                 return -EINVAL;
 901
 902         padgrp = intel_community_get_padgroup(community, pin);
 903         if (!padgrp)
 904                 return -EINVAL;
 905
 906         return pin - padgrp->base + padgrp->gpio_base;
 907 }
 908
 909 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 910 {
 911         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 912         void __iomem *reg;
 913         u32 padcfg0;
 914         int pin;
 915
 916         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 917         if (pin < 0)
 918                 return -EINVAL;
 919
 920         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 921         if (!reg)
 922                 return -EINVAL;
 923
 924         padcfg0 = readl(reg);
 925         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 926                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 927
 928         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 929 }
 930
 931 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 932                            int value)
 933 {
 934         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 935         unsigned long flags;
 936         void __iomem *reg;
 937         u32 padcfg0;
 938         int pin;
 939
 940         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 941         if (pin < 0)
 942                 return;
 943
 944         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 945         if (!reg)
 946                 return;
 947
 948         raw_spin_lock_irqsave(&pctrl->lock, flags);
 949         padcfg0 = readl(reg);
 950         if (value)
 951                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 952         else
 953                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 954         writel(padcfg0, reg);
 955         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 956 }
 957
 958 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 959 {
 960         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 961         unsigned long flags;
 962         void __iomem *reg;
 963         u32 padcfg0;
 964         int pin;
 965
 966         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 967         if (pin < 0)
 968                 return -EINVAL;
 969
 970         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 971         if (!reg)
 972                 return -EINVAL;
 973
 974         raw_spin_lock_irqsave(&pctrl->lock, flags);
 975         padcfg0 = readl(reg);
 976         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 977         if (padcfg0 & PADCFG0_PMODE_MASK)
 978                 return -EINVAL;
 979
 980         if (padcfg0 & PADCFG0_GPIOTXDIS)
 981                 return GPIO_LINE_DIRECTION_IN;
 982
 983         return GPIO_LINE_DIRECTION_OUT;
 984 }
 985
 986 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 987 {
 988         return pinctrl_gpio_direction_input(chip->base + offset);
 989 }
 990
 991 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
 992                                        int value)
 993 {
 994         intel_gpio_set(chip, offset, value);
 995         return pinctrl_gpio_direction_output(chip->base + offset);
 996 }
 997
 998 static const struct gpio_chip intel_gpio_chip = {
 999         .owner = THIS_MODULE,
1000         .request = gpiochip_generic_request,
1001         .free = gpiochip_generic_free,
1002         .get_direction = intel_gpio_get_direction,
1003         .direction_input = intel_gpio_direction_input,
1004         .direction_output = intel_gpio_direction_output,
1005         .get = intel_gpio_get,
1006         .set = intel_gpio_set,
1007         .set_config = gpiochip_generic_config,
1008 };
1009
1010 static void intel_gpio_irq_ack(struct irq_data *d)
1011 {
1012         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1013         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1014         const struct intel_community *community;
1015         const struct intel_padgroup *padgrp;
1016         int pin;
1017
1018         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1019         if (pin >= 0) {
1020                 unsigned int gpp, gpp_offset, is_offset;
1021
1022                 gpp = padgrp->reg_num;
1023                 gpp_offset = padgroup_offset(padgrp, pin);
1024                 is_offset = community->is_offset + gpp * 4;
1025
1026                 raw_spin_lock(&pctrl->lock);
1027                 writel(BIT(gpp_offset), community->regs + is_offset);
1028                 raw_spin_unlock(&pctrl->lock);
1029         }
1030 }
1031
1032 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1033 {
1034         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1035         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1036         const struct intel_community *community;
1037         const struct intel_padgroup *padgrp;
1038         int pin;
1039
1040         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1041         if (pin >= 0) {
1042                 unsigned int gpp, gpp_offset;
1043                 unsigned long flags;
1044                 void __iomem *reg, *is;
1045                 u32 value;
1046
1047                 gpp = padgrp->reg_num;
1048                 gpp_offset = padgroup_offset(padgrp, pin);
1049
1050                 reg = community->regs + community->ie_offset + gpp * 4;
1051                 is = community->regs + community->is_offset + gpp * 4;
1052
1053                 raw_spin_lock_irqsave(&pctrl->lock, flags);
1054
1055                 /* Clear interrupt status first to avoid unexpected interrupt */
1056                 writel(BIT(gpp_offset), is);
1057
1058                 value = readl(reg);
1059                 if (mask)
1060                         value &= ~BIT(gpp_offset);
1061                 else
1062                         value |= BIT(gpp_offset);
1063                 writel(value, reg);
1064                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1065         }
1066 }
1067
1068 static void intel_gpio_irq_mask(struct irq_data *d)
1069 {
1070         intel_gpio_irq_mask_unmask(d, true);
1071 }
1072
1073 static void intel_gpio_irq_unmask(struct irq_data *d)
1074 {
1075         intel_gpio_irq_mask_unmask(d, false);
1076 }
1077
1078 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1079 {
1080         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1081         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1082         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1083         unsigned long flags;
1084         void __iomem *reg;
1085         u32 value;
1086
1087         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1088         if (!reg)
1089                 return -EINVAL;
1090
1091         /*
1092          * If the pin is in ACPI mode it is still usable as a GPIO but it
1093          * cannot be used as IRQ because GPI_IS status bit will not be
1094          * updated by the host controller hardware.
1095          */
1096         if (intel_pad_acpi_mode(pctrl, pin)) {
1097                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1098                 return -EPERM;
1099         }
1100
1101         raw_spin_lock_irqsave(&pctrl->lock, flags);
1102
1103         intel_gpio_set_gpio_mode(reg);
1104
1105         value = readl(reg);
1106
1107         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1108
1109         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1110                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1111         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1112                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1113                 value |= PADCFG0_RXINV;
1114         } else if (type & IRQ_TYPE_EDGE_RISING) {
1115                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1116         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1117                 if (type & IRQ_TYPE_LEVEL_LOW)
1118                         value |= PADCFG0_RXINV;
1119         } else {
1120                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1121         }
1122
1123         writel(value, reg);
1124
1125         if (type & IRQ_TYPE_EDGE_BOTH)
1126                 irq_set_handler_locked(d, handle_edge_irq);
1127         else if (type & IRQ_TYPE_LEVEL_MASK)
1128                 irq_set_handler_locked(d, handle_level_irq);
1129
1130         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1131
1132         return 0;
1133 }
1134
1135 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1136 {
1137         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1138         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1139         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1140
1141         if (on)
1142                 enable_irq_wake(pctrl->irq);
1143         else
1144                 disable_irq_wake(pctrl->irq);
1145
1146         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1147         return 0;
1148 }
1149
1150 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1151                                             const struct intel_community *community)
1152 {
1153         struct gpio_chip *gc = &pctrl->chip;
1154         unsigned int gpp;
1155         int ret = 0;
1156
1157         for (gpp = 0; gpp < community->ngpps; gpp++) {
1158                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1159                 unsigned long pending, enabled, gpp_offset;
1160                 unsigned long flags;
1161
1162                 raw_spin_lock_irqsave(&pctrl->lock, flags);
1163
1164                 pending = readl(community->regs + community->is_offset +
1165                                 padgrp->reg_num * 4);
1166                 enabled = readl(community->regs + community->ie_offset +
1167                                 padgrp->reg_num * 4);
1168
1169                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1170
1171                 /* Only interrupts that are enabled */
1172                 pending &= enabled;
1173
1174                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1175                         unsigned int irq;
1176
1177                         irq = irq_find_mapping(gc->irq.domain,
1178                                                padgrp->gpio_base + gpp_offset);
1179                         generic_handle_irq(irq);
1180                 }
1181
1182                 ret += pending ? 1 : 0;
1183         }
1184
1185         return ret;
1186 }
1187
1188 static irqreturn_t intel_gpio_irq(int irq, void *data)
1189 {
1190         const struct intel_community *community;
1191         struct intel_pinctrl *pctrl = data;
1192         unsigned int i;
1193         int ret = 0;
1194
1195         /* Need to check all communities for pending interrupts */
1196         for (i = 0; i < pctrl->ncommunities; i++) {
1197                 community = &pctrl->communities[i];
1198                 ret += intel_gpio_community_irq_handler(pctrl, community);
1199         }
1200
1201         return IRQ_RETVAL(ret);
1202 }
1203
1204 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1205 {
1206         int i;
1207
1208         for (i = 0; i < pctrl->ncommunities; i++) {
1209                 const struct intel_community *community;
1210                 void __iomem *base;
1211                 unsigned int gpp;
1212
1213                 community = &pctrl->communities[i];
1214                 base = community->regs;
1215
1216                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1217                         /* Mask and clear all interrupts */
1218                         writel(0, base + community->ie_offset + gpp * 4);
1219                         writel(0xffff, base + community->is_offset + gpp * 4);
1220                 }
1221         }
1222 }
1223
1224 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1225 {
1226         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1227
1228         /*
1229          * Make sure the interrupt lines are in a proper state before
1230          * further configuration.
1231          */
1232         intel_gpio_irq_init(pctrl);
1233
1234         return 0;
1235 }
1236
1237 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1238                                 const struct intel_community *community)
1239 {
1240         int ret = 0, i;
1241
1242         for (i = 0; i < community->ngpps; i++) {
1243                 const struct intel_padgroup *gpp = &community->gpps[i];
1244
1245                 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1246                         continue;
1247
1248                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1249                                              gpp->gpio_base, gpp->base,
1250                                              gpp->size);
1251                 if (ret)
1252                         return ret;
1253         }
1254
1255         return ret;
1256 }
1257
1258 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1259 {
1260         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1261         int ret, i;
1262
1263         for (i = 0; i < pctrl->ncommunities; i++) {
1264                 struct intel_community *community = &pctrl->communities[i];
1265
1266                 ret = intel_gpio_add_community_ranges(pctrl, community);
1267                 if (ret) {
1268                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1269                         return ret;
1270                 }
1271         }
1272
1273         return 0;
1274 }
1275
1276 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1277 {
1278         const struct intel_community *community;
1279         unsigned int ngpio = 0;
1280         int i, j;
1281
1282         for (i = 0; i < pctrl->ncommunities; i++) {
1283                 community = &pctrl->communities[i];
1284                 for (j = 0; j < community->ngpps; j++) {
1285                         const struct intel_padgroup *gpp = &community->gpps[j];
1286
1287                         if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1288                                 continue;
1289
1290                         if (gpp->gpio_base + gpp->size > ngpio)
1291                                 ngpio = gpp->gpio_base + gpp->size;
1292                 }
1293         }
1294
1295         return ngpio;
1296 }
1297
1298 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1299 {
1300         int ret;
1301         struct gpio_irq_chip *girq;
1302
1303         pctrl->chip = intel_gpio_chip;
1304
1305         /* Setup GPIO chip */
1306         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1307         pctrl->chip.label = dev_name(pctrl->dev);
1308         pctrl->chip.parent = pctrl->dev;
1309         pctrl->chip.base = -1;
1310         pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1311         pctrl->irq = irq;
1312
1313         /* Setup IRQ chip */
1314         pctrl->irqchip.name = dev_name(pctrl->dev);
1315         pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1316         pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1317         pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1318         pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1319         pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1320         pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1321
1322         /*
1323          * On some platforms several GPIO controllers share the same interrupt
1324          * line.
1325          */
1326         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1327                                IRQF_SHARED | IRQF_NO_THREAD,
1328                                dev_name(pctrl->dev), pctrl);
1329         if (ret) {
1330                 dev_err(pctrl->dev, "failed to request interrupt\n");
1331                 return ret;
1332         }
1333
1334         girq = &pctrl->chip.irq;
1335         girq->chip = &pctrl->irqchip;
1336         /* This will let us handle the IRQ in the driver */
1337         girq->parent_handler = NULL;
1338         girq->num_parents = 0;
1339         girq->default_type = IRQ_TYPE_NONE;
1340         girq->handler = handle_bad_irq;
1341         girq->init_hw = intel_gpio_irq_init_hw;
1342
1343         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1344         if (ret) {
1345                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1346                 return ret;
1347         }
1348
1349         return 0;
1350 }
1351
1352 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1353                                        struct intel_community *community)
1354 {
1355         struct intel_padgroup *gpps;
1356         unsigned int npins = community->npins;
1357         unsigned int padown_num = 0;
1358         size_t ngpps, i;
1359
1360         if (community->gpps)
1361                 ngpps = community->ngpps;
1362         else
1363                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1364
1365         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1366         if (!gpps)
1367                 return -ENOMEM;
1368
1369         for (i = 0; i < ngpps; i++) {
1370                 if (community->gpps) {
1371                         gpps[i] = community->gpps[i];
1372                 } else {
1373                         unsigned int gpp_size = community->gpp_size;
1374
1375                         gpps[i].reg_num = i;
1376                         gpps[i].base = community->pin_base + i * gpp_size;
1377                         gpps[i].size = min(gpp_size, npins);
1378                         npins -= gpps[i].size;
1379                 }
1380
1381                 if (gpps[i].size > 32)
1382                         return -EINVAL;
1383
1384                 /* Special treatment for GPIO base */
1385                 switch (gpps[i].gpio_base) {
1386                         case INTEL_GPIO_BASE_MATCH:
1387                                 gpps[i].gpio_base = gpps[i].base;
1388                                 break;
1389                         case INTEL_GPIO_BASE_ZERO:
1390                                 gpps[i].gpio_base = 0;
1391                                 break;
1392                         case INTEL_GPIO_BASE_NOMAP:
1393                         default:
1394                                 break;
1395                 }
1396
1397                 gpps[i].padown_num = padown_num;
1398
1399                 /*
1400                  * In older hardware the number of padown registers per
1401                  * group is fixed regardless of the group size.
1402                  */
1403                 if (community->gpp_num_padown_regs)
1404                         padown_num += community->gpp_num_padown_regs;
1405                 else
1406                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1407         }
1408
1409         community->ngpps = ngpps;
1410         community->gpps = gpps;
1411
1412         return 0;
1413 }
1414
1415 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1416 {
1417 #ifdef CONFIG_PM_SLEEP
1418         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1419         struct intel_community_context *communities;
1420         struct intel_pad_context *pads;
1421         int i;
1422
1423         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1424         if (!pads)
1425                 return -ENOMEM;
1426
1427         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1428                                    sizeof(*communities), GFP_KERNEL);
1429         if (!communities)
1430                 return -ENOMEM;
1431
1432
1433         for (i = 0; i < pctrl->ncommunities; i++) {
1434                 struct intel_community *community = &pctrl->communities[i];
1435                 u32 *intmask, *hostown;
1436
1437                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1438                                        sizeof(*intmask), GFP_KERNEL);
1439                 if (!intmask)
1440                         return -ENOMEM;
1441
1442                 communities[i].intmask = intmask;
1443
1444                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1445                                        sizeof(*hostown), GFP_KERNEL);
1446                 if (!hostown)
1447                         return -ENOMEM;
1448
1449                 communities[i].hostown = hostown;
1450         }
1451
1452         pctrl->context.pads = pads;
1453         pctrl->context.communities = communities;
1454 #endif
1455
1456         return 0;
1457 }
1458
1459 static int intel_pinctrl_probe(struct platform_device *pdev,
1460                                const struct intel_pinctrl_soc_data *soc_data)
1461 {
1462         struct intel_pinctrl *pctrl;
1463         int i, ret, irq;
1464
1465         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1466         if (!pctrl)
1467                 return -ENOMEM;
1468
1469         pctrl->dev = &pdev->dev;
1470         pctrl->soc = soc_data;
1471         raw_spin_lock_init(&pctrl->lock);
1472
1473         /*
1474          * Make a copy of the communities which we can use to hold pointers
1475          * to the registers.
1476          */
1477         pctrl->ncommunities = pctrl->soc->ncommunities;
1478         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1479                                   sizeof(*pctrl->communities), GFP_KERNEL);
1480         if (!pctrl->communities)
1481                 return -ENOMEM;
1482
1483         for (i = 0; i < pctrl->ncommunities; i++) {
1484                 struct intel_community *community = &pctrl->communities[i];
1485                 void __iomem *regs;
1486                 u32 padbar;
1487
1488                 *community = pctrl->soc->communities[i];
1489
1490                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1491                 if (IS_ERR(regs))
1492                         return PTR_ERR(regs);
1493
1494                 /*
1495                  * Determine community features based on the revision if
1496                  * not specified already.
1497                  */
1498                 if (!community->features) {
1499                         u32 rev;
1500
1501                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1502                         if (rev >= 0x94) {
1503                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1504                                 community->features |= PINCTRL_FEATURE_1K_PD;
1505                         }
1506                 }
1507
1508                 /* Read offset of the pad configuration registers */
1509                 padbar = readl(regs + PADBAR);
1510
1511                 community->regs = regs;
1512                 community->pad_regs = regs + padbar;
1513
1514                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1515                 if (ret)
1516                         return ret;
1517         }
1518
1519         irq = platform_get_irq(pdev, 0);
1520         if (irq < 0)
1521                 return irq;
1522
1523         ret = intel_pinctrl_pm_init(pctrl);
1524         if (ret)
1525                 return ret;
1526
1527         pctrl->pctldesc = intel_pinctrl_desc;
1528         pctrl->pctldesc.name = dev_name(&pdev->dev);
1529         pctrl->pctldesc.pins = pctrl->soc->pins;
1530         pctrl->pctldesc.npins = pctrl->soc->npins;
1531
1532         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1533                                                pctrl);
1534         if (IS_ERR(pctrl->pctldev)) {
1535                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1536                 return PTR_ERR(pctrl->pctldev);
1537         }
1538
1539         ret = intel_gpio_probe(pctrl, irq);
1540         if (ret)
1541                 return ret;
1542
1543         platform_set_drvdata(pdev, pctrl);
1544
1545         return 0;
1546 }
1547
1548 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1549 {
1550         const struct intel_pinctrl_soc_data *data;
1551
1552         data = device_get_match_data(&pdev->dev);
1553         if (!data)
1554                 return -ENODATA;
1555
1556         return intel_pinctrl_probe(pdev, data);
1557 }
1558 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1559
1560 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1561 {
1562         const struct intel_pinctrl_soc_data *data;
1563
1564         data = intel_pinctrl_get_soc_data(pdev);
1565         if (IS_ERR(data))
1566                 return PTR_ERR(data);
1567
1568         return intel_pinctrl_probe(pdev, data);
1569 }
1570 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1571
1572 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1573 {
1574         const struct intel_pinctrl_soc_data * const *table;
1575         const struct intel_pinctrl_soc_data *data = NULL;
1576
1577         table = device_get_match_data(&pdev->dev);
1578         if (table) {
1579                 struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
1580                 unsigned int i;
1581
1582                 for (i = 0; table[i]; i++) {
1583                         if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1584                                 data = table[i];
1585                                 break;
1586                         }
1587                 }
1588         } else {
1589                 const struct platform_device_id *id;
1590
1591                 id = platform_get_device_id(pdev);
1592                 if (!id)
1593                         return ERR_PTR(-ENODEV);
1594
1595                 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1596                 data = table[pdev->id];
1597         }
1598
1599         return data ?: ERR_PTR(-ENODATA);
1600 }
1601 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
1602
1603 #ifdef CONFIG_PM_SLEEP
1604 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1605 {
1606         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1607
1608         if (!pd || !intel_pad_usable(pctrl, pin))
1609                 return false;
1610
1611         /*
1612          * Only restore the pin if it is actually in use by the kernel (or
1613          * by userspace). It is possible that some pins are used by the
1614          * BIOS during resume and those are not always locked down so leave
1615          * them alone.
1616          */
1617         if (pd->mux_owner || pd->gpio_owner ||
1618             gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1619                 return true;
1620
1621         return false;
1622 }
1623
1624 int intel_pinctrl_suspend_noirq(struct device *dev)
1625 {
1626         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1627         struct intel_community_context *communities;
1628         struct intel_pad_context *pads;
1629         int i;
1630
1631         pads = pctrl->context.pads;
1632         for (i = 0; i < pctrl->soc->npins; i++) {
1633                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1634                 void __iomem *padcfg;
1635                 u32 val;
1636
1637                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1638                         continue;
1639
1640                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1641                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1642                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1643                 pads[i].padcfg1 = val;
1644
1645                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1646                 if (padcfg)
1647                         pads[i].padcfg2 = readl(padcfg);
1648         }
1649
1650         communities = pctrl->context.communities;
1651         for (i = 0; i < pctrl->ncommunities; i++) {
1652                 struct intel_community *community = &pctrl->communities[i];
1653                 void __iomem *base;
1654                 unsigned int gpp;
1655
1656                 base = community->regs + community->ie_offset;
1657                 for (gpp = 0; gpp < community->ngpps; gpp++)
1658                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1659
1660                 base = community->regs + community->hostown_offset;
1661                 for (gpp = 0; gpp < community->ngpps; gpp++)
1662                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1663         }
1664
1665         return 0;
1666 }
1667 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1668
1669 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1670 {
1671         u32 curr, updated;
1672
1673         curr = readl(reg);
1674
1675         updated = (curr & ~mask) | (value & mask);
1676         if (curr == updated)
1677                 return false;
1678
1679         writel(updated, reg);
1680         return true;
1681 }
1682
1683 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1684                                   void __iomem *base, unsigned int gpp, u32 saved)
1685 {
1686         const struct intel_community *community = &pctrl->communities[c];
1687         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1688         struct device *dev = pctrl->dev;
1689         const char *dummy;
1690         u32 requested = 0;
1691         unsigned int i;
1692
1693         if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1694                 return;
1695
1696         for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1697                 requested |= BIT(i);
1698
1699         if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1700                 return;
1701
1702         dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1703 }
1704
1705 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1706                                   void __iomem *base, unsigned int gpp, u32 saved)
1707 {
1708         struct device *dev = pctrl->dev;
1709
1710         if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1711                 return;
1712
1713         dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1714 }
1715
1716 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1717                                  unsigned int reg, u32 saved)
1718 {
1719         u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1720         unsigned int n = reg / sizeof(u32);
1721         struct device *dev = pctrl->dev;
1722         void __iomem *padcfg;
1723
1724         padcfg = intel_get_padcfg(pctrl, pin, reg);
1725         if (!padcfg)
1726                 return;
1727
1728         if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1729                 return;
1730
1731         dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1732 }
1733
1734 int intel_pinctrl_resume_noirq(struct device *dev)
1735 {
1736         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1737         const struct intel_community_context *communities;
1738         const struct intel_pad_context *pads;
1739         int i;
1740
1741         /* Mask all interrupts */
1742         intel_gpio_irq_init(pctrl);
1743
1744         pads = pctrl->context.pads;
1745         for (i = 0; i < pctrl->soc->npins; i++) {
1746                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1747
1748                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1749                         continue;
1750
1751                 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1752                 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1753                 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1754         }
1755
1756         communities = pctrl->context.communities;
1757         for (i = 0; i < pctrl->ncommunities; i++) {
1758                 struct intel_community *community = &pctrl->communities[i];
1759                 void __iomem *base;
1760                 unsigned int gpp;
1761
1762                 base = community->regs + community->ie_offset;
1763                 for (gpp = 0; gpp < community->ngpps; gpp++)
1764                         intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1765
1766                 base = community->regs + community->hostown_offset;
1767                 for (gpp = 0; gpp < community->ngpps; gpp++)
1768                         intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1769         }
1770
1771         return 0;
1772 }
1773 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1774 #endif
1775
1776 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1777 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1778 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1779 MODULE_LICENSE("GPL v2");