drivers/pinctrl/intel/pinctrl-intel.c

   1 /*
   2  * Intel pinctrl/GPIO core driver.
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinmux.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinconf-generic.h>
  21
  22 #include "../core.h"
  23 #include "pinctrl-intel.h"
  24
  25 /* Offset from regs */
  26 #define PADBAR                          0x00c
  27 #define GPI_IS                          0x100
  28 #define GPI_GPE_STS                     0x140
  29 #define GPI_GPE_EN                      0x160
  30
  31 #define PADOWN_BITS                     4
  32 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  33 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  34 #define PADOWN_GPP(p)                   ((p) / 8)
  35
  36 /* Offset from pad_regs */
  37 #define PADCFG0                         0x000
  38 #define PADCFG0_RXEVCFG_SHIFT           25
  39 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  40 #define PADCFG0_RXEVCFG_LEVEL           0
  41 #define PADCFG0_RXEVCFG_EDGE            1
  42 #define PADCFG0_RXEVCFG_DISABLED        2
  43 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  44 #define PADCFG0_RXINV                   BIT(23)
  45 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  46 #define PADCFG0_GPIROUTSCI              BIT(19)
  47 #define PADCFG0_GPIROUTSMI              BIT(18)
  48 #define PADCFG0_GPIROUTNMI              BIT(17)
  49 #define PADCFG0_PMODE_SHIFT             10
  50 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  51 #define PADCFG0_GPIORXDIS               BIT(9)
  52 #define PADCFG0_GPIOTXDIS               BIT(8)
  53 #define PADCFG0_GPIORXSTATE             BIT(1)
  54 #define PADCFG0_GPIOTXSTATE             BIT(0)
  55
  56 #define PADCFG1                         0x004
  57 #define PADCFG1_TERM_UP                 BIT(13)
  58 #define PADCFG1_TERM_SHIFT              10
  59 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  60 #define PADCFG1_TERM_20K                4
  61 #define PADCFG1_TERM_2K                 3
  62 #define PADCFG1_TERM_5K                 2
  63 #define PADCFG1_TERM_1K                 1
  64
  65 struct intel_pad_context {
  66         u32 padcfg0;
  67         u32 padcfg1;
  68 };
  69
  70 struct intel_community_context {
  71         u32 *intmask;
  72 };
  73
  74 struct intel_pinctrl_context {
  75         struct intel_pad_context *pads;
  76         struct intel_community_context *communities;
  77 };
  78
  79 /**
  80  * struct intel_pinctrl - Intel pinctrl private structure
  81  * @dev: Pointer to the device structure
  82  * @lock: Lock to serialize register access
  83  * @pctldesc: Pin controller description
  84  * @pctldev: Pointer to the pin controller device
  85  * @chip: GPIO chip in this pin controller
  86  * @soc: SoC/PCH specific pin configuration data
  87  * @communities: All communities in this pin controller
  88  * @ncommunities: Number of communities in this pin controller
  89  * @context: Configuration saved over system sleep
  90  * @irq: pinctrl/GPIO chip irq number
  91  */
  92 struct intel_pinctrl {
  93         struct device *dev;
  94         raw_spinlock_t lock;
  95         struct pinctrl_desc pctldesc;
  96         struct pinctrl_dev *pctldev;
  97         struct gpio_chip chip;
  98         const struct intel_pinctrl_soc_data *soc;
  99         struct intel_community *communities;
 100         size_t ncommunities;
 101         struct intel_pinctrl_context context;
 102         int irq;
 103 };
 104
 105 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 106
 107 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 108                                                    unsigned pin)
 109 {
 110         struct intel_community *community;
 111         int i;
 112
 113         for (i = 0; i < pctrl->ncommunities; i++) {
 114                 community = &pctrl->communities[i];
 115                 if (pin >= community->pin_base &&
 116                     pin < community->pin_base + community->npins)
 117                         return community;
 118         }
 119
 120         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 121         return NULL;
 122 }
 123
 124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 125                                       unsigned reg)
 126 {
 127         const struct intel_community *community;
 128         unsigned padno;
 129
 130         community = intel_get_community(pctrl, pin);
 131         if (!community)
 132                 return NULL;
 133
 134         padno = pin_to_padno(community, pin);
 135         return community->pad_regs + reg + padno * 8;
 136 }
 137
 138 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 139 {
 140         const struct intel_community *community;
 141         unsigned padno, gpp, offset, group;
 142         void __iomem *padown;
 143
 144         community = intel_get_community(pctrl, pin);
 145         if (!community)
 146                 return false;
 147         if (!community->padown_offset)
 148                 return true;
 149
 150         padno = pin_to_padno(community, pin);
 151         group = padno / community->gpp_size;
 152         gpp = PADOWN_GPP(padno % community->gpp_size);
 153         offset = community->padown_offset + 0x10 * group + gpp * 4;
 154         padown = community->regs + offset;
 155
 156         return !(readl(padown) & PADOWN_MASK(padno));
 157 }
 158
 159 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 160 {
 161         const struct intel_community *community;
 162         unsigned padno, gpp, offset;
 163         void __iomem *hostown;
 164
 165         community = intel_get_community(pctrl, pin);
 166         if (!community)
 167                 return true;
 168         if (!community->hostown_offset)
 169                 return false;
 170
 171         padno = pin_to_padno(community, pin);
 172         gpp = padno / community->gpp_size;
 173         offset = community->hostown_offset + gpp * 4;
 174         hostown = community->regs + offset;
 175
 176         return !(readl(hostown) & BIT(padno % community->gpp_size));
 177 }
 178
 179 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 180 {
 181         struct intel_community *community;
 182         unsigned padno, gpp, offset;
 183         u32 value;
 184
 185         community = intel_get_community(pctrl, pin);
 186         if (!community)
 187                 return true;
 188         if (!community->padcfglock_offset)
 189                 return false;
 190
 191         padno = pin_to_padno(community, pin);
 192         gpp = padno / community->gpp_size;
 193
 194         /*
 195          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 196          * the pad is considered unlocked. Any other case means that it is
 197          * either fully or partially locked and we don't touch it.
 198          */
 199         offset = community->padcfglock_offset + gpp * 8;
 200         value = readl(community->regs + offset);
 201         if (value & BIT(pin % community->gpp_size))
 202                 return true;
 203
 204         offset = community->padcfglock_offset + 4 + gpp * 8;
 205         value = readl(community->regs + offset);
 206         if (value & BIT(pin % community->gpp_size))
 207                 return true;
 208
 209         return false;
 210 }
 211
 212 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 213 {
 214         return intel_pad_owned_by_host(pctrl, pin) &&
 215                 !intel_pad_locked(pctrl, pin);
 216 }
 217
 218 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 219 {
 220         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 221
 222         return pctrl->soc->ngroups;
 223 }
 224
 225 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 226                                       unsigned group)
 227 {
 228         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 229
 230         return pctrl->soc->groups[group].name;
 231 }
 232
 233 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 234                               const unsigned **pins, unsigned *npins)
 235 {
 236         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 237
 238         *pins = pctrl->soc->groups[group].pins;
 239         *npins = pctrl->soc->groups[group].npins;
 240         return 0;
 241 }
 242
 243 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 244                                unsigned pin)
 245 {
 246         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 247         u32 cfg0, cfg1, mode;
 248         bool locked, acpi;
 249
 250         if (!intel_pad_owned_by_host(pctrl, pin)) {
 251                 seq_puts(s, "not available");
 252                 return;
 253         }
 254
 255         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 256         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 257
 258         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 259         if (!mode)
 260                 seq_puts(s, "GPIO ");
 261         else
 262                 seq_printf(s, "mode %d ", mode);
 263
 264         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 265
 266         locked = intel_pad_locked(pctrl, pin);
 267         acpi = intel_pad_acpi_mode(pctrl, pin);
 268
 269         if (locked || acpi) {
 270                 seq_puts(s, " [");
 271                 if (locked) {
 272                         seq_puts(s, "LOCKED");
 273                         if (acpi)
 274                                 seq_puts(s, ", ");
 275                 }
 276                 if (acpi)
 277                         seq_puts(s, "ACPI");
 278                 seq_puts(s, "]");
 279         }
 280 }
 281
 282 static const struct pinctrl_ops intel_pinctrl_ops = {
 283         .get_groups_count = intel_get_groups_count,
 284         .get_group_name = intel_get_group_name,
 285         .get_group_pins = intel_get_group_pins,
 286         .pin_dbg_show = intel_pin_dbg_show,
 287 };
 288
 289 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 290 {
 291         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 292
 293         return pctrl->soc->nfunctions;
 294 }
 295
 296 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 297                                            unsigned function)
 298 {
 299         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 300
 301         return pctrl->soc->functions[function].name;
 302 }
 303
 304 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 305                                      unsigned function,
 306                                      const char * const **groups,
 307                                      unsigned * const ngroups)
 308 {
 309         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 310
 311         *groups = pctrl->soc->functions[function].groups;
 312         *ngroups = pctrl->soc->functions[function].ngroups;
 313         return 0;
 314 }
 315
 316 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 317                                 unsigned group)
 318 {
 319         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 320         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 321         unsigned long flags;
 322         int i;
 323
 324         raw_spin_lock_irqsave(&pctrl->lock, flags);
 325
 326         /*
 327          * All pins in the groups needs to be accessible and writable
 328          * before we can enable the mux for this group.
 329          */
 330         for (i = 0; i < grp->npins; i++) {
 331                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 332                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 333                         return -EBUSY;
 334                 }
 335         }
 336
 337         /* Now enable the mux setting for each pin in the group */
 338         for (i = 0; i < grp->npins; i++) {
 339                 void __iomem *padcfg0;
 340                 u32 value;
 341
 342                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 343                 value = readl(padcfg0);
 344
 345                 value &= ~PADCFG0_PMODE_MASK;
 346                 value |= grp->mode << PADCFG0_PMODE_SHIFT;
 347
 348                 writel(value, padcfg0);
 349         }
 350
 351         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 352
 353         return 0;
 354 }
 355
 356 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 357 {
 358         u32 value;
 359
 360         value = readl(padcfg0);
 361         if (input) {
 362                 value &= ~PADCFG0_GPIORXDIS;
 363                 value |= PADCFG0_GPIOTXDIS;
 364         } else {
 365                 value &= ~PADCFG0_GPIOTXDIS;
 366                 value |= PADCFG0_GPIORXDIS;
 367         }
 368         writel(value, padcfg0);
 369 }
 370
 371 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 372                                      struct pinctrl_gpio_range *range,
 373                                      unsigned pin)
 374 {
 375         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 376         void __iomem *padcfg0;
 377         unsigned long flags;
 378         u32 value;
 379
 380         raw_spin_lock_irqsave(&pctrl->lock, flags);
 381
 382         if (!intel_pad_usable(pctrl, pin)) {
 383                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 384                 return -EBUSY;
 385         }
 386
 387         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 388         /* Put the pad into GPIO mode */
 389         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 390         /* Disable SCI/SMI/NMI generation */
 391         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 392         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 393         writel(value, padcfg0);
 394
 395         /* Disable TX buffer and enable RX (this will be input) */
 396         __intel_gpio_set_direction(padcfg0, true);
 397
 398         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 399
 400         return 0;
 401 }
 402
 403 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 404                                     struct pinctrl_gpio_range *range,
 405                                     unsigned pin, bool input)
 406 {
 407         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 408         void __iomem *padcfg0;
 409         unsigned long flags;
 410
 411         raw_spin_lock_irqsave(&pctrl->lock, flags);
 412
 413         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 414         __intel_gpio_set_direction(padcfg0, input);
 415
 416         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 417
 418         return 0;
 419 }
 420
 421 static const struct pinmux_ops intel_pinmux_ops = {
 422         .get_functions_count = intel_get_functions_count,
 423         .get_function_name = intel_get_function_name,
 424         .get_function_groups = intel_get_function_groups,
 425         .set_mux = intel_pinmux_set_mux,
 426         .gpio_request_enable = intel_gpio_request_enable,
 427         .gpio_set_direction = intel_gpio_set_direction,
 428 };
 429
 430 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 431                             unsigned long *config)
 432 {
 433         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 434         enum pin_config_param param = pinconf_to_config_param(*config);
 435         u32 value, term;
 436         u16 arg = 0;
 437
 438         if (!intel_pad_owned_by_host(pctrl, pin))
 439                 return -ENOTSUPP;
 440
 441         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 442         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 443
 444         switch (param) {
 445         case PIN_CONFIG_BIAS_DISABLE:
 446                 if (term)
 447                         return -EINVAL;
 448                 break;
 449
 450         case PIN_CONFIG_BIAS_PULL_UP:
 451                 if (!term || !(value & PADCFG1_TERM_UP))
 452                         return -EINVAL;
 453
 454                 switch (term) {
 455                 case PADCFG1_TERM_1K:
 456                         arg = 1000;
 457                         break;
 458                 case PADCFG1_TERM_2K:
 459                         arg = 2000;
 460                         break;
 461                 case PADCFG1_TERM_5K:
 462                         arg = 5000;
 463                         break;
 464                 case PADCFG1_TERM_20K:
 465                         arg = 20000;
 466                         break;
 467                 }
 468
 469                 break;
 470
 471         case PIN_CONFIG_BIAS_PULL_DOWN:
 472                 if (!term || value & PADCFG1_TERM_UP)
 473                         return -EINVAL;
 474
 475                 switch (term) {
 476                 case PADCFG1_TERM_5K:
 477                         arg = 5000;
 478                         break;
 479                 case PADCFG1_TERM_20K:
 480                         arg = 20000;
 481                         break;
 482                 }
 483
 484                 break;
 485
 486         default:
 487                 return -ENOTSUPP;
 488         }
 489
 490         *config = pinconf_to_config_packed(param, arg);
 491         return 0;
 492 }
 493
 494 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 495                                  unsigned long config)
 496 {
 497         unsigned param = pinconf_to_config_param(config);
 498         unsigned arg = pinconf_to_config_argument(config);
 499         void __iomem *padcfg1;
 500         unsigned long flags;
 501         int ret = 0;
 502         u32 value;
 503
 504         raw_spin_lock_irqsave(&pctrl->lock, flags);
 505
 506         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 507         value = readl(padcfg1);
 508
 509         switch (param) {
 510         case PIN_CONFIG_BIAS_DISABLE:
 511                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 512                 break;
 513
 514         case PIN_CONFIG_BIAS_PULL_UP:
 515                 value &= ~PADCFG1_TERM_MASK;
 516
 517                 value |= PADCFG1_TERM_UP;
 518
 519                 switch (arg) {
 520                 case 20000:
 521                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 522                         break;
 523                 case 5000:
 524                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 525                         break;
 526                 case 2000:
 527                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 528                         break;
 529                 case 1000:
 530                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 531                         break;
 532                 default:
 533                         ret = -EINVAL;
 534                 }
 535
 536                 break;
 537
 538         case PIN_CONFIG_BIAS_PULL_DOWN:
 539                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 540
 541                 switch (arg) {
 542                 case 20000:
 543                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 544                         break;
 545                 case 5000:
 546                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 547                         break;
 548                 default:
 549                         ret = -EINVAL;
 550                 }
 551
 552                 break;
 553         }
 554
 555         if (!ret)
 556                 writel(value, padcfg1);
 557
 558         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 559
 560         return ret;
 561 }
 562
 563 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 564                           unsigned long *configs, unsigned nconfigs)
 565 {
 566         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 567         int i, ret;
 568
 569         if (!intel_pad_usable(pctrl, pin))
 570                 return -ENOTSUPP;
 571
 572         for (i = 0; i < nconfigs; i++) {
 573                 switch (pinconf_to_config_param(configs[i])) {
 574                 case PIN_CONFIG_BIAS_DISABLE:
 575                 case PIN_CONFIG_BIAS_PULL_UP:
 576                 case PIN_CONFIG_BIAS_PULL_DOWN:
 577                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 578                         if (ret)
 579                                 return ret;
 580                         break;
 581
 582                 default:
 583                         return -ENOTSUPP;
 584                 }
 585         }
 586
 587         return 0;
 588 }
 589
 590 static const struct pinconf_ops intel_pinconf_ops = {
 591         .is_generic = true,
 592         .pin_config_get = intel_config_get,
 593         .pin_config_set = intel_config_set,
 594 };
 595
 596 static const struct pinctrl_desc intel_pinctrl_desc = {
 597         .pctlops = &intel_pinctrl_ops,
 598         .pmxops = &intel_pinmux_ops,
 599         .confops = &intel_pinconf_ops,
 600         .owner = THIS_MODULE,
 601 };
 602
 603 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 604 {
 605         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 606         void __iomem *reg;
 607         u32 padcfg0;
 608
 609         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 610         if (!reg)
 611                 return -EINVAL;
 612
 613         padcfg0 = readl(reg);
 614         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 615                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 616
 617         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 618 }
 619
 620 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 621 {
 622         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 623         void __iomem *reg;
 624
 625         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 626         if (reg) {
 627                 unsigned long flags;
 628                 u32 padcfg0;
 629
 630                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 631                 padcfg0 = readl(reg);
 632                 if (value)
 633                         padcfg0 |= PADCFG0_GPIOTXSTATE;
 634                 else
 635                         padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 636                 writel(padcfg0, reg);
 637                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 638         }
 639 }
 640
 641 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 642 {
 643         return pinctrl_gpio_direction_input(chip->base + offset);
 644 }
 645
 646 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 647                                        int value)
 648 {
 649         intel_gpio_set(chip, offset, value);
 650         return pinctrl_gpio_direction_output(chip->base + offset);
 651 }
 652
 653 static const struct gpio_chip intel_gpio_chip = {
 654         .owner = THIS_MODULE,
 655         .request = gpiochip_generic_request,
 656         .free = gpiochip_generic_free,
 657         .direction_input = intel_gpio_direction_input,
 658         .direction_output = intel_gpio_direction_output,
 659         .get = intel_gpio_get,
 660         .set = intel_gpio_set,
 661 };
 662
 663 static void intel_gpio_irq_ack(struct irq_data *d)
 664 {
 665         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 666         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 667         const struct intel_community *community;
 668         unsigned pin = irqd_to_hwirq(d);
 669
 670         raw_spin_lock(&pctrl->lock);
 671
 672         community = intel_get_community(pctrl, pin);
 673         if (community) {
 674                 unsigned padno = pin_to_padno(community, pin);
 675                 unsigned gpp_offset = padno % community->gpp_size;
 676                 unsigned gpp = padno / community->gpp_size;
 677
 678                 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 679         }
 680
 681         raw_spin_unlock(&pctrl->lock);
 682 }
 683
 684 static void intel_gpio_irq_enable(struct irq_data *d)
 685 {
 686         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 687         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 688         const struct intel_community *community;
 689         unsigned pin = irqd_to_hwirq(d);
 690         unsigned long flags;
 691
 692         raw_spin_lock_irqsave(&pctrl->lock, flags);
 693
 694         community = intel_get_community(pctrl, pin);
 695         if (community) {
 696                 unsigned padno = pin_to_padno(community, pin);
 697                 unsigned gpp_size = community->gpp_size;
 698                 unsigned gpp_offset = padno % gpp_size;
 699                 unsigned gpp = padno / gpp_size;
 700                 u32 value;
 701
 702                 /* Clear interrupt status first to avoid unexpected interrupt */
 703                 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 704
 705                 value = readl(community->regs + community->ie_offset + gpp * 4);
 706                 value |= BIT(gpp_offset);
 707                 writel(value, community->regs + community->ie_offset + gpp * 4);
 708         }
 709
 710         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 711 }
 712
 713 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 714 {
 715         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 716         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 717         const struct intel_community *community;
 718         unsigned pin = irqd_to_hwirq(d);
 719         unsigned long flags;
 720
 721         raw_spin_lock_irqsave(&pctrl->lock, flags);
 722
 723         community = intel_get_community(pctrl, pin);
 724         if (community) {
 725                 unsigned padno = pin_to_padno(community, pin);
 726                 unsigned gpp_offset = padno % community->gpp_size;
 727                 unsigned gpp = padno / community->gpp_size;
 728                 void __iomem *reg;
 729                 u32 value;
 730
 731                 reg = community->regs + community->ie_offset + gpp * 4;
 732                 value = readl(reg);
 733                 if (mask)
 734                         value &= ~BIT(gpp_offset);
 735                 else
 736                         value |= BIT(gpp_offset);
 737                 writel(value, reg);
 738         }
 739
 740         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 741 }
 742
 743 static void intel_gpio_irq_mask(struct irq_data *d)
 744 {
 745         intel_gpio_irq_mask_unmask(d, true);
 746 }
 747
 748 static void intel_gpio_irq_unmask(struct irq_data *d)
 749 {
 750         intel_gpio_irq_mask_unmask(d, false);
 751 }
 752
 753 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
 754 {
 755         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 756         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 757         unsigned pin = irqd_to_hwirq(d);
 758         unsigned long flags;
 759         void __iomem *reg;
 760         u32 value;
 761
 762         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 763         if (!reg)
 764                 return -EINVAL;
 765
 766         /*
 767          * If the pin is in ACPI mode it is still usable as a GPIO but it
 768          * cannot be used as IRQ because GPI_IS status bit will not be
 769          * updated by the host controller hardware.
 770          */
 771         if (intel_pad_acpi_mode(pctrl, pin)) {
 772                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
 773                 return -EPERM;
 774         }
 775
 776         raw_spin_lock_irqsave(&pctrl->lock, flags);
 777
 778         value = readl(reg);
 779
 780         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
 781
 782         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 783                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
 784         } else if (type & IRQ_TYPE_EDGE_FALLING) {
 785                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 786                 value |= PADCFG0_RXINV;
 787         } else if (type & IRQ_TYPE_EDGE_RISING) {
 788                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 789         } else if (type & IRQ_TYPE_LEVEL_MASK) {
 790                 if (type & IRQ_TYPE_LEVEL_LOW)
 791                         value |= PADCFG0_RXINV;
 792         } else {
 793                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
 794         }
 795
 796         writel(value, reg);
 797
 798         if (type & IRQ_TYPE_EDGE_BOTH)
 799                 irq_set_handler_locked(d, handle_edge_irq);
 800         else if (type & IRQ_TYPE_LEVEL_MASK)
 801                 irq_set_handler_locked(d, handle_level_irq);
 802
 803         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 804
 805         return 0;
 806 }
 807
 808 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
 809 {
 810         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 811         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 812         unsigned pin = irqd_to_hwirq(d);
 813
 814         if (on)
 815                 enable_irq_wake(pctrl->irq);
 816         else
 817                 disable_irq_wake(pctrl->irq);
 818
 819         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
 820         return 0;
 821 }
 822
 823 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
 824         const struct intel_community *community)
 825 {
 826         struct gpio_chip *gc = &pctrl->chip;
 827         irqreturn_t ret = IRQ_NONE;
 828         int gpp;
 829
 830         for (gpp = 0; gpp < community->ngpps; gpp++) {
 831                 unsigned long pending, enabled, gpp_offset;
 832
 833                 pending = readl(community->regs + GPI_IS + gpp * 4);
 834                 enabled = readl(community->regs + community->ie_offset +
 835                                 gpp * 4);
 836
 837                 /* Only interrupts that are enabled */
 838                 pending &= enabled;
 839
 840                 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
 841                         unsigned padno, irq;
 842
 843                         /*
 844                          * The last group in community can have less pins
 845                          * than NPADS_IN_GPP.
 846                          */
 847                         padno = gpp_offset + gpp * community->gpp_size;
 848                         if (padno >= community->npins)
 849                                 break;
 850
 851                         irq = irq_find_mapping(gc->irqdomain,
 852                                                community->pin_base + padno);
 853                         generic_handle_irq(irq);
 854
 855                         ret |= IRQ_HANDLED;
 856                 }
 857         }
 858
 859         return ret;
 860 }
 861
 862 static irqreturn_t intel_gpio_irq(int irq, void *data)
 863 {
 864         const struct intel_community *community;
 865         struct intel_pinctrl *pctrl = data;
 866         irqreturn_t ret = IRQ_NONE;
 867         int i;
 868
 869         /* Need to check all communities for pending interrupts */
 870         for (i = 0; i < pctrl->ncommunities; i++) {
 871                 community = &pctrl->communities[i];
 872                 ret |= intel_gpio_community_irq_handler(pctrl, community);
 873         }
 874
 875         return ret;
 876 }
 877
 878 static struct irq_chip intel_gpio_irqchip = {
 879         .name = "intel-gpio",
 880         .irq_enable = intel_gpio_irq_enable,
 881         .irq_ack = intel_gpio_irq_ack,
 882         .irq_mask = intel_gpio_irq_mask,
 883         .irq_unmask = intel_gpio_irq_unmask,
 884         .irq_set_type = intel_gpio_irq_type,
 885         .irq_set_wake = intel_gpio_irq_wake,
 886 };
 887
 888 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
 889 {
 890         int ret;
 891
 892         pctrl->chip = intel_gpio_chip;
 893
 894         pctrl->chip.ngpio = pctrl->soc->npins;
 895         pctrl->chip.label = dev_name(pctrl->dev);
 896         pctrl->chip.parent = pctrl->dev;
 897         pctrl->chip.base = -1;
 898         pctrl->irq = irq;
 899
 900         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 901         if (ret) {
 902                 dev_err(pctrl->dev, "failed to register gpiochip\n");
 903                 return ret;
 904         }
 905
 906         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
 907                                      0, 0, pctrl->soc->npins);
 908         if (ret) {
 909                 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
 910                 goto fail;
 911         }
 912
 913         /*
 914          * We need to request the interrupt here (instead of providing chip
 915          * to the irq directly) because on some platforms several GPIO
 916          * controllers share the same interrupt line.
 917          */
 918         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
 919                                IRQF_SHARED | IRQF_NO_THREAD,
 920                                dev_name(pctrl->dev), pctrl);
 921         if (ret) {
 922                 dev_err(pctrl->dev, "failed to request interrupt\n");
 923                 goto fail;
 924         }
 925
 926         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
 927                                    handle_simple_irq, IRQ_TYPE_NONE);
 928         if (ret) {
 929                 dev_err(pctrl->dev, "failed to add irqchip\n");
 930                 goto fail;
 931         }
 932
 933         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
 934                                      NULL);
 935         return 0;
 936
 937 fail:
 938         gpiochip_remove(&pctrl->chip);
 939
 940         return ret;
 941 }
 942
 943 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
 944 {
 945 #ifdef CONFIG_PM_SLEEP
 946         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
 947         struct intel_community_context *communities;
 948         struct intel_pad_context *pads;
 949         int i;
 950
 951         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
 952         if (!pads)
 953                 return -ENOMEM;
 954
 955         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
 956                                    sizeof(*communities), GFP_KERNEL);
 957         if (!communities)
 958                 return -ENOMEM;
 959
 960
 961         for (i = 0; i < pctrl->ncommunities; i++) {
 962                 struct intel_community *community = &pctrl->communities[i];
 963                 u32 *intmask;
 964
 965                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
 966                                        sizeof(*intmask), GFP_KERNEL);
 967                 if (!intmask)
 968                         return -ENOMEM;
 969
 970                 communities[i].intmask = intmask;
 971         }
 972
 973         pctrl->context.pads = pads;
 974         pctrl->context.communities = communities;
 975 #endif
 976
 977         return 0;
 978 }
 979
 980 int intel_pinctrl_probe(struct platform_device *pdev,
 981                         const struct intel_pinctrl_soc_data *soc_data)
 982 {
 983         struct intel_pinctrl *pctrl;
 984         int i, ret, irq;
 985
 986         if (!soc_data)
 987                 return -EINVAL;
 988
 989         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 990         if (!pctrl)
 991                 return -ENOMEM;
 992
 993         pctrl->dev = &pdev->dev;
 994         pctrl->soc = soc_data;
 995         raw_spin_lock_init(&pctrl->lock);
 996
 997         /*
 998          * Make a copy of the communities which we can use to hold pointers
 999          * to the registers.
1000          */
1001         pctrl->ncommunities = pctrl->soc->ncommunities;
1002         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1003                                   sizeof(*pctrl->communities), GFP_KERNEL);
1004         if (!pctrl->communities)
1005                 return -ENOMEM;
1006
1007         for (i = 0; i < pctrl->ncommunities; i++) {
1008                 struct intel_community *community = &pctrl->communities[i];
1009                 struct resource *res;
1010                 void __iomem *regs;
1011                 u32 padbar;
1012
1013                 *community = pctrl->soc->communities[i];
1014
1015                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1016                                             community->barno);
1017                 regs = devm_ioremap_resource(&pdev->dev, res);
1018                 if (IS_ERR(regs))
1019                         return PTR_ERR(regs);
1020
1021                 /* Read offset of the pad configuration registers */
1022                 padbar = readl(regs + PADBAR);
1023
1024                 community->regs = regs;
1025                 community->pad_regs = regs + padbar;
1026                 community->ngpps = DIV_ROUND_UP(community->npins,
1027                                                 community->gpp_size);
1028         }
1029
1030         irq = platform_get_irq(pdev, 0);
1031         if (irq < 0) {
1032                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1033                 return irq;
1034         }
1035
1036         ret = intel_pinctrl_pm_init(pctrl);
1037         if (ret)
1038                 return ret;
1039
1040         pctrl->pctldesc = intel_pinctrl_desc;
1041         pctrl->pctldesc.name = dev_name(&pdev->dev);
1042         pctrl->pctldesc.pins = pctrl->soc->pins;
1043         pctrl->pctldesc.npins = pctrl->soc->npins;
1044
1045         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1046                                                pctrl);
1047         if (IS_ERR(pctrl->pctldev)) {
1048                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1049                 return PTR_ERR(pctrl->pctldev);
1050         }
1051
1052         ret = intel_gpio_probe(pctrl, irq);
1053         if (ret)
1054                 return ret;
1055
1056         platform_set_drvdata(pdev, pctrl);
1057
1058         return 0;
1059 }
1060 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1061
1062 int intel_pinctrl_remove(struct platform_device *pdev)
1063 {
1064         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1065
1066         gpiochip_remove(&pctrl->chip);
1067
1068         return 0;
1069 }
1070 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1071
1072 #ifdef CONFIG_PM_SLEEP
1073 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1074 {
1075         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1076
1077         if (!pd || !intel_pad_usable(pctrl, pin))
1078                 return false;
1079
1080         /*
1081          * Only restore the pin if it is actually in use by the kernel (or
1082          * by userspace). It is possible that some pins are used by the
1083          * BIOS during resume and those are not always locked down so leave
1084          * them alone.
1085          */
1086         if (pd->mux_owner || pd->gpio_owner ||
1087             gpiochip_line_is_irq(&pctrl->chip, pin))
1088                 return true;
1089
1090         return false;
1091 }
1092
1093 int intel_pinctrl_suspend(struct device *dev)
1094 {
1095         struct platform_device *pdev = to_platform_device(dev);
1096         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1097         struct intel_community_context *communities;
1098         struct intel_pad_context *pads;
1099         int i;
1100
1101         pads = pctrl->context.pads;
1102         for (i = 0; i < pctrl->soc->npins; i++) {
1103                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1104                 u32 val;
1105
1106                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1107                         continue;
1108
1109                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1110                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1111                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1112                 pads[i].padcfg1 = val;
1113         }
1114
1115         communities = pctrl->context.communities;
1116         for (i = 0; i < pctrl->ncommunities; i++) {
1117                 struct intel_community *community = &pctrl->communities[i];
1118                 void __iomem *base;
1119                 unsigned gpp;
1120
1121                 base = community->regs + community->ie_offset;
1122                 for (gpp = 0; gpp < community->ngpps; gpp++)
1123                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1124         }
1125
1126         return 0;
1127 }
1128 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1129
1130 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1131 {
1132         size_t i;
1133
1134         for (i = 0; i < pctrl->ncommunities; i++) {
1135                 const struct intel_community *community;
1136                 void __iomem *base;
1137                 unsigned gpp;
1138
1139                 community = &pctrl->communities[i];
1140                 base = community->regs;
1141
1142                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1143                         /* Mask and clear all interrupts */
1144                         writel(0, base + community->ie_offset + gpp * 4);
1145                         writel(0xffff, base + GPI_IS + gpp * 4);
1146                 }
1147         }
1148 }
1149
1150 int intel_pinctrl_resume(struct device *dev)
1151 {
1152         struct platform_device *pdev = to_platform_device(dev);
1153         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1154         const struct intel_community_context *communities;
1155         const struct intel_pad_context *pads;
1156         int i;
1157
1158         /* Mask all interrupts */
1159         intel_gpio_irq_init(pctrl);
1160
1161         pads = pctrl->context.pads;
1162         for (i = 0; i < pctrl->soc->npins; i++) {
1163                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1164                 void __iomem *padcfg;
1165                 u32 val;
1166
1167                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1168                         continue;
1169
1170                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1171                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1172                 if (val != pads[i].padcfg0) {
1173                         writel(pads[i].padcfg0, padcfg);
1174                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1175                                 desc->number, readl(padcfg));
1176                 }
1177
1178                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1179                 val = readl(padcfg);
1180                 if (val != pads[i].padcfg1) {
1181                         writel(pads[i].padcfg1, padcfg);
1182                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1183                                 desc->number, readl(padcfg));
1184                 }
1185         }
1186
1187         communities = pctrl->context.communities;
1188         for (i = 0; i < pctrl->ncommunities; i++) {
1189                 struct intel_community *community = &pctrl->communities[i];
1190                 void __iomem *base;
1191                 unsigned gpp;
1192
1193                 base = community->regs + community->ie_offset;
1194                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1195                         writel(communities[i].intmask[gpp], base + gpp * 4);
1196                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1197                                 readl(base + gpp * 4));
1198                 }
1199         }
1200
1201         return 0;
1202 }
1203 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1204 #endif
1205
1206 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1207 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1208 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1209 MODULE_LICENSE("GPL v2");