1 // SPDX-License-Identifier: GPL-2.0
3 * Cherryview/Braswell pinctrl driver
5 * Copyright (C) 2014, 2020 Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This driver is based on the original Cherryview GPIO driver by
9 * Ning Li <ning.li@intel.com>
10 * Alan Cox <alan@linux.intel.com>
13 #include <linux/acpi.h>
14 #include <linux/dmi.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/types.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-intel.h"
28 #define CHV_INTSTAT 0x300
29 #define CHV_INTMASK 0x380
31 #define FAMILY_PAD_REGS_OFF 0x4400
32 #define FAMILY_PAD_REGS_SIZE 0x400
33 #define MAX_FAMILY_PAD_GPIO_NO 15
34 #define GPIO_REGS_SIZE 8
36 #define CHV_PADCTRL0 0x000
37 #define CHV_PADCTRL0_INTSEL_SHIFT 28
38 #define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28)
39 #define CHV_PADCTRL0_TERM_UP BIT(23)
40 #define CHV_PADCTRL0_TERM_SHIFT 20
41 #define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20)
42 #define CHV_PADCTRL0_TERM_20K 1
43 #define CHV_PADCTRL0_TERM_5K 2
44 #define CHV_PADCTRL0_TERM_1K 4
45 #define CHV_PADCTRL0_PMODE_SHIFT 16
46 #define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16)
47 #define CHV_PADCTRL0_GPIOEN BIT(15)
48 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
49 #define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8)
50 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
51 #define CHV_PADCTRL0_GPIOCFG_GPO 1
52 #define CHV_PADCTRL0_GPIOCFG_GPI 2
53 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
54 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
55 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
57 #define CHV_PADCTRL1 0x004
58 #define CHV_PADCTRL1_CFGLOCK BIT(31)
59 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
60 #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4)
61 #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7)
62 #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6)
63 #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5)
64 #define CHV_PADCTRL1_ODEN BIT(3)
65 #define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0)
66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
67 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
68 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
71 struct intel_pad_context {
77 * struct intel_community_context - community context for Cherryview
78 * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
79 * @saved_intmask: Interrupt mask saved for system sleep
81 struct intel_community_context {
82 unsigned int intr_lines[16];
86 #define PINMODE_INVERT_OE BIT(15)
88 #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE))
90 #define CHV_GPP(start, end) \
93 .size = (end) - (start) + 1, \
96 #define CHV_COMMUNITY(g, i, a) \
99 .ngpps = ARRAY_SIZE(g), \
101 .acpi_space_id = (a), \
104 static const struct pinctrl_pin_desc southwest_pins[] = {
105 PINCTRL_PIN(0, "FST_SPI_D2"),
106 PINCTRL_PIN(1, "FST_SPI_D0"),
107 PINCTRL_PIN(2, "FST_SPI_CLK"),
108 PINCTRL_PIN(3, "FST_SPI_D3"),
109 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
110 PINCTRL_PIN(5, "FST_SPI_D1"),
111 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
112 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
114 PINCTRL_PIN(15, "UART1_RTS_B"),
115 PINCTRL_PIN(16, "UART1_RXD"),
116 PINCTRL_PIN(17, "UART2_RXD"),
117 PINCTRL_PIN(18, "UART1_CTS_B"),
118 PINCTRL_PIN(19, "UART2_RTS_B"),
119 PINCTRL_PIN(20, "UART1_TXD"),
120 PINCTRL_PIN(21, "UART2_TXD"),
121 PINCTRL_PIN(22, "UART2_CTS_B"),
123 PINCTRL_PIN(30, "MF_HDA_CLK"),
124 PINCTRL_PIN(31, "MF_HDA_RSTB"),
125 PINCTRL_PIN(32, "MF_HDA_SDIO"),
126 PINCTRL_PIN(33, "MF_HDA_SDO"),
127 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
128 PINCTRL_PIN(35, "MF_HDA_SYNC"),
129 PINCTRL_PIN(36, "MF_HDA_SDI1"),
130 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
132 PINCTRL_PIN(45, "I2C5_SDA"),
133 PINCTRL_PIN(46, "I2C4_SDA"),
134 PINCTRL_PIN(47, "I2C6_SDA"),
135 PINCTRL_PIN(48, "I2C5_SCL"),
136 PINCTRL_PIN(49, "I2C_NFC_SDA"),
137 PINCTRL_PIN(50, "I2C4_SCL"),
138 PINCTRL_PIN(51, "I2C6_SCL"),
139 PINCTRL_PIN(52, "I2C_NFC_SCL"),
141 PINCTRL_PIN(60, "I2C1_SDA"),
142 PINCTRL_PIN(61, "I2C0_SDA"),
143 PINCTRL_PIN(62, "I2C2_SDA"),
144 PINCTRL_PIN(63, "I2C1_SCL"),
145 PINCTRL_PIN(64, "I2C3_SDA"),
146 PINCTRL_PIN(65, "I2C0_SCL"),
147 PINCTRL_PIN(66, "I2C2_SCL"),
148 PINCTRL_PIN(67, "I2C3_SCL"),
150 PINCTRL_PIN(75, "SATA_GP0"),
151 PINCTRL_PIN(76, "SATA_GP1"),
152 PINCTRL_PIN(77, "SATA_LEDN"),
153 PINCTRL_PIN(78, "SATA_GP2"),
154 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
155 PINCTRL_PIN(80, "SATA_GP3"),
156 PINCTRL_PIN(81, "MF_SMB_CLK"),
157 PINCTRL_PIN(82, "MF_SMB_DATA"),
159 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
160 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
161 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
162 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
163 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
164 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
165 PINCTRL_PIN(96, "GP_SSP_2_FS"),
166 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
169 static const unsigned southwest_uart0_pins[] = { 16, 20 };
170 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
171 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
172 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
173 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
174 static const unsigned southwest_lpe_pins[] = {
175 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
177 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
178 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
179 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
180 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
181 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
182 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
183 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
184 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
186 /* Some of LPE I2S TXD pins need to have OE inversion set */
187 static const unsigned int southwest_lpe_altfuncs[] = {
188 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
189 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
190 PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
194 * Two spi3 chipselects are available in different mode than the main spi3
195 * functionality, which is using mode 2.
197 static const unsigned int southwest_spi3_altfuncs[] = {
198 PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
199 PINMODE(2, 0), /* 82 */
202 static const struct intel_pingroup southwest_groups[] = {
203 PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
204 PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
205 PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
206 PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
207 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
208 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
209 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
210 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
211 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
212 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
213 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
214 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
215 PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
216 PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
219 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
220 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
221 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
222 static const char * const southwest_hda_groups[] = { "hda_grp" };
223 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
224 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
225 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
226 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
227 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
228 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
229 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
230 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
231 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
232 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
235 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
236 * enabled only as GPIOs.
238 static const struct intel_function southwest_functions[] = {
239 FUNCTION("uart0", southwest_uart0_groups),
240 FUNCTION("uart1", southwest_uart1_groups),
241 FUNCTION("uart2", southwest_uart2_groups),
242 FUNCTION("hda", southwest_hda_groups),
243 FUNCTION("lpe", southwest_lpe_groups),
244 FUNCTION("i2c0", southwest_i2c0_groups),
245 FUNCTION("i2c1", southwest_i2c1_groups),
246 FUNCTION("i2c2", southwest_i2c2_groups),
247 FUNCTION("i2c3", southwest_i2c3_groups),
248 FUNCTION("i2c4", southwest_i2c4_groups),
249 FUNCTION("i2c5", southwest_i2c5_groups),
250 FUNCTION("i2c6", southwest_i2c6_groups),
251 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
252 FUNCTION("spi3", southwest_spi3_groups),
255 static const struct intel_padgroup southwest_gpps[] = {
266 * Southwest community can generate GPIO interrupts only for the first 8
267 * interrupts. The upper half (8-15) can only be used to trigger GPEs.
269 static const struct intel_community southwest_communities[] = {
270 CHV_COMMUNITY(southwest_gpps, 8, 0x91),
273 static const struct intel_pinctrl_soc_data southwest_soc_data = {
275 .pins = southwest_pins,
276 .npins = ARRAY_SIZE(southwest_pins),
277 .groups = southwest_groups,
278 .ngroups = ARRAY_SIZE(southwest_groups),
279 .functions = southwest_functions,
280 .nfunctions = ARRAY_SIZE(southwest_functions),
281 .communities = southwest_communities,
282 .ncommunities = ARRAY_SIZE(southwest_communities),
285 static const struct pinctrl_pin_desc north_pins[] = {
286 PINCTRL_PIN(0, "GPIO_DFX_0"),
287 PINCTRL_PIN(1, "GPIO_DFX_3"),
288 PINCTRL_PIN(2, "GPIO_DFX_7"),
289 PINCTRL_PIN(3, "GPIO_DFX_1"),
290 PINCTRL_PIN(4, "GPIO_DFX_5"),
291 PINCTRL_PIN(5, "GPIO_DFX_4"),
292 PINCTRL_PIN(6, "GPIO_DFX_8"),
293 PINCTRL_PIN(7, "GPIO_DFX_2"),
294 PINCTRL_PIN(8, "GPIO_DFX_6"),
296 PINCTRL_PIN(15, "GPIO_SUS0"),
297 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
298 PINCTRL_PIN(17, "GPIO_SUS3"),
299 PINCTRL_PIN(18, "GPIO_SUS7"),
300 PINCTRL_PIN(19, "GPIO_SUS1"),
301 PINCTRL_PIN(20, "GPIO_SUS5"),
302 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
303 PINCTRL_PIN(22, "GPIO_SUS4"),
304 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
305 PINCTRL_PIN(24, "GPIO_SUS2"),
306 PINCTRL_PIN(25, "GPIO_SUS6"),
307 PINCTRL_PIN(26, "CX_PREQ_B"),
308 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
310 PINCTRL_PIN(30, "TRST_B"),
311 PINCTRL_PIN(31, "TCK"),
312 PINCTRL_PIN(32, "PROCHOT_B"),
313 PINCTRL_PIN(33, "SVIDO_DATA"),
314 PINCTRL_PIN(34, "TMS"),
315 PINCTRL_PIN(35, "CX_PRDY_B_2"),
316 PINCTRL_PIN(36, "TDO_2"),
317 PINCTRL_PIN(37, "CX_PRDY_B"),
318 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
319 PINCTRL_PIN(39, "TDO"),
320 PINCTRL_PIN(40, "SVIDO_CLK"),
321 PINCTRL_PIN(41, "TDI"),
323 PINCTRL_PIN(45, "GP_CAMERASB_05"),
324 PINCTRL_PIN(46, "GP_CAMERASB_02"),
325 PINCTRL_PIN(47, "GP_CAMERASB_08"),
326 PINCTRL_PIN(48, "GP_CAMERASB_00"),
327 PINCTRL_PIN(49, "GP_CAMERASB_06"),
328 PINCTRL_PIN(50, "GP_CAMERASB_10"),
329 PINCTRL_PIN(51, "GP_CAMERASB_03"),
330 PINCTRL_PIN(52, "GP_CAMERASB_09"),
331 PINCTRL_PIN(53, "GP_CAMERASB_01"),
332 PINCTRL_PIN(54, "GP_CAMERASB_07"),
333 PINCTRL_PIN(55, "GP_CAMERASB_11"),
334 PINCTRL_PIN(56, "GP_CAMERASB_04"),
336 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
337 PINCTRL_PIN(61, "HV_DDI0_HPD"),
338 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
339 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
340 PINCTRL_PIN(64, "HV_DDI1_HPD"),
341 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
342 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
343 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
344 PINCTRL_PIN(68, "HV_DDI2_HPD"),
345 PINCTRL_PIN(69, "PANEL1_VDDEN"),
346 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
347 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
348 PINCTRL_PIN(72, "PANEL0_VDDEN"),
351 static const struct intel_padgroup north_gpps[] = {
360 * North community can generate GPIO interrupts only for the first 8
361 * interrupts. The upper half (8-15) can only be used to trigger GPEs.
363 static const struct intel_community north_communities[] = {
364 CHV_COMMUNITY(north_gpps, 8, 0x92),
367 static const struct intel_pinctrl_soc_data north_soc_data = {
370 .npins = ARRAY_SIZE(north_pins),
371 .communities = north_communities,
372 .ncommunities = ARRAY_SIZE(north_communities),
375 static const struct pinctrl_pin_desc east_pins[] = {
376 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
377 PINCTRL_PIN(1, "PMU_BATLOW_B"),
378 PINCTRL_PIN(2, "SUS_STAT_B"),
379 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
380 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
381 PINCTRL_PIN(5, "PMU_PLTRST_B"),
382 PINCTRL_PIN(6, "PMU_SUSCLK"),
383 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
384 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
385 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
386 PINCTRL_PIN(10, "PMU_WAKE_B"),
387 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
389 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
390 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
391 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
392 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
393 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
394 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
395 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
396 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
397 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
398 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
399 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
400 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
403 static const struct intel_padgroup east_gpps[] = {
408 static const struct intel_community east_communities[] = {
409 CHV_COMMUNITY(east_gpps, 16, 0x93),
412 static const struct intel_pinctrl_soc_data east_soc_data = {
415 .npins = ARRAY_SIZE(east_pins),
416 .communities = east_communities,
417 .ncommunities = ARRAY_SIZE(east_communities),
420 static const struct pinctrl_pin_desc southeast_pins[] = {
421 PINCTRL_PIN(0, "MF_PLT_CLK0"),
422 PINCTRL_PIN(1, "PWM1"),
423 PINCTRL_PIN(2, "MF_PLT_CLK1"),
424 PINCTRL_PIN(3, "MF_PLT_CLK4"),
425 PINCTRL_PIN(4, "MF_PLT_CLK3"),
426 PINCTRL_PIN(5, "PWM0"),
427 PINCTRL_PIN(6, "MF_PLT_CLK5"),
428 PINCTRL_PIN(7, "MF_PLT_CLK2"),
430 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
431 PINCTRL_PIN(16, "SDMMC1_CLK"),
432 PINCTRL_PIN(17, "SDMMC1_D0"),
433 PINCTRL_PIN(18, "SDMMC2_D1"),
434 PINCTRL_PIN(19, "SDMMC2_CLK"),
435 PINCTRL_PIN(20, "SDMMC1_D2"),
436 PINCTRL_PIN(21, "SDMMC2_D2"),
437 PINCTRL_PIN(22, "SDMMC2_CMD"),
438 PINCTRL_PIN(23, "SDMMC1_CMD"),
439 PINCTRL_PIN(24, "SDMMC1_D1"),
440 PINCTRL_PIN(25, "SDMMC2_D0"),
441 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
443 PINCTRL_PIN(30, "SDMMC3_D1"),
444 PINCTRL_PIN(31, "SDMMC3_CLK"),
445 PINCTRL_PIN(32, "SDMMC3_D3"),
446 PINCTRL_PIN(33, "SDMMC3_D2"),
447 PINCTRL_PIN(34, "SDMMC3_CMD"),
448 PINCTRL_PIN(35, "SDMMC3_D0"),
450 PINCTRL_PIN(45, "MF_LPC_AD2"),
451 PINCTRL_PIN(46, "LPC_CLKRUNB"),
452 PINCTRL_PIN(47, "MF_LPC_AD0"),
453 PINCTRL_PIN(48, "LPC_FRAMEB"),
454 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
455 PINCTRL_PIN(50, "MF_LPC_AD3"),
456 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
457 PINCTRL_PIN(52, "MF_LPC_AD1"),
459 PINCTRL_PIN(60, "SPI1_MISO"),
460 PINCTRL_PIN(61, "SPI1_CSO_B"),
461 PINCTRL_PIN(62, "SPI1_CLK"),
462 PINCTRL_PIN(63, "MMC1_D6"),
463 PINCTRL_PIN(64, "SPI1_MOSI"),
464 PINCTRL_PIN(65, "MMC1_D5"),
465 PINCTRL_PIN(66, "SPI1_CS1_B"),
466 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
467 PINCTRL_PIN(68, "MMC1_D7"),
468 PINCTRL_PIN(69, "MMC1_RCLK"),
470 PINCTRL_PIN(75, "USB_OC1_B"),
471 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
472 PINCTRL_PIN(77, "GPIO_ALERT"),
473 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
474 PINCTRL_PIN(79, "ILB_SERIRQ"),
475 PINCTRL_PIN(80, "USB_OC0_B"),
476 PINCTRL_PIN(81, "SDMMC3_CD_B"),
477 PINCTRL_PIN(82, "SPKR"),
478 PINCTRL_PIN(83, "SUSPWRDNACK"),
479 PINCTRL_PIN(84, "SPARE_PIN"),
480 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
483 static const unsigned southeast_pwm0_pins[] = { 5 };
484 static const unsigned southeast_pwm1_pins[] = { 1 };
485 static const unsigned southeast_sdmmc1_pins[] = {
486 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
488 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
489 static const unsigned southeast_sdmmc3_pins[] = {
490 30, 31, 32, 33, 34, 35, 78, 81, 85,
492 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
493 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
495 static const struct intel_pingroup southeast_groups[] = {
496 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
497 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
498 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
499 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
500 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
501 PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
502 PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
505 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
506 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
507 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
508 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
509 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
510 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
511 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
513 static const struct intel_function southeast_functions[] = {
514 FUNCTION("pwm0", southeast_pwm0_groups),
515 FUNCTION("pwm1", southeast_pwm1_groups),
516 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
517 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
518 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
519 FUNCTION("spi1", southeast_spi1_groups),
520 FUNCTION("spi2", southeast_spi2_groups),
523 static const struct intel_padgroup southeast_gpps[] = {
532 static const struct intel_community southeast_communities[] = {
533 CHV_COMMUNITY(southeast_gpps, 16, 0x94),
536 static const struct intel_pinctrl_soc_data southeast_soc_data = {
538 .pins = southeast_pins,
539 .npins = ARRAY_SIZE(southeast_pins),
540 .groups = southeast_groups,
541 .ngroups = ARRAY_SIZE(southeast_groups),
542 .functions = southeast_functions,
543 .nfunctions = ARRAY_SIZE(southeast_functions),
544 .communities = southeast_communities,
545 .ncommunities = ARRAY_SIZE(southeast_communities),
548 static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
557 * Lock to serialize register accesses
559 * Due to a silicon issue, a shared lock must be used to prevent
560 * concurrent accesses across the 4 GPIO controllers.
562 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
563 * errata #CHT34, for further information.
565 static DEFINE_RAW_SPINLOCK(chv_lock);
567 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
569 const struct intel_community *community = &pctrl->communities[0];
571 return readl(community->regs + offset);
574 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
576 const struct intel_community *community = &pctrl->communities[0];
577 void __iomem *reg = community->regs + offset;
579 /* Write and simple read back to confirm the bus transferring done */
584 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
587 const struct intel_community *community = &pctrl->communities[0];
588 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
589 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
591 offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
593 return community->pad_regs + offset + reg;
596 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
598 return readl(chv_padreg(pctrl, pin, offset));
601 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
603 void __iomem *reg = chv_padreg(pctrl, pin, offset);
605 /* Write and simple read back to confirm the bus transferring done */
610 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
611 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
613 return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
616 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
618 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
620 return pctrl->soc->ngroups;
623 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
626 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
628 return pctrl->soc->groups[group].name;
631 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
632 const unsigned int **pins, unsigned int *npins)
634 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
636 *pins = pctrl->soc->groups[group].pins;
637 *npins = pctrl->soc->groups[group].npins;
641 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
644 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
649 raw_spin_lock_irqsave(&chv_lock, flags);
651 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
652 ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
653 locked = chv_pad_locked(pctrl, offset);
655 raw_spin_unlock_irqrestore(&chv_lock, flags);
657 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
658 seq_puts(s, "GPIO ");
662 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
663 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
665 seq_printf(s, "mode %d ", mode);
668 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
671 seq_puts(s, " [LOCKED]");
674 static const struct pinctrl_ops chv_pinctrl_ops = {
675 .get_groups_count = chv_get_groups_count,
676 .get_group_name = chv_get_group_name,
677 .get_group_pins = chv_get_group_pins,
678 .pin_dbg_show = chv_pin_dbg_show,
681 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
683 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
685 return pctrl->soc->nfunctions;
688 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
689 unsigned int function)
691 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
693 return pctrl->soc->functions[function].name;
696 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
697 unsigned int function,
698 const char * const **groups,
699 unsigned int * const ngroups)
701 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
703 *groups = pctrl->soc->functions[function].groups;
704 *ngroups = pctrl->soc->functions[function].ngroups;
708 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
709 unsigned int function, unsigned int group)
711 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
712 const struct intel_pingroup *grp;
716 grp = &pctrl->soc->groups[group];
718 raw_spin_lock_irqsave(&chv_lock, flags);
720 /* Check first that the pad is not locked */
721 for (i = 0; i < grp->npins; i++) {
722 if (chv_pad_locked(pctrl, grp->pins[i])) {
723 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
725 raw_spin_unlock_irqrestore(&chv_lock, flags);
730 for (i = 0; i < grp->npins; i++) {
731 int pin = grp->pins[i];
736 /* Check if there is pin-specific config */
738 mode = grp->modes[i];
742 /* Extract OE inversion */
743 invert_oe = mode & PINMODE_INVERT_OE;
744 mode &= ~PINMODE_INVERT_OE;
746 value = chv_readl(pctrl, pin, CHV_PADCTRL0);
747 /* Disable GPIO mode */
748 value &= ~CHV_PADCTRL0_GPIOEN;
749 /* Set to desired mode */
750 value &= ~CHV_PADCTRL0_PMODE_MASK;
751 value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
752 chv_writel(pctrl, pin, CHV_PADCTRL0, value);
754 /* Update for invert_oe */
755 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
757 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
758 chv_writel(pctrl, pin, CHV_PADCTRL1, value);
760 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
761 pin, mode, invert_oe ? "" : "not ");
764 raw_spin_unlock_irqrestore(&chv_lock, flags);
769 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
772 u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
776 * One some devices the GPIO should output the inverted value from what
777 * device-drivers / ACPI code expects (inverted external buffer?). The
778 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
779 * preserve this flag if the pin is already setup as GPIO.
781 value = chv_readl(pctrl, offset, CHV_PADCTRL0);
782 if (value & CHV_PADCTRL0_GPIOEN)
783 invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
785 value = chv_readl(pctrl, offset, CHV_PADCTRL1);
786 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
787 value &= ~invrxtx_mask;
788 chv_writel(pctrl, offset, CHV_PADCTRL1, value);
791 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
792 struct pinctrl_gpio_range *range,
795 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
799 raw_spin_lock_irqsave(&chv_lock, flags);
801 if (chv_pad_locked(pctrl, offset)) {
802 value = chv_readl(pctrl, offset, CHV_PADCTRL0);
803 if (!(value & CHV_PADCTRL0_GPIOEN)) {
804 /* Locked so cannot enable */
805 raw_spin_unlock_irqrestore(&chv_lock, flags);
809 struct intel_community_context *cctx = &pctrl->context.communities[0];
812 /* Reset the interrupt mapping */
813 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
814 if (cctx->intr_lines[i] == offset) {
815 cctx->intr_lines[i] = 0;
820 /* Disable interrupt generation */
821 chv_gpio_clear_triggering(pctrl, offset);
823 value = chv_readl(pctrl, offset, CHV_PADCTRL0);
826 * If the pin is in HiZ mode (both TX and RX buffers are
827 * disabled) we turn it to be input now.
829 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
830 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
831 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
832 value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
835 /* Switch to a GPIO mode */
836 value |= CHV_PADCTRL0_GPIOEN;
837 chv_writel(pctrl, offset, CHV_PADCTRL0, value);
840 raw_spin_unlock_irqrestore(&chv_lock, flags);
845 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
846 struct pinctrl_gpio_range *range,
849 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
852 raw_spin_lock_irqsave(&chv_lock, flags);
854 if (!chv_pad_locked(pctrl, offset))
855 chv_gpio_clear_triggering(pctrl, offset);
857 raw_spin_unlock_irqrestore(&chv_lock, flags);
860 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
861 struct pinctrl_gpio_range *range,
862 unsigned int offset, bool input)
864 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
868 raw_spin_lock_irqsave(&chv_lock, flags);
870 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
872 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
874 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
875 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
877 raw_spin_unlock_irqrestore(&chv_lock, flags);
882 static const struct pinmux_ops chv_pinmux_ops = {
883 .get_functions_count = chv_get_functions_count,
884 .get_function_name = chv_get_function_name,
885 .get_function_groups = chv_get_function_groups,
886 .set_mux = chv_pinmux_set_mux,
887 .gpio_request_enable = chv_gpio_request_enable,
888 .gpio_disable_free = chv_gpio_disable_free,
889 .gpio_set_direction = chv_gpio_set_direction,
892 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
893 unsigned long *config)
895 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
896 enum pin_config_param param = pinconf_to_config_param(*config);
902 raw_spin_lock_irqsave(&chv_lock, flags);
903 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
904 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
905 raw_spin_unlock_irqrestore(&chv_lock, flags);
907 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
910 case PIN_CONFIG_BIAS_DISABLE:
915 case PIN_CONFIG_BIAS_PULL_UP:
916 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
920 case CHV_PADCTRL0_TERM_20K:
923 case CHV_PADCTRL0_TERM_5K:
926 case CHV_PADCTRL0_TERM_1K:
933 case PIN_CONFIG_BIAS_PULL_DOWN:
934 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
938 case CHV_PADCTRL0_TERM_20K:
941 case CHV_PADCTRL0_TERM_5K:
948 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
951 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
952 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
953 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
958 case PIN_CONFIG_DRIVE_PUSH_PULL:
959 if (ctrl1 & CHV_PADCTRL1_ODEN)
963 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
964 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
973 *config = pinconf_to_config_packed(param, arg);
977 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
978 enum pin_config_param param, u32 arg)
983 raw_spin_lock_irqsave(&chv_lock, flags);
984 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
987 case PIN_CONFIG_BIAS_DISABLE:
988 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
991 case PIN_CONFIG_BIAS_PULL_UP:
992 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
996 /* For 1k there is only pull up */
997 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1000 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1003 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1006 raw_spin_unlock_irqrestore(&chv_lock, flags);
1010 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1013 case PIN_CONFIG_BIAS_PULL_DOWN:
1014 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1018 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1021 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1024 raw_spin_unlock_irqrestore(&chv_lock, flags);
1032 raw_spin_unlock_irqrestore(&chv_lock, flags);
1036 chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
1037 raw_spin_unlock_irqrestore(&chv_lock, flags);
1042 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
1045 unsigned long flags;
1048 raw_spin_lock_irqsave(&chv_lock, flags);
1049 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
1052 ctrl1 |= CHV_PADCTRL1_ODEN;
1054 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1056 chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
1057 raw_spin_unlock_irqrestore(&chv_lock, flags);
1062 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1063 unsigned long *configs, unsigned int nconfigs)
1065 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1066 enum pin_config_param param;
1070 if (chv_pad_locked(pctrl, pin))
1073 for (i = 0; i < nconfigs; i++) {
1074 param = pinconf_to_config_param(configs[i]);
1075 arg = pinconf_to_config_argument(configs[i]);
1078 case PIN_CONFIG_BIAS_DISABLE:
1079 case PIN_CONFIG_BIAS_PULL_UP:
1080 case PIN_CONFIG_BIAS_PULL_DOWN:
1081 ret = chv_config_set_pull(pctrl, pin, param, arg);
1086 case PIN_CONFIG_DRIVE_PUSH_PULL:
1087 ret = chv_config_set_oden(pctrl, pin, false);
1092 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1093 ret = chv_config_set_oden(pctrl, pin, true);
1102 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1109 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1111 unsigned long *config)
1113 const unsigned int *pins;
1117 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1121 ret = chv_config_get(pctldev, pins[0], config);
1128 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1129 unsigned int group, unsigned long *configs,
1130 unsigned int num_configs)
1132 const unsigned int *pins;
1136 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1140 for (i = 0; i < npins; i++) {
1141 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1149 static const struct pinconf_ops chv_pinconf_ops = {
1151 .pin_config_set = chv_config_set,
1152 .pin_config_get = chv_config_get,
1153 .pin_config_group_get = chv_config_group_get,
1154 .pin_config_group_set = chv_config_group_set,
1157 static struct pinctrl_desc chv_pinctrl_desc = {
1158 .pctlops = &chv_pinctrl_ops,
1159 .pmxops = &chv_pinmux_ops,
1160 .confops = &chv_pinconf_ops,
1161 .owner = THIS_MODULE,
1164 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1166 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1167 unsigned long flags;
1170 raw_spin_lock_irqsave(&chv_lock, flags);
1171 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1172 raw_spin_unlock_irqrestore(&chv_lock, flags);
1174 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1175 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1177 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1178 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1179 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1182 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1184 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1185 unsigned long flags;
1188 raw_spin_lock_irqsave(&chv_lock, flags);
1190 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1193 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1195 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1197 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
1199 raw_spin_unlock_irqrestore(&chv_lock, flags);
1202 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1204 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1205 u32 ctrl0, direction;
1206 unsigned long flags;
1208 raw_spin_lock_irqsave(&chv_lock, flags);
1209 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1210 raw_spin_unlock_irqrestore(&chv_lock, flags);
1212 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1213 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1215 if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1216 return GPIO_LINE_DIRECTION_OUT;
1218 return GPIO_LINE_DIRECTION_IN;
1221 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1223 return pinctrl_gpio_direction_input(chip->base + offset);
1226 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1229 chv_gpio_set(chip, offset, value);
1230 return pinctrl_gpio_direction_output(chip->base + offset);
1233 static const struct gpio_chip chv_gpio_chip = {
1234 .owner = THIS_MODULE,
1235 .request = gpiochip_generic_request,
1236 .free = gpiochip_generic_free,
1237 .get_direction = chv_gpio_get_direction,
1238 .direction_input = chv_gpio_direction_input,
1239 .direction_output = chv_gpio_direction_output,
1240 .get = chv_gpio_get,
1241 .set = chv_gpio_set,
1244 static void chv_gpio_irq_ack(struct irq_data *d)
1246 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1247 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1248 int pin = irqd_to_hwirq(d);
1251 raw_spin_lock(&chv_lock);
1253 intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
1254 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1255 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1256 chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
1258 raw_spin_unlock(&chv_lock);
1261 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1263 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1264 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1265 int pin = irqd_to_hwirq(d);
1266 u32 value, intr_line;
1267 unsigned long flags;
1269 raw_spin_lock_irqsave(&chv_lock, flags);
1271 intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
1272 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1273 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1275 value = chv_pctrl_readl(pctrl, CHV_INTMASK);
1277 value &= ~BIT(intr_line);
1279 value |= BIT(intr_line);
1280 chv_pctrl_writel(pctrl, CHV_INTMASK, value);
1282 raw_spin_unlock_irqrestore(&chv_lock, flags);
1285 static void chv_gpio_irq_mask(struct irq_data *d)
1287 chv_gpio_irq_mask_unmask(d, true);
1290 static void chv_gpio_irq_unmask(struct irq_data *d)
1292 chv_gpio_irq_mask_unmask(d, false);
1295 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1298 * Check if the interrupt has been requested with 0 as triggering
1299 * type. In that case it is assumed that the current values
1300 * programmed to the hardware are used (e.g BIOS configured
1303 * In that case ->irq_set_type() will never be called so we need to
1304 * read back the values from hardware now, set correct flow handler
1305 * and update mappings before the interrupt is being used.
1307 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1308 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1309 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1310 struct intel_community_context *cctx = &pctrl->context.communities[0];
1311 unsigned int pin = irqd_to_hwirq(d);
1312 irq_flow_handler_t handler;
1313 unsigned long flags;
1316 raw_spin_lock_irqsave(&chv_lock, flags);
1317 intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
1318 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1319 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1321 value = chv_readl(pctrl, pin, CHV_PADCTRL1);
1322 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1323 handler = handle_level_irq;
1325 handler = handle_edge_irq;
1327 if (!cctx->intr_lines[intsel]) {
1328 irq_set_handler_locked(d, handler);
1329 cctx->intr_lines[intsel] = pin;
1331 raw_spin_unlock_irqrestore(&chv_lock, flags);
1334 chv_gpio_irq_unmask(d);
1338 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1341 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1342 struct intel_community_context *cctx = &pctrl->context.communities[0];
1343 unsigned int pin = irqd_to_hwirq(d);
1344 unsigned long flags;
1347 raw_spin_lock_irqsave(&chv_lock, flags);
1350 * Pins which can be used as shared interrupt are configured in
1351 * BIOS. Driver trusts BIOS configurations and assigns different
1352 * handler according to the irq type.
1354 * Driver needs to save the mapping between each pin and
1355 * its interrupt line.
1356 * 1. If the pin cfg is locked in BIOS:
1357 * Trust BIOS has programmed IntWakeCfg bits correctly,
1358 * driver just needs to save the mapping.
1359 * 2. If the pin cfg is not locked in BIOS:
1360 * Driver programs the IntWakeCfg bits and save the mapping.
1362 if (!chv_pad_locked(pctrl, pin)) {
1363 value = chv_readl(pctrl, pin, CHV_PADCTRL1);
1364 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1365 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1367 if (type & IRQ_TYPE_EDGE_BOTH) {
1368 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1369 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1370 else if (type & IRQ_TYPE_EDGE_RISING)
1371 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1372 else if (type & IRQ_TYPE_EDGE_FALLING)
1373 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1374 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1375 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1376 if (type & IRQ_TYPE_LEVEL_LOW)
1377 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1380 chv_writel(pctrl, pin, CHV_PADCTRL1, value);
1383 value = chv_readl(pctrl, pin, CHV_PADCTRL0);
1384 value &= CHV_PADCTRL0_INTSEL_MASK;
1385 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1387 cctx->intr_lines[value] = pin;
1389 if (type & IRQ_TYPE_EDGE_BOTH)
1390 irq_set_handler_locked(d, handle_edge_irq);
1391 else if (type & IRQ_TYPE_LEVEL_MASK)
1392 irq_set_handler_locked(d, handle_level_irq);
1394 raw_spin_unlock_irqrestore(&chv_lock, flags);
1399 static void chv_gpio_irq_handler(struct irq_desc *desc)
1401 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1402 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1403 const struct intel_community *community = &pctrl->communities[0];
1404 struct intel_community_context *cctx = &pctrl->context.communities[0];
1405 struct irq_chip *chip = irq_desc_get_chip(desc);
1406 unsigned long pending;
1407 unsigned long flags;
1410 chained_irq_enter(chip, desc);
1412 raw_spin_lock_irqsave(&chv_lock, flags);
1413 pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
1414 raw_spin_unlock_irqrestore(&chv_lock, flags);
1416 for_each_set_bit(intr_line, &pending, community->nirqs) {
1417 unsigned int irq, offset;
1419 offset = cctx->intr_lines[intr_line];
1420 irq = irq_find_mapping(gc->irq.domain, offset);
1421 generic_handle_irq(irq);
1424 chained_irq_exit(chip, desc);
1428 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1429 * tables. Since we leave GPIOs that are not capable of generating
1430 * interrupts out of the irqdomain the numbering will be different and
1431 * cause devices using the hardcoded IRQ numbers fail. In order not to
1432 * break such machines we will only mask pins from irqdomain if the machine
1433 * is not listed below.
1435 static const struct dmi_system_id chv_no_valid_mask[] = {
1436 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1438 .ident = "Intel_Strago based Chromebooks (All models)",
1440 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1441 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1445 .ident = "HP Chromebook 11 G5 (Setzer)",
1447 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1448 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1452 .ident = "Acer Chromebook R11 (Cyan)",
1454 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1455 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1459 .ident = "Samsung Chromebook 3 (Celes)",
1461 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1462 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1468 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1469 unsigned long *valid_mask,
1470 unsigned int ngpios)
1472 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1473 const struct intel_community *community = &pctrl->communities[0];
1476 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1477 for (i = 0; i < pctrl->soc->npins; i++) {
1478 const struct pinctrl_pin_desc *desc;
1481 desc = &pctrl->soc->pins[i];
1483 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1484 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1485 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1487 if (intsel >= community->nirqs)
1488 clear_bit(desc->number, valid_mask);
1492 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1494 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1495 const struct intel_community *community = &pctrl->communities[0];
1498 * The same set of machines in chv_no_valid_mask[] have incorrectly
1499 * configured GPIOs that generate spurious interrupts so we use
1500 * this same list to apply another quirk for them.
1502 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1504 if (!pctrl->chip.irq.init_valid_mask) {
1506 * Mask all interrupts the community is able to generate
1507 * but leave the ones that can only generate GPEs unmasked.
1509 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
1512 /* Clear all interrupts */
1513 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1518 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1520 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1521 const struct intel_community *community = &pctrl->communities[0];
1522 const struct intel_padgroup *gpp;
1525 for (i = 0; i < community->ngpps; i++) {
1526 gpp = &community->gpps[i];
1527 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1528 gpp->base, gpp->base,
1531 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1539 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1541 const struct intel_community *community = &pctrl->communities[0];
1542 const struct intel_padgroup *gpp;
1543 struct gpio_chip *chip = &pctrl->chip;
1544 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1545 int ret, i, irq_base;
1547 *chip = chv_gpio_chip;
1549 chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
1550 chip->label = dev_name(pctrl->dev);
1551 chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1552 chip->parent = pctrl->dev;
1556 pctrl->irqchip.name = "chv-gpio";
1557 pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1558 pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1559 pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1560 pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1561 pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1562 pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1564 chip->irq.chip = &pctrl->irqchip;
1565 chip->irq.init_hw = chv_gpio_irq_init_hw;
1566 chip->irq.parent_handler = chv_gpio_irq_handler;
1567 chip->irq.num_parents = 1;
1568 chip->irq.parents = &pctrl->irq;
1569 chip->irq.default_type = IRQ_TYPE_NONE;
1570 chip->irq.handler = handle_bad_irq;
1571 if (need_valid_mask) {
1572 chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1574 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1575 pctrl->soc->npins, NUMA_NO_NODE);
1577 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1582 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1584 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1588 if (!need_valid_mask) {
1589 for (i = 0; i < community->ngpps; i++) {
1590 gpp = &community->gpps[i];
1592 irq_domain_associate_many(chip->irq.domain, irq_base,
1593 gpp->base, gpp->size);
1594 irq_base += gpp->size;
1601 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1602 acpi_physical_address address, u32 bits, u64 *value,
1603 void *handler_context, void *region_context)
1605 struct intel_pinctrl *pctrl = region_context;
1606 unsigned long flags;
1607 acpi_status ret = AE_OK;
1609 raw_spin_lock_irqsave(&chv_lock, flags);
1611 if (function == ACPI_WRITE)
1612 chv_pctrl_writel(pctrl, address, *value);
1613 else if (function == ACPI_READ)
1614 *value = chv_pctrl_readl(pctrl, address);
1616 ret = AE_BAD_PARAMETER;
1618 raw_spin_unlock_irqrestore(&chv_lock, flags);
1623 static int chv_pinctrl_probe(struct platform_device *pdev)
1625 const struct intel_pinctrl_soc_data *soc_data;
1626 struct intel_community *community;
1627 struct device *dev = &pdev->dev;
1628 struct intel_pinctrl *pctrl;
1632 soc_data = intel_pinctrl_get_soc_data(pdev);
1633 if (IS_ERR(soc_data))
1634 return PTR_ERR(soc_data);
1636 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1641 pctrl->soc = soc_data;
1643 pctrl->ncommunities = pctrl->soc->ncommunities;
1644 pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
1645 pctrl->ncommunities * sizeof(*pctrl->communities),
1647 if (!pctrl->communities)
1650 community = &pctrl->communities[0];
1651 community->regs = devm_platform_ioremap_resource(pdev, 0);
1652 if (IS_ERR(community->regs))
1653 return PTR_ERR(community->regs);
1655 community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
1657 #ifdef CONFIG_PM_SLEEP
1658 pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
1659 sizeof(*pctrl->context.pads),
1661 if (!pctrl->context.pads)
1665 pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
1666 sizeof(*pctrl->context.communities),
1668 if (!pctrl->context.communities)
1671 irq = platform_get_irq(pdev, 0);
1675 pctrl->pctldesc = chv_pinctrl_desc;
1676 pctrl->pctldesc.name = dev_name(dev);
1677 pctrl->pctldesc.pins = pctrl->soc->pins;
1678 pctrl->pctldesc.npins = pctrl->soc->npins;
1680 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1681 if (IS_ERR(pctrl->pctldev)) {
1682 dev_err(dev, "failed to register pinctrl driver\n");
1683 return PTR_ERR(pctrl->pctldev);
1686 ret = chv_gpio_probe(pctrl, irq);
1690 status = acpi_install_address_space_handler(ACPI_HANDLE(dev),
1691 community->acpi_space_id,
1692 chv_pinctrl_mmio_access_handler,
1694 if (ACPI_FAILURE(status))
1695 dev_err(dev, "failed to install ACPI addr space handler\n");
1697 platform_set_drvdata(pdev, pctrl);
1702 static int chv_pinctrl_remove(struct platform_device *pdev)
1704 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1705 const struct intel_community *community = &pctrl->communities[0];
1707 acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),
1708 community->acpi_space_id,
1709 chv_pinctrl_mmio_access_handler);
1714 #ifdef CONFIG_PM_SLEEP
1715 static int chv_pinctrl_suspend_noirq(struct device *dev)
1717 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1718 struct intel_community_context *cctx = &pctrl->context.communities[0];
1719 unsigned long flags;
1722 raw_spin_lock_irqsave(&chv_lock, flags);
1724 cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
1726 for (i = 0; i < pctrl->soc->npins; i++) {
1727 const struct pinctrl_pin_desc *desc;
1728 struct intel_pad_context *ctx = &pctrl->context.pads[i];
1730 desc = &pctrl->soc->pins[i];
1731 if (chv_pad_locked(pctrl, desc->number))
1734 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1735 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
1737 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1740 raw_spin_unlock_irqrestore(&chv_lock, flags);
1745 static int chv_pinctrl_resume_noirq(struct device *dev)
1747 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1748 struct intel_community_context *cctx = &pctrl->context.communities[0];
1749 unsigned long flags;
1752 raw_spin_lock_irqsave(&chv_lock, flags);
1755 * Mask all interrupts before restoring per-pin configuration
1756 * registers because we don't know in which state BIOS left them
1757 * upon exiting suspend.
1759 chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
1761 for (i = 0; i < pctrl->soc->npins; i++) {
1762 const struct pinctrl_pin_desc *desc;
1763 struct intel_pad_context *ctx = &pctrl->context.pads[i];
1766 desc = &pctrl->soc->pins[i];
1767 if (chv_pad_locked(pctrl, desc->number))
1770 /* Only restore if our saved state differs from the current */
1771 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1772 val &= ~CHV_PADCTRL0_GPIORXSTATE;
1773 if (ctx->padctrl0 != val) {
1774 chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
1775 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1776 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
1779 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1780 if (ctx->padctrl1 != val) {
1781 chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
1782 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1783 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
1788 * Now that all pins are restored to known state, we can restore
1789 * the interrupt mask register as well.
1791 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1792 chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
1794 raw_spin_unlock_irqrestore(&chv_lock, flags);
1800 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1801 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1802 chv_pinctrl_resume_noirq)
1805 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1806 { "INT33FF", (kernel_ulong_t)chv_soc_data },
1809 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1811 static struct platform_driver chv_pinctrl_driver = {
1812 .probe = chv_pinctrl_probe,
1813 .remove = chv_pinctrl_remove,
1815 .name = "cherryview-pinctrl",
1816 .pm = &chv_pinctrl_pm_ops,
1817 .acpi_match_table = chv_pinctrl_acpi_match,
1821 static int __init chv_pinctrl_init(void)
1823 return platform_driver_register(&chv_pinctrl_driver);
1825 subsys_initcall(chv_pinctrl_init);
1827 static void __exit chv_pinctrl_exit(void)
1829 platform_driver_unregister(&chv_pinctrl_driver);
1831 module_exit(chv_pinctrl_exit);
1833 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1834 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1835 MODULE_LICENSE("GPL v2");