drivers/pinctrl/intel/pinctrl-cherryview.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cherryview/Braswell pinctrl driver
   4  *
   5  * Copyright (C) 2014, Intel Corporation
   6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This driver is based on the original Cherryview GPIO driver by
   9  *   Ning Li <ning.li@intel.com>
  10  *   Alan Cox <alan@linux.intel.com>
  11  */
  12
  13 #include <linux/dmi.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/gpio.h>
  19 #include <linux/gpio/driver.h>
  20 #include <linux/acpi.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/platform_device.h>
  26
  27 #define CHV_INTSTAT                     0x300
  28 #define CHV_INTMASK                     0x380
  29
  30 #define FAMILY_PAD_REGS_OFF             0x4400
  31 #define FAMILY_PAD_REGS_SIZE            0x400
  32 #define MAX_FAMILY_PAD_GPIO_NO          15
  33 #define GPIO_REGS_SIZE                  8
  34
  35 #define CHV_PADCTRL0                    0x000
  36 #define CHV_PADCTRL0_INTSEL_SHIFT       28
  37 #define CHV_PADCTRL0_INTSEL_MASK        (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
  38 #define CHV_PADCTRL0_TERM_UP            BIT(23)
  39 #define CHV_PADCTRL0_TERM_SHIFT         20
  40 #define CHV_PADCTRL0_TERM_MASK          (7 << CHV_PADCTRL0_TERM_SHIFT)
  41 #define CHV_PADCTRL0_TERM_20K           1
  42 #define CHV_PADCTRL0_TERM_5K            2
  43 #define CHV_PADCTRL0_TERM_1K            4
  44 #define CHV_PADCTRL0_PMODE_SHIFT        16
  45 #define CHV_PADCTRL0_PMODE_MASK         (0xf << CHV_PADCTRL0_PMODE_SHIFT)
  46 #define CHV_PADCTRL0_GPIOEN             BIT(15)
  47 #define CHV_PADCTRL0_GPIOCFG_SHIFT      8
  48 #define CHV_PADCTRL0_GPIOCFG_MASK       (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
  49 #define CHV_PADCTRL0_GPIOCFG_GPIO       0
  50 #define CHV_PADCTRL0_GPIOCFG_GPO        1
  51 #define CHV_PADCTRL0_GPIOCFG_GPI        2
  52 #define CHV_PADCTRL0_GPIOCFG_HIZ        3
  53 #define CHV_PADCTRL0_GPIOTXSTATE        BIT(1)
  54 #define CHV_PADCTRL0_GPIORXSTATE        BIT(0)
  55
  56 #define CHV_PADCTRL1                    0x004
  57 #define CHV_PADCTRL1_CFGLOCK            BIT(31)
  58 #define CHV_PADCTRL1_INVRXTX_SHIFT      4
  59 #define CHV_PADCTRL1_INVRXTX_MASK       (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
  60 #define CHV_PADCTRL1_INVRXTX_TXENABLE   (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
  61 #define CHV_PADCTRL1_ODEN               BIT(3)
  62 #define CHV_PADCTRL1_INVRXTX_RXDATA     (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
  63 #define CHV_PADCTRL1_INTWAKECFG_MASK    7
  64 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
  65 #define CHV_PADCTRL1_INTWAKECFG_RISING  2
  66 #define CHV_PADCTRL1_INTWAKECFG_BOTH    3
  67 #define CHV_PADCTRL1_INTWAKECFG_LEVEL   4
  68
  69 /**
  70  * struct chv_alternate_function - A per group or per pin alternate function
  71  * @pin: Pin number (only used in per pin configs)
  72  * @mode: Mode the pin should be set in
  73  * @invert_oe: Invert OE for this pin
  74  */
  75 struct chv_alternate_function {
  76         unsigned pin;
  77         u8 mode;
  78         bool invert_oe;
  79 };
  80
  81 /**
  82  * struct chv_pincgroup - describes a CHV pin group
  83  * @name: Name of the group
  84  * @pins: An array of pins in this group
  85  * @npins: Number of pins in this group
  86  * @altfunc: Alternate function applied to all pins in this group
  87  * @overrides: Alternate function override per pin or %NULL if not used
  88  * @noverrides: Number of per pin alternate function overrides if
  89  *              @overrides != NULL.
  90  */
  91 struct chv_pingroup {
  92         const char *name;
  93         const unsigned *pins;
  94         size_t npins;
  95         struct chv_alternate_function altfunc;
  96         const struct chv_alternate_function *overrides;
  97         size_t noverrides;
  98 };
  99
 100 /**
 101  * struct chv_function - A CHV pinmux function
 102  * @name: Name of the function
 103  * @groups: An array of groups for this function
 104  * @ngroups: Number of groups in @groups
 105  */
 106 struct chv_function {
 107         const char *name;
 108         const char * const *groups;
 109         size_t ngroups;
 110 };
 111
 112 /**
 113  * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
 114  * @base: Start pin number
 115  * @npins: Number of pins in this range
 116  */
 117 struct chv_gpio_pinrange {
 118         unsigned base;
 119         unsigned npins;
 120 };
 121
 122 /**
 123  * struct chv_community - A community specific configuration
 124  * @uid: ACPI _UID used to match the community
 125  * @pins: All pins in this community
 126  * @npins: Number of pins
 127  * @groups: All groups in this community
 128  * @ngroups: Number of groups
 129  * @functions: All functions in this community
 130  * @nfunctions: Number of functions
 131  * @gpio_ranges: An array of GPIO ranges in this community
 132  * @ngpio_ranges: Number of GPIO ranges
 133  * @nirqs: Total number of IRQs this community can generate
 134  */
 135 struct chv_community {
 136         const char *uid;
 137         const struct pinctrl_pin_desc *pins;
 138         size_t npins;
 139         const struct chv_pingroup *groups;
 140         size_t ngroups;
 141         const struct chv_function *functions;
 142         size_t nfunctions;
 143         const struct chv_gpio_pinrange *gpio_ranges;
 144         size_t ngpio_ranges;
 145         size_t nirqs;
 146         acpi_adr_space_type acpi_space_id;
 147 };
 148
 149 struct chv_pin_context {
 150         u32 padctrl0;
 151         u32 padctrl1;
 152 };
 153
 154 /**
 155  * struct chv_pinctrl - CHV pinctrl private structure
 156  * @dev: Pointer to the parent device
 157  * @pctldesc: Pin controller description
 158  * @pctldev: Pointer to the pin controller device
 159  * @chip: GPIO chip in this pin controller
 160  * @irqchip: IRQ chip in this pin controller
 161  * @regs: MMIO registers
 162  * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
 163  *              offset (in GPIO number space)
 164  * @community: Community this pinctrl instance represents
 165  *
 166  * The first group in @groups is expected to contain all pins that can be
 167  * used as GPIOs.
 168  */
 169 struct chv_pinctrl {
 170         struct device *dev;
 171         struct pinctrl_desc pctldesc;
 172         struct pinctrl_dev *pctldev;
 173         struct gpio_chip chip;
 174         struct irq_chip irqchip;
 175         void __iomem *regs;
 176         unsigned intr_lines[16];
 177         const struct chv_community *community;
 178         u32 saved_intmask;
 179         struct chv_pin_context *saved_pin_context;
 180 };
 181
 182 #define ALTERNATE_FUNCTION(p, m, i)             \
 183         {                                       \
 184                 .pin = (p),                     \
 185                 .mode = (m),                    \
 186                 .invert_oe = (i),               \
 187         }
 188
 189 #define PIN_GROUP(n, p, m, i)                   \
 190         {                                       \
 191                 .name = (n),                    \
 192                 .pins = (p),                    \
 193                 .npins = ARRAY_SIZE((p)),       \
 194                 .altfunc.mode = (m),            \
 195                 .altfunc.invert_oe = (i),       \
 196         }
 197
 198 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o)  \
 199         {                                       \
 200                 .name = (n),                    \
 201                 .pins = (p),                    \
 202                 .npins = ARRAY_SIZE((p)),       \
 203                 .altfunc.mode = (m),            \
 204                 .altfunc.invert_oe = (i),       \
 205                 .overrides = (o),               \
 206                 .noverrides = ARRAY_SIZE((o)),  \
 207         }
 208
 209 #define FUNCTION(n, g)                          \
 210         {                                       \
 211                 .name = (n),                    \
 212                 .groups = (g),                  \
 213                 .ngroups = ARRAY_SIZE((g)),     \
 214         }
 215
 216 #define GPIO_PINRANGE(start, end)               \
 217         {                                       \
 218                 .base = (start),                \
 219                 .npins = (end) - (start) + 1,   \
 220         }
 221
 222 static const struct pinctrl_pin_desc southwest_pins[] = {
 223         PINCTRL_PIN(0, "FST_SPI_D2"),
 224         PINCTRL_PIN(1, "FST_SPI_D0"),
 225         PINCTRL_PIN(2, "FST_SPI_CLK"),
 226         PINCTRL_PIN(3, "FST_SPI_D3"),
 227         PINCTRL_PIN(4, "FST_SPI_CS1_B"),
 228         PINCTRL_PIN(5, "FST_SPI_D1"),
 229         PINCTRL_PIN(6, "FST_SPI_CS0_B"),
 230         PINCTRL_PIN(7, "FST_SPI_CS2_B"),
 231
 232         PINCTRL_PIN(15, "UART1_RTS_B"),
 233         PINCTRL_PIN(16, "UART1_RXD"),
 234         PINCTRL_PIN(17, "UART2_RXD"),
 235         PINCTRL_PIN(18, "UART1_CTS_B"),
 236         PINCTRL_PIN(19, "UART2_RTS_B"),
 237         PINCTRL_PIN(20, "UART1_TXD"),
 238         PINCTRL_PIN(21, "UART2_TXD"),
 239         PINCTRL_PIN(22, "UART2_CTS_B"),
 240
 241         PINCTRL_PIN(30, "MF_HDA_CLK"),
 242         PINCTRL_PIN(31, "MF_HDA_RSTB"),
 243         PINCTRL_PIN(32, "MF_HDA_SDIO"),
 244         PINCTRL_PIN(33, "MF_HDA_SDO"),
 245         PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
 246         PINCTRL_PIN(35, "MF_HDA_SYNC"),
 247         PINCTRL_PIN(36, "MF_HDA_SDI1"),
 248         PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
 249
 250         PINCTRL_PIN(45, "I2C5_SDA"),
 251         PINCTRL_PIN(46, "I2C4_SDA"),
 252         PINCTRL_PIN(47, "I2C6_SDA"),
 253         PINCTRL_PIN(48, "I2C5_SCL"),
 254         PINCTRL_PIN(49, "I2C_NFC_SDA"),
 255         PINCTRL_PIN(50, "I2C4_SCL"),
 256         PINCTRL_PIN(51, "I2C6_SCL"),
 257         PINCTRL_PIN(52, "I2C_NFC_SCL"),
 258
 259         PINCTRL_PIN(60, "I2C1_SDA"),
 260         PINCTRL_PIN(61, "I2C0_SDA"),
 261         PINCTRL_PIN(62, "I2C2_SDA"),
 262         PINCTRL_PIN(63, "I2C1_SCL"),
 263         PINCTRL_PIN(64, "I2C3_SDA"),
 264         PINCTRL_PIN(65, "I2C0_SCL"),
 265         PINCTRL_PIN(66, "I2C2_SCL"),
 266         PINCTRL_PIN(67, "I2C3_SCL"),
 267
 268         PINCTRL_PIN(75, "SATA_GP0"),
 269         PINCTRL_PIN(76, "SATA_GP1"),
 270         PINCTRL_PIN(77, "SATA_LEDN"),
 271         PINCTRL_PIN(78, "SATA_GP2"),
 272         PINCTRL_PIN(79, "MF_SMB_ALERTB"),
 273         PINCTRL_PIN(80, "SATA_GP3"),
 274         PINCTRL_PIN(81, "MF_SMB_CLK"),
 275         PINCTRL_PIN(82, "MF_SMB_DATA"),
 276
 277         PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
 278         PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
 279         PINCTRL_PIN(92, "GP_SSP_2_CLK"),
 280         PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
 281         PINCTRL_PIN(94, "GP_SSP_2_RXD"),
 282         PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
 283         PINCTRL_PIN(96, "GP_SSP_2_FS"),
 284         PINCTRL_PIN(97, "GP_SSP_2_TXD"),
 285 };
 286
 287 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 288 static const unsigned southwest_uart0_pins[] = { 16, 20 };
 289 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
 290 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
 291 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
 292 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
 293 static const unsigned southwest_lpe_pins[] = {
 294         30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
 295 };
 296 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
 297 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
 298 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
 299 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
 300 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
 301 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
 302 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
 303 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
 304 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
 305
 306 /* LPE I2S TXD pins need to have invert_oe set */
 307 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
 308         ALTERNATE_FUNCTION(30, 1, true),
 309         ALTERNATE_FUNCTION(34, 1, true),
 310         ALTERNATE_FUNCTION(97, 1, true),
 311 };
 312
 313 /*
 314  * Two spi3 chipselects are available in different mode than the main spi3
 315  * functionality, which is using mode 1.
 316  */
 317 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
 318         ALTERNATE_FUNCTION(76, 3, false),
 319         ALTERNATE_FUNCTION(80, 3, false),
 320 };
 321
 322 static const struct chv_pingroup southwest_groups[] = {
 323         PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
 324         PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
 325         PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
 326         PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
 327         PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
 328         PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
 329         PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
 330         PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
 331         PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
 332         PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
 333         PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
 334         PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
 335
 336         PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
 337                                 southwest_lpe_altfuncs),
 338         PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
 339                                 southwest_spi3_altfuncs),
 340 };
 341
 342 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
 343 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
 344 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
 345 static const char * const southwest_hda_groups[] = { "hda_grp" };
 346 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
 347 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
 348 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
 349 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
 350 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
 351 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
 352 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
 353 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
 354 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
 355 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
 356
 357 /*
 358  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
 359  * enabled only as GPIOs.
 360  */
 361 static const struct chv_function southwest_functions[] = {
 362         FUNCTION("uart0", southwest_uart0_groups),
 363         FUNCTION("uart1", southwest_uart1_groups),
 364         FUNCTION("uart2", southwest_uart2_groups),
 365         FUNCTION("hda", southwest_hda_groups),
 366         FUNCTION("lpe", southwest_lpe_groups),
 367         FUNCTION("i2c0", southwest_i2c0_groups),
 368         FUNCTION("i2c1", southwest_i2c1_groups),
 369         FUNCTION("i2c2", southwest_i2c2_groups),
 370         FUNCTION("i2c3", southwest_i2c3_groups),
 371         FUNCTION("i2c4", southwest_i2c4_groups),
 372         FUNCTION("i2c5", southwest_i2c5_groups),
 373         FUNCTION("i2c6", southwest_i2c6_groups),
 374         FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
 375         FUNCTION("spi3", southwest_spi3_groups),
 376 };
 377
 378 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
 379         GPIO_PINRANGE(0, 7),
 380         GPIO_PINRANGE(15, 22),
 381         GPIO_PINRANGE(30, 37),
 382         GPIO_PINRANGE(45, 52),
 383         GPIO_PINRANGE(60, 67),
 384         GPIO_PINRANGE(75, 82),
 385         GPIO_PINRANGE(90, 97),
 386 };
 387
 388 static const struct chv_community southwest_community = {
 389         .uid = "1",
 390         .pins = southwest_pins,
 391         .npins = ARRAY_SIZE(southwest_pins),
 392         .groups = southwest_groups,
 393         .ngroups = ARRAY_SIZE(southwest_groups),
 394         .functions = southwest_functions,
 395         .nfunctions = ARRAY_SIZE(southwest_functions),
 396         .gpio_ranges = southwest_gpio_ranges,
 397         .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
 398         /*
 399          * Southwest community can benerate GPIO interrupts only for the
 400          * first 8 interrupts. The upper half (8-15) can only be used to
 401          * trigger GPEs.
 402          */
 403         .nirqs = 8,
 404         .acpi_space_id = 0x91,
 405 };
 406
 407 static const struct pinctrl_pin_desc north_pins[] = {
 408         PINCTRL_PIN(0, "GPIO_DFX_0"),
 409         PINCTRL_PIN(1, "GPIO_DFX_3"),
 410         PINCTRL_PIN(2, "GPIO_DFX_7"),
 411         PINCTRL_PIN(3, "GPIO_DFX_1"),
 412         PINCTRL_PIN(4, "GPIO_DFX_5"),
 413         PINCTRL_PIN(5, "GPIO_DFX_4"),
 414         PINCTRL_PIN(6, "GPIO_DFX_8"),
 415         PINCTRL_PIN(7, "GPIO_DFX_2"),
 416         PINCTRL_PIN(8, "GPIO_DFX_6"),
 417
 418         PINCTRL_PIN(15, "GPIO_SUS0"),
 419         PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
 420         PINCTRL_PIN(17, "GPIO_SUS3"),
 421         PINCTRL_PIN(18, "GPIO_SUS7"),
 422         PINCTRL_PIN(19, "GPIO_SUS1"),
 423         PINCTRL_PIN(20, "GPIO_SUS5"),
 424         PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
 425         PINCTRL_PIN(22, "GPIO_SUS4"),
 426         PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
 427         PINCTRL_PIN(24, "GPIO_SUS2"),
 428         PINCTRL_PIN(25, "GPIO_SUS6"),
 429         PINCTRL_PIN(26, "CX_PREQ_B"),
 430         PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
 431
 432         PINCTRL_PIN(30, "TRST_B"),
 433         PINCTRL_PIN(31, "TCK"),
 434         PINCTRL_PIN(32, "PROCHOT_B"),
 435         PINCTRL_PIN(33, "SVIDO_DATA"),
 436         PINCTRL_PIN(34, "TMS"),
 437         PINCTRL_PIN(35, "CX_PRDY_B_2"),
 438         PINCTRL_PIN(36, "TDO_2"),
 439         PINCTRL_PIN(37, "CX_PRDY_B"),
 440         PINCTRL_PIN(38, "SVIDO_ALERT_B"),
 441         PINCTRL_PIN(39, "TDO"),
 442         PINCTRL_PIN(40, "SVIDO_CLK"),
 443         PINCTRL_PIN(41, "TDI"),
 444
 445         PINCTRL_PIN(45, "GP_CAMERASB_05"),
 446         PINCTRL_PIN(46, "GP_CAMERASB_02"),
 447         PINCTRL_PIN(47, "GP_CAMERASB_08"),
 448         PINCTRL_PIN(48, "GP_CAMERASB_00"),
 449         PINCTRL_PIN(49, "GP_CAMERASB_06"),
 450         PINCTRL_PIN(50, "GP_CAMERASB_10"),
 451         PINCTRL_PIN(51, "GP_CAMERASB_03"),
 452         PINCTRL_PIN(52, "GP_CAMERASB_09"),
 453         PINCTRL_PIN(53, "GP_CAMERASB_01"),
 454         PINCTRL_PIN(54, "GP_CAMERASB_07"),
 455         PINCTRL_PIN(55, "GP_CAMERASB_11"),
 456         PINCTRL_PIN(56, "GP_CAMERASB_04"),
 457
 458         PINCTRL_PIN(60, "PANEL0_BKLTEN"),
 459         PINCTRL_PIN(61, "HV_DDI0_HPD"),
 460         PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
 461         PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
 462         PINCTRL_PIN(64, "HV_DDI1_HPD"),
 463         PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
 464         PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
 465         PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
 466         PINCTRL_PIN(68, "HV_DDI2_HPD"),
 467         PINCTRL_PIN(69, "PANEL1_VDDEN"),
 468         PINCTRL_PIN(70, "PANEL1_BKLTEN"),
 469         PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
 470         PINCTRL_PIN(72, "PANEL0_VDDEN"),
 471 };
 472
 473 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
 474         GPIO_PINRANGE(0, 8),
 475         GPIO_PINRANGE(15, 27),
 476         GPIO_PINRANGE(30, 41),
 477         GPIO_PINRANGE(45, 56),
 478         GPIO_PINRANGE(60, 72),
 479 };
 480
 481 static const struct chv_community north_community = {
 482         .uid = "2",
 483         .pins = north_pins,
 484         .npins = ARRAY_SIZE(north_pins),
 485         .gpio_ranges = north_gpio_ranges,
 486         .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
 487         /*
 488          * North community can generate GPIO interrupts only for the first
 489          * 8 interrupts. The upper half (8-15) can only be used to trigger
 490          * GPEs.
 491          */
 492         .nirqs = 8,
 493         .acpi_space_id = 0x92,
 494 };
 495
 496 static const struct pinctrl_pin_desc east_pins[] = {
 497         PINCTRL_PIN(0, "PMU_SLP_S3_B"),
 498         PINCTRL_PIN(1, "PMU_BATLOW_B"),
 499         PINCTRL_PIN(2, "SUS_STAT_B"),
 500         PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
 501         PINCTRL_PIN(4, "PMU_AC_PRESENT"),
 502         PINCTRL_PIN(5, "PMU_PLTRST_B"),
 503         PINCTRL_PIN(6, "PMU_SUSCLK"),
 504         PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
 505         PINCTRL_PIN(8, "PMU_PWRBTN_B"),
 506         PINCTRL_PIN(9, "PMU_SLP_S4_B"),
 507         PINCTRL_PIN(10, "PMU_WAKE_B"),
 508         PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
 509
 510         PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
 511         PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
 512         PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
 513         PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
 514         PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
 515         PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
 516         PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
 517         PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
 518         PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
 519         PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
 520         PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
 521         PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
 522 };
 523
 524 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
 525         GPIO_PINRANGE(0, 11),
 526         GPIO_PINRANGE(15, 26),
 527 };
 528
 529 static const struct chv_community east_community = {
 530         .uid = "3",
 531         .pins = east_pins,
 532         .npins = ARRAY_SIZE(east_pins),
 533         .gpio_ranges = east_gpio_ranges,
 534         .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
 535         .nirqs = 16,
 536         .acpi_space_id = 0x93,
 537 };
 538
 539 static const struct pinctrl_pin_desc southeast_pins[] = {
 540         PINCTRL_PIN(0, "MF_PLT_CLK0"),
 541         PINCTRL_PIN(1, "PWM1"),
 542         PINCTRL_PIN(2, "MF_PLT_CLK1"),
 543         PINCTRL_PIN(3, "MF_PLT_CLK4"),
 544         PINCTRL_PIN(4, "MF_PLT_CLK3"),
 545         PINCTRL_PIN(5, "PWM0"),
 546         PINCTRL_PIN(6, "MF_PLT_CLK5"),
 547         PINCTRL_PIN(7, "MF_PLT_CLK2"),
 548
 549         PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
 550         PINCTRL_PIN(16, "SDMMC1_CLK"),
 551         PINCTRL_PIN(17, "SDMMC1_D0"),
 552         PINCTRL_PIN(18, "SDMMC2_D1"),
 553         PINCTRL_PIN(19, "SDMMC2_CLK"),
 554         PINCTRL_PIN(20, "SDMMC1_D2"),
 555         PINCTRL_PIN(21, "SDMMC2_D2"),
 556         PINCTRL_PIN(22, "SDMMC2_CMD"),
 557         PINCTRL_PIN(23, "SDMMC1_CMD"),
 558         PINCTRL_PIN(24, "SDMMC1_D1"),
 559         PINCTRL_PIN(25, "SDMMC2_D0"),
 560         PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
 561
 562         PINCTRL_PIN(30, "SDMMC3_D1"),
 563         PINCTRL_PIN(31, "SDMMC3_CLK"),
 564         PINCTRL_PIN(32, "SDMMC3_D3"),
 565         PINCTRL_PIN(33, "SDMMC3_D2"),
 566         PINCTRL_PIN(34, "SDMMC3_CMD"),
 567         PINCTRL_PIN(35, "SDMMC3_D0"),
 568
 569         PINCTRL_PIN(45, "MF_LPC_AD2"),
 570         PINCTRL_PIN(46, "LPC_CLKRUNB"),
 571         PINCTRL_PIN(47, "MF_LPC_AD0"),
 572         PINCTRL_PIN(48, "LPC_FRAMEB"),
 573         PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
 574         PINCTRL_PIN(50, "MF_LPC_AD3"),
 575         PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
 576         PINCTRL_PIN(52, "MF_LPC_AD1"),
 577
 578         PINCTRL_PIN(60, "SPI1_MISO"),
 579         PINCTRL_PIN(61, "SPI1_CSO_B"),
 580         PINCTRL_PIN(62, "SPI1_CLK"),
 581         PINCTRL_PIN(63, "MMC1_D6"),
 582         PINCTRL_PIN(64, "SPI1_MOSI"),
 583         PINCTRL_PIN(65, "MMC1_D5"),
 584         PINCTRL_PIN(66, "SPI1_CS1_B"),
 585         PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
 586         PINCTRL_PIN(68, "MMC1_D7"),
 587         PINCTRL_PIN(69, "MMC1_RCLK"),
 588
 589         PINCTRL_PIN(75, "USB_OC1_B"),
 590         PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
 591         PINCTRL_PIN(77, "GPIO_ALERT"),
 592         PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
 593         PINCTRL_PIN(79, "ILB_SERIRQ"),
 594         PINCTRL_PIN(80, "USB_OC0_B"),
 595         PINCTRL_PIN(81, "SDMMC3_CD_B"),
 596         PINCTRL_PIN(82, "SPKR"),
 597         PINCTRL_PIN(83, "SUSPWRDNACK"),
 598         PINCTRL_PIN(84, "SPARE_PIN"),
 599         PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
 600 };
 601
 602 static const unsigned southeast_pwm0_pins[] = { 5 };
 603 static const unsigned southeast_pwm1_pins[] = { 1 };
 604 static const unsigned southeast_sdmmc1_pins[] = {
 605         16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
 606 };
 607 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
 608 static const unsigned southeast_sdmmc3_pins[] = {
 609         30, 31, 32, 33, 34, 35, 78, 81, 85,
 610 };
 611 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
 612 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
 613
 614 static const struct chv_pingroup southeast_groups[] = {
 615         PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
 616         PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
 617         PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
 618         PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
 619         PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
 620         PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
 621         PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
 622 };
 623
 624 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
 625 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
 626 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
 627 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
 628 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
 629 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
 630 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
 631
 632 static const struct chv_function southeast_functions[] = {
 633         FUNCTION("pwm0", southeast_pwm0_groups),
 634         FUNCTION("pwm1", southeast_pwm1_groups),
 635         FUNCTION("sdmmc1", southeast_sdmmc1_groups),
 636         FUNCTION("sdmmc2", southeast_sdmmc2_groups),
 637         FUNCTION("sdmmc3", southeast_sdmmc3_groups),
 638         FUNCTION("spi1", southeast_spi1_groups),
 639         FUNCTION("spi2", southeast_spi2_groups),
 640 };
 641
 642 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
 643         GPIO_PINRANGE(0, 7),
 644         GPIO_PINRANGE(15, 26),
 645         GPIO_PINRANGE(30, 35),
 646         GPIO_PINRANGE(45, 52),
 647         GPIO_PINRANGE(60, 69),
 648         GPIO_PINRANGE(75, 85),
 649 };
 650
 651 static const struct chv_community southeast_community = {
 652         .uid = "4",
 653         .pins = southeast_pins,
 654         .npins = ARRAY_SIZE(southeast_pins),
 655         .groups = southeast_groups,
 656         .ngroups = ARRAY_SIZE(southeast_groups),
 657         .functions = southeast_functions,
 658         .nfunctions = ARRAY_SIZE(southeast_functions),
 659         .gpio_ranges = southeast_gpio_ranges,
 660         .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
 661         .nirqs = 16,
 662         .acpi_space_id = 0x94,
 663 };
 664
 665 static const struct chv_community *chv_communities[] = {
 666         &southwest_community,
 667         &north_community,
 668         &east_community,
 669         &southeast_community,
 670 };
 671
 672 /*
 673  * Lock to serialize register accesses
 674  *
 675  * Due to a silicon issue, a shared lock must be used to prevent
 676  * concurrent accesses across the 4 GPIO controllers.
 677  *
 678  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
 679  * errata #CHT34, for further information.
 680  */
 681 static DEFINE_RAW_SPINLOCK(chv_lock);
 682
 683 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
 684                                 unsigned reg)
 685 {
 686         unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
 687         unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
 688
 689         offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
 690                  GPIO_REGS_SIZE * pad_no;
 691
 692         return pctrl->regs + offset + reg;
 693 }
 694
 695 static void chv_writel(u32 value, void __iomem *reg)
 696 {
 697         writel(value, reg);
 698         /* simple readback to confirm the bus transferring done */
 699         readl(reg);
 700 }
 701
 702 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
 703 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
 704 {
 705         void __iomem *reg;
 706
 707         reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 708         return readl(reg) & CHV_PADCTRL1_CFGLOCK;
 709 }
 710
 711 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
 712 {
 713         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 714
 715         return pctrl->community->ngroups;
 716 }
 717
 718 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
 719                                       unsigned group)
 720 {
 721         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 722
 723         return pctrl->community->groups[group].name;
 724 }
 725
 726 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 727                               const unsigned **pins, unsigned *npins)
 728 {
 729         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 730
 731         *pins = pctrl->community->groups[group].pins;
 732         *npins = pctrl->community->groups[group].npins;
 733         return 0;
 734 }
 735
 736 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 737                              unsigned offset)
 738 {
 739         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 740         unsigned long flags;
 741         u32 ctrl0, ctrl1;
 742         bool locked;
 743
 744         raw_spin_lock_irqsave(&chv_lock, flags);
 745
 746         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 747         ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
 748         locked = chv_pad_locked(pctrl, offset);
 749
 750         raw_spin_unlock_irqrestore(&chv_lock, flags);
 751
 752         if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
 753                 seq_puts(s, "GPIO ");
 754         } else {
 755                 u32 mode;
 756
 757                 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
 758                 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
 759
 760                 seq_printf(s, "mode %d ", mode);
 761         }
 762
 763         seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
 764
 765         if (locked)
 766                 seq_puts(s, " [LOCKED]");
 767 }
 768
 769 static const struct pinctrl_ops chv_pinctrl_ops = {
 770         .get_groups_count = chv_get_groups_count,
 771         .get_group_name = chv_get_group_name,
 772         .get_group_pins = chv_get_group_pins,
 773         .pin_dbg_show = chv_pin_dbg_show,
 774 };
 775
 776 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
 777 {
 778         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 779
 780         return pctrl->community->nfunctions;
 781 }
 782
 783 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
 784                                          unsigned function)
 785 {
 786         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 787
 788         return pctrl->community->functions[function].name;
 789 }
 790
 791 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
 792                                    unsigned function,
 793                                    const char * const **groups,
 794                                    unsigned * const ngroups)
 795 {
 796         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 797
 798         *groups = pctrl->community->functions[function].groups;
 799         *ngroups = pctrl->community->functions[function].ngroups;
 800         return 0;
 801 }
 802
 803 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 804                               unsigned group)
 805 {
 806         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 807         const struct chv_pingroup *grp;
 808         unsigned long flags;
 809         int i;
 810
 811         grp = &pctrl->community->groups[group];
 812
 813         raw_spin_lock_irqsave(&chv_lock, flags);
 814
 815         /* Check first that the pad is not locked */
 816         for (i = 0; i < grp->npins; i++) {
 817                 if (chv_pad_locked(pctrl, grp->pins[i])) {
 818                         dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
 819                                  grp->pins[i]);
 820                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 821                         return -EBUSY;
 822                 }
 823         }
 824
 825         for (i = 0; i < grp->npins; i++) {
 826                 const struct chv_alternate_function *altfunc = &grp->altfunc;
 827                 int pin = grp->pins[i];
 828                 void __iomem *reg;
 829                 u32 value;
 830
 831                 /* Check if there is pin-specific config */
 832                 if (grp->overrides) {
 833                         int j;
 834
 835                         for (j = 0; j < grp->noverrides; j++) {
 836                                 if (grp->overrides[j].pin == pin) {
 837                                         altfunc = &grp->overrides[j];
 838                                         break;
 839                                 }
 840                         }
 841                 }
 842
 843                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
 844                 value = readl(reg);
 845                 /* Disable GPIO mode */
 846                 value &= ~CHV_PADCTRL0_GPIOEN;
 847                 /* Set to desired mode */
 848                 value &= ~CHV_PADCTRL0_PMODE_MASK;
 849                 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
 850                 chv_writel(value, reg);
 851
 852                 /* Update for invert_oe */
 853                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
 854                 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
 855                 if (altfunc->invert_oe)
 856                         value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
 857                 chv_writel(value, reg);
 858
 859                 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
 860                         pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
 861         }
 862
 863         raw_spin_unlock_irqrestore(&chv_lock, flags);
 864
 865         return 0;
 866 }
 867
 868 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
 869                                    struct pinctrl_gpio_range *range,
 870                                    unsigned offset)
 871 {
 872         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 873         unsigned long flags;
 874         void __iomem *reg;
 875         u32 value;
 876
 877         raw_spin_lock_irqsave(&chv_lock, flags);
 878
 879         if (chv_pad_locked(pctrl, offset)) {
 880                 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 881                 if (!(value & CHV_PADCTRL0_GPIOEN)) {
 882                         /* Locked so cannot enable */
 883                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 884                         return -EBUSY;
 885                 }
 886         } else {
 887                 int i;
 888
 889                 /* Reset the interrupt mapping */
 890                 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
 891                         if (pctrl->intr_lines[i] == offset) {
 892                                 pctrl->intr_lines[i] = 0;
 893                                 break;
 894                         }
 895                 }
 896
 897                 /* Disable interrupt generation */
 898                 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 899                 value = readl(reg);
 900                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
 901                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
 902                 chv_writel(value, reg);
 903
 904                 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 905                 value = readl(reg);
 906
 907                 /*
 908                  * If the pin is in HiZ mode (both TX and RX buffers are
 909                  * disabled) we turn it to be input now.
 910                  */
 911                 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
 912                      (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
 913                         value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
 914                         value |= CHV_PADCTRL0_GPIOCFG_GPI <<
 915                                 CHV_PADCTRL0_GPIOCFG_SHIFT;
 916                 }
 917
 918                 /* Switch to a GPIO mode */
 919                 value |= CHV_PADCTRL0_GPIOEN;
 920                 chv_writel(value, reg);
 921         }
 922
 923         raw_spin_unlock_irqrestore(&chv_lock, flags);
 924
 925         return 0;
 926 }
 927
 928 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
 929                                   struct pinctrl_gpio_range *range,
 930                                   unsigned offset)
 931 {
 932         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 933         unsigned long flags;
 934         void __iomem *reg;
 935         u32 value;
 936
 937         raw_spin_lock_irqsave(&chv_lock, flags);
 938
 939         reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 940         value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
 941         chv_writel(value, reg);
 942
 943         raw_spin_unlock_irqrestore(&chv_lock, flags);
 944 }
 945
 946 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
 947                                   struct pinctrl_gpio_range *range,
 948                                   unsigned offset, bool input)
 949 {
 950         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 951         void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 952         unsigned long flags;
 953         u32 ctrl0;
 954
 955         raw_spin_lock_irqsave(&chv_lock, flags);
 956
 957         ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
 958         if (input)
 959                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 960         else
 961                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
 962         chv_writel(ctrl0, reg);
 963
 964         raw_spin_unlock_irqrestore(&chv_lock, flags);
 965
 966         return 0;
 967 }
 968
 969 static const struct pinmux_ops chv_pinmux_ops = {
 970         .get_functions_count = chv_get_functions_count,
 971         .get_function_name = chv_get_function_name,
 972         .get_function_groups = chv_get_function_groups,
 973         .set_mux = chv_pinmux_set_mux,
 974         .gpio_request_enable = chv_gpio_request_enable,
 975         .gpio_disable_free = chv_gpio_disable_free,
 976         .gpio_set_direction = chv_gpio_set_direction,
 977 };
 978
 979 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 980                           unsigned long *config)
 981 {
 982         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 983         enum pin_config_param param = pinconf_to_config_param(*config);
 984         unsigned long flags;
 985         u32 ctrl0, ctrl1;
 986         u16 arg = 0;
 987         u32 term;
 988
 989         raw_spin_lock_irqsave(&chv_lock, flags);
 990         ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
 991         ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
 992         raw_spin_unlock_irqrestore(&chv_lock, flags);
 993
 994         term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
 995
 996         switch (param) {
 997         case PIN_CONFIG_BIAS_DISABLE:
 998                 if (term)
 999                         return -EINVAL;
1000                 break;
1001
1002         case PIN_CONFIG_BIAS_PULL_UP:
1003                 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
1004                         return -EINVAL;
1005
1006                 switch (term) {
1007                 case CHV_PADCTRL0_TERM_20K:
1008                         arg = 20000;
1009                         break;
1010                 case CHV_PADCTRL0_TERM_5K:
1011                         arg = 5000;
1012                         break;
1013                 case CHV_PADCTRL0_TERM_1K:
1014                         arg = 1000;
1015                         break;
1016                 }
1017
1018                 break;
1019
1020         case PIN_CONFIG_BIAS_PULL_DOWN:
1021                 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1022                         return -EINVAL;
1023
1024                 switch (term) {
1025                 case CHV_PADCTRL0_TERM_20K:
1026                         arg = 20000;
1027                         break;
1028                 case CHV_PADCTRL0_TERM_5K:
1029                         arg = 5000;
1030                         break;
1031                 }
1032
1033                 break;
1034
1035         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1036                 u32 cfg;
1037
1038                 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1039                 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1040                 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1041                         return -EINVAL;
1042
1043                 break;
1044
1045         case PIN_CONFIG_DRIVE_PUSH_PULL:
1046                 if (ctrl1 & CHV_PADCTRL1_ODEN)
1047                         return -EINVAL;
1048                 break;
1049
1050         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1051                 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1052                         return -EINVAL;
1053                 break;
1054         }
1055
1056         default:
1057                 return -ENOTSUPP;
1058         }
1059
1060         *config = pinconf_to_config_packed(param, arg);
1061         return 0;
1062 }
1063
1064 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1065                                enum pin_config_param param, u32 arg)
1066 {
1067         void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1068         unsigned long flags;
1069         u32 ctrl0, pull;
1070
1071         raw_spin_lock_irqsave(&chv_lock, flags);
1072         ctrl0 = readl(reg);
1073
1074         switch (param) {
1075         case PIN_CONFIG_BIAS_DISABLE:
1076                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1077                 break;
1078
1079         case PIN_CONFIG_BIAS_PULL_UP:
1080                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1081
1082                 switch (arg) {
1083                 case 1000:
1084                         /* For 1k there is only pull up */
1085                         pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1086                         break;
1087                 case 5000:
1088                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1089                         break;
1090                 case 20000:
1091                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1092                         break;
1093                 default:
1094                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1095                         return -EINVAL;
1096                 }
1097
1098                 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1099                 break;
1100
1101         case PIN_CONFIG_BIAS_PULL_DOWN:
1102                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1103
1104                 switch (arg) {
1105                 case 5000:
1106                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1107                         break;
1108                 case 20000:
1109                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1110                         break;
1111                 default:
1112                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1113                         return -EINVAL;
1114                 }
1115
1116                 ctrl0 |= pull;
1117                 break;
1118
1119         default:
1120                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1121                 return -EINVAL;
1122         }
1123
1124         chv_writel(ctrl0, reg);
1125         raw_spin_unlock_irqrestore(&chv_lock, flags);
1126
1127         return 0;
1128 }
1129
1130 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1131                                bool enable)
1132 {
1133         void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1134         unsigned long flags;
1135         u32 ctrl1;
1136
1137         raw_spin_lock_irqsave(&chv_lock, flags);
1138         ctrl1 = readl(reg);
1139
1140         if (enable)
1141                 ctrl1 |= CHV_PADCTRL1_ODEN;
1142         else
1143                 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1144
1145         chv_writel(ctrl1, reg);
1146         raw_spin_unlock_irqrestore(&chv_lock, flags);
1147
1148         return 0;
1149 }
1150
1151 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1152                           unsigned long *configs, unsigned nconfigs)
1153 {
1154         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1155         enum pin_config_param param;
1156         int i, ret;
1157         u32 arg;
1158
1159         if (chv_pad_locked(pctrl, pin))
1160                 return -EBUSY;
1161
1162         for (i = 0; i < nconfigs; i++) {
1163                 param = pinconf_to_config_param(configs[i]);
1164                 arg = pinconf_to_config_argument(configs[i]);
1165
1166                 switch (param) {
1167                 case PIN_CONFIG_BIAS_DISABLE:
1168                 case PIN_CONFIG_BIAS_PULL_UP:
1169                 case PIN_CONFIG_BIAS_PULL_DOWN:
1170                         ret = chv_config_set_pull(pctrl, pin, param, arg);
1171                         if (ret)
1172                                 return ret;
1173                         break;
1174
1175                 case PIN_CONFIG_DRIVE_PUSH_PULL:
1176                         ret = chv_config_set_oden(pctrl, pin, false);
1177                         if (ret)
1178                                 return ret;
1179                         break;
1180
1181                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1182                         ret = chv_config_set_oden(pctrl, pin, true);
1183                         if (ret)
1184                                 return ret;
1185                         break;
1186
1187                 default:
1188                         return -ENOTSUPP;
1189                 }
1190
1191                 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1192                         param, arg);
1193         }
1194
1195         return 0;
1196 }
1197
1198 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1199                                 unsigned int group,
1200                                 unsigned long *config)
1201 {
1202         const unsigned int *pins;
1203         unsigned int npins;
1204         int ret;
1205
1206         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1207         if (ret)
1208                 return ret;
1209
1210         ret = chv_config_get(pctldev, pins[0], config);
1211         if (ret)
1212                 return ret;
1213
1214         return 0;
1215 }
1216
1217 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1218                                 unsigned int group, unsigned long *configs,
1219                                 unsigned int num_configs)
1220 {
1221         const unsigned int *pins;
1222         unsigned int npins;
1223         int i, ret;
1224
1225         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1226         if (ret)
1227                 return ret;
1228
1229         for (i = 0; i < npins; i++) {
1230                 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1231                 if (ret)
1232                         return ret;
1233         }
1234
1235         return 0;
1236 }
1237
1238 static const struct pinconf_ops chv_pinconf_ops = {
1239         .is_generic = true,
1240         .pin_config_set = chv_config_set,
1241         .pin_config_get = chv_config_get,
1242         .pin_config_group_get = chv_config_group_get,
1243         .pin_config_group_set = chv_config_group_set,
1244 };
1245
1246 static struct pinctrl_desc chv_pinctrl_desc = {
1247         .pctlops = &chv_pinctrl_ops,
1248         .pmxops = &chv_pinmux_ops,
1249         .confops = &chv_pinconf_ops,
1250         .owner = THIS_MODULE,
1251 };
1252
1253 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1254 {
1255         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1256         unsigned long flags;
1257         u32 ctrl0, cfg;
1258
1259         raw_spin_lock_irqsave(&chv_lock, flags);
1260         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1261         raw_spin_unlock_irqrestore(&chv_lock, flags);
1262
1263         cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1264         cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1265
1266         if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1267                 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1268         return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1269 }
1270
1271 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1272 {
1273         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1274         unsigned long flags;
1275         void __iomem *reg;
1276         u32 ctrl0;
1277
1278         raw_spin_lock_irqsave(&chv_lock, flags);
1279
1280         reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1281         ctrl0 = readl(reg);
1282
1283         if (value)
1284                 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1285         else
1286                 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1287
1288         chv_writel(ctrl0, reg);
1289
1290         raw_spin_unlock_irqrestore(&chv_lock, flags);
1291 }
1292
1293 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1294 {
1295         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1296         u32 ctrl0, direction;
1297         unsigned long flags;
1298
1299         raw_spin_lock_irqsave(&chv_lock, flags);
1300         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1301         raw_spin_unlock_irqrestore(&chv_lock, flags);
1302
1303         direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1304         direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1305
1306         return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1307 }
1308
1309 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1310 {
1311         return pinctrl_gpio_direction_input(chip->base + offset);
1312 }
1313
1314 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1315                                      int value)
1316 {
1317         chv_gpio_set(chip, offset, value);
1318         return pinctrl_gpio_direction_output(chip->base + offset);
1319 }
1320
1321 static const struct gpio_chip chv_gpio_chip = {
1322         .owner = THIS_MODULE,
1323         .request = gpiochip_generic_request,
1324         .free = gpiochip_generic_free,
1325         .get_direction = chv_gpio_get_direction,
1326         .direction_input = chv_gpio_direction_input,
1327         .direction_output = chv_gpio_direction_output,
1328         .get = chv_gpio_get,
1329         .set = chv_gpio_set,
1330 };
1331
1332 static void chv_gpio_irq_ack(struct irq_data *d)
1333 {
1334         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1335         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1336         int pin = irqd_to_hwirq(d);
1337         u32 intr_line;
1338
1339         raw_spin_lock(&chv_lock);
1340
1341         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1342         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1343         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1344         chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1345
1346         raw_spin_unlock(&chv_lock);
1347 }
1348
1349 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1350 {
1351         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1352         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1353         int pin = irqd_to_hwirq(d);
1354         u32 value, intr_line;
1355         unsigned long flags;
1356
1357         raw_spin_lock_irqsave(&chv_lock, flags);
1358
1359         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1360         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1361         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1362
1363         value = readl(pctrl->regs + CHV_INTMASK);
1364         if (mask)
1365                 value &= ~BIT(intr_line);
1366         else
1367                 value |= BIT(intr_line);
1368         chv_writel(value, pctrl->regs + CHV_INTMASK);
1369
1370         raw_spin_unlock_irqrestore(&chv_lock, flags);
1371 }
1372
1373 static void chv_gpio_irq_mask(struct irq_data *d)
1374 {
1375         chv_gpio_irq_mask_unmask(d, true);
1376 }
1377
1378 static void chv_gpio_irq_unmask(struct irq_data *d)
1379 {
1380         chv_gpio_irq_mask_unmask(d, false);
1381 }
1382
1383 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1384 {
1385         /*
1386          * Check if the interrupt has been requested with 0 as triggering
1387          * type. In that case it is assumed that the current values
1388          * programmed to the hardware are used (e.g BIOS configured
1389          * defaults).
1390          *
1391          * In that case ->irq_set_type() will never be called so we need to
1392          * read back the values from hardware now, set correct flow handler
1393          * and update mappings before the interrupt is being used.
1394          */
1395         if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1396                 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1397                 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1398                 unsigned pin = irqd_to_hwirq(d);
1399                 irq_flow_handler_t handler;
1400                 unsigned long flags;
1401                 u32 intsel, value;
1402
1403                 raw_spin_lock_irqsave(&chv_lock, flags);
1404                 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1405                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1406                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1407
1408                 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1409                 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1410                         handler = handle_level_irq;
1411                 else
1412                         handler = handle_edge_irq;
1413
1414                 if (!pctrl->intr_lines[intsel]) {
1415                         irq_set_handler_locked(d, handler);
1416                         pctrl->intr_lines[intsel] = pin;
1417                 }
1418                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1419         }
1420
1421         chv_gpio_irq_unmask(d);
1422         return 0;
1423 }
1424
1425 static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1426 {
1427         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1428         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1429         unsigned pin = irqd_to_hwirq(d);
1430         unsigned long flags;
1431         u32 value;
1432
1433         raw_spin_lock_irqsave(&chv_lock, flags);
1434
1435         /*
1436          * Pins which can be used as shared interrupt are configured in
1437          * BIOS. Driver trusts BIOS configurations and assigns different
1438          * handler according to the irq type.
1439          *
1440          * Driver needs to save the mapping between each pin and
1441          * its interrupt line.
1442          * 1. If the pin cfg is locked in BIOS:
1443          *      Trust BIOS has programmed IntWakeCfg bits correctly,
1444          *      driver just needs to save the mapping.
1445          * 2. If the pin cfg is not locked in BIOS:
1446          *      Driver programs the IntWakeCfg bits and save the mapping.
1447          */
1448         if (!chv_pad_locked(pctrl, pin)) {
1449                 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1450
1451                 value = readl(reg);
1452                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1453                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1454
1455                 if (type & IRQ_TYPE_EDGE_BOTH) {
1456                         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1457                                 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1458                         else if (type & IRQ_TYPE_EDGE_RISING)
1459                                 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1460                         else if (type & IRQ_TYPE_EDGE_FALLING)
1461                                 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1462                 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1463                         value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1464                         if (type & IRQ_TYPE_LEVEL_LOW)
1465                                 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1466                 }
1467
1468                 chv_writel(value, reg);
1469         }
1470
1471         value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1472         value &= CHV_PADCTRL0_INTSEL_MASK;
1473         value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1474
1475         pctrl->intr_lines[value] = pin;
1476
1477         if (type & IRQ_TYPE_EDGE_BOTH)
1478                 irq_set_handler_locked(d, handle_edge_irq);
1479         else if (type & IRQ_TYPE_LEVEL_MASK)
1480                 irq_set_handler_locked(d, handle_level_irq);
1481
1482         raw_spin_unlock_irqrestore(&chv_lock, flags);
1483
1484         return 0;
1485 }
1486
1487 static void chv_gpio_irq_handler(struct irq_desc *desc)
1488 {
1489         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1490         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1491         struct irq_chip *chip = irq_desc_get_chip(desc);
1492         unsigned long pending;
1493         unsigned long flags;
1494         u32 intr_line;
1495
1496         chained_irq_enter(chip, desc);
1497
1498         raw_spin_lock_irqsave(&chv_lock, flags);
1499         pending = readl(pctrl->regs + CHV_INTSTAT);
1500         raw_spin_unlock_irqrestore(&chv_lock, flags);
1501
1502         for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1503                 unsigned irq, offset;
1504
1505                 offset = pctrl->intr_lines[intr_line];
1506                 irq = irq_find_mapping(gc->irq.domain, offset);
1507                 generic_handle_irq(irq);
1508         }
1509
1510         chained_irq_exit(chip, desc);
1511 }
1512
1513 /*
1514  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1515  * tables. Since we leave GPIOs that are not capable of generating
1516  * interrupts out of the irqdomain the numbering will be different and
1517  * cause devices using the hardcoded IRQ numbers fail. In order not to
1518  * break such machines we will only mask pins from irqdomain if the machine
1519  * is not listed below.
1520  */
1521 static const struct dmi_system_id chv_no_valid_mask[] = {
1522         /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1523         {
1524                 .ident = "Intel_Strago based Chromebooks (All models)",
1525                 .matches = {
1526                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1527                         DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1528                 },
1529         },
1530         {
1531                 .ident = "HP Chromebook 11 G5 (Setzer)",
1532                 .matches = {
1533                         DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1534                         DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1535                 },
1536         },
1537         {
1538                 .ident = "Acer Chromebook R11 (Cyan)",
1539                 .matches = {
1540                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1541                         DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1542                 },
1543         },
1544         {
1545                 .ident = "Samsung Chromebook 3 (Celes)",
1546                 .matches = {
1547                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1548                         DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1549                 },
1550         },
1551         {}
1552 };
1553
1554 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1555 {
1556         const struct chv_gpio_pinrange *range;
1557         struct gpio_chip *chip = &pctrl->chip;
1558         bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1559         const struct chv_community *community = pctrl->community;
1560         int ret, i, irq_base;
1561
1562         *chip = chv_gpio_chip;
1563
1564         chip->ngpio = community->pins[community->npins - 1].number + 1;
1565         chip->label = dev_name(pctrl->dev);
1566         chip->parent = pctrl->dev;
1567         chip->base = -1;
1568         chip->irq.need_valid_mask = need_valid_mask;
1569
1570         ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1571         if (ret) {
1572                 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1573                 return ret;
1574         }
1575
1576         for (i = 0; i < community->ngpio_ranges; i++) {
1577                 range = &community->gpio_ranges[i];
1578                 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1579                                              range->base, range->base,
1580                                              range->npins);
1581                 if (ret) {
1582                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1583                         return ret;
1584                 }
1585         }
1586
1587         /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1588         for (i = 0; i < community->npins; i++) {
1589                 const struct pinctrl_pin_desc *desc;
1590                 u32 intsel;
1591
1592                 desc = &community->pins[i];
1593
1594                 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1595                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1596                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1597
1598                 if (need_valid_mask && intsel >= community->nirqs)
1599                         clear_bit(desc->number, chip->irq.valid_mask);
1600         }
1601
1602         /*
1603          * The same set of machines in chv_no_valid_mask[] have incorrectly
1604          * configured GPIOs that generate spurious interrupts so we use
1605          * this same list to apply another quirk for them.
1606          *
1607          * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1608          */
1609         if (!need_valid_mask) {
1610                 /*
1611                  * Mask all interrupts the community is able to generate
1612                  * but leave the ones that can only generate GPEs unmasked.
1613                  */
1614                 chv_writel(GENMASK(31, pctrl->community->nirqs),
1615                            pctrl->regs + CHV_INTMASK);
1616         }
1617
1618         /* Clear all interrupts */
1619         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1620
1621         if (!need_valid_mask) {
1622                 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1623                                                 community->npins, NUMA_NO_NODE);
1624                 if (irq_base < 0) {
1625                         dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1626                         return irq_base;
1627                 }
1628         }
1629
1630         pctrl->irqchip.name = "chv-gpio";
1631         pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1632         pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1633         pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1634         pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1635         pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1636         pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1637
1638         ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
1639                                    handle_bad_irq, IRQ_TYPE_NONE);
1640         if (ret) {
1641                 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1642                 return ret;
1643         }
1644
1645         if (!need_valid_mask) {
1646                 for (i = 0; i < community->ngpio_ranges; i++) {
1647                         range = &community->gpio_ranges[i];
1648
1649                         irq_domain_associate_many(chip->irq.domain, irq_base,
1650                                                   range->base, range->npins);
1651                         irq_base += range->npins;
1652                 }
1653         }
1654
1655         gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
1656                                      chv_gpio_irq_handler);
1657         return 0;
1658 }
1659
1660 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1661         acpi_physical_address address, u32 bits, u64 *value,
1662         void *handler_context, void *region_context)
1663 {
1664         struct chv_pinctrl *pctrl = region_context;
1665         unsigned long flags;
1666         acpi_status ret = AE_OK;
1667
1668         raw_spin_lock_irqsave(&chv_lock, flags);
1669
1670         if (function == ACPI_WRITE)
1671                 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1672         else if (function == ACPI_READ)
1673                 *value = readl(pctrl->regs + (u32)address);
1674         else
1675                 ret = AE_BAD_PARAMETER;
1676
1677         raw_spin_unlock_irqrestore(&chv_lock, flags);
1678
1679         return ret;
1680 }
1681
1682 static int chv_pinctrl_probe(struct platform_device *pdev)
1683 {
1684         struct chv_pinctrl *pctrl;
1685         struct acpi_device *adev;
1686         struct resource *res;
1687         acpi_status status;
1688         int ret, irq, i;
1689
1690         adev = ACPI_COMPANION(&pdev->dev);
1691         if (!adev)
1692                 return -ENODEV;
1693
1694         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1695         if (!pctrl)
1696                 return -ENOMEM;
1697
1698         for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1699                 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1700                         pctrl->community = chv_communities[i];
1701                         break;
1702                 }
1703         if (i == ARRAY_SIZE(chv_communities))
1704                 return -ENODEV;
1705
1706         pctrl->dev = &pdev->dev;
1707
1708 #ifdef CONFIG_PM_SLEEP
1709         pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1710                 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1711                 GFP_KERNEL);
1712         if (!pctrl->saved_pin_context)
1713                 return -ENOMEM;
1714 #endif
1715
1716         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1717         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1718         if (IS_ERR(pctrl->regs))
1719                 return PTR_ERR(pctrl->regs);
1720
1721         irq = platform_get_irq(pdev, 0);
1722         if (irq < 0) {
1723                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1724                 return irq;
1725         }
1726
1727         pctrl->pctldesc = chv_pinctrl_desc;
1728         pctrl->pctldesc.name = dev_name(&pdev->dev);
1729         pctrl->pctldesc.pins = pctrl->community->pins;
1730         pctrl->pctldesc.npins = pctrl->community->npins;
1731
1732         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1733                                                pctrl);
1734         if (IS_ERR(pctrl->pctldev)) {
1735                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1736                 return PTR_ERR(pctrl->pctldev);
1737         }
1738
1739         ret = chv_gpio_probe(pctrl, irq);
1740         if (ret)
1741                 return ret;
1742
1743         status = acpi_install_address_space_handler(adev->handle,
1744                                         pctrl->community->acpi_space_id,
1745                                         chv_pinctrl_mmio_access_handler,
1746                                         NULL, pctrl);
1747         if (ACPI_FAILURE(status))
1748                 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1749
1750         platform_set_drvdata(pdev, pctrl);
1751
1752         return 0;
1753 }
1754
1755 static int chv_pinctrl_remove(struct platform_device *pdev)
1756 {
1757         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1758
1759         acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1760                                           pctrl->community->acpi_space_id,
1761                                           chv_pinctrl_mmio_access_handler);
1762
1763         return 0;
1764 }
1765
1766 #ifdef CONFIG_PM_SLEEP
1767 static int chv_pinctrl_suspend_noirq(struct device *dev)
1768 {
1769         struct platform_device *pdev = to_platform_device(dev);
1770         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1771         unsigned long flags;
1772         int i;
1773
1774         raw_spin_lock_irqsave(&chv_lock, flags);
1775
1776         pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1777
1778         for (i = 0; i < pctrl->community->npins; i++) {
1779                 const struct pinctrl_pin_desc *desc;
1780                 struct chv_pin_context *ctx;
1781                 void __iomem *reg;
1782
1783                 desc = &pctrl->community->pins[i];
1784                 if (chv_pad_locked(pctrl, desc->number))
1785                         continue;
1786
1787                 ctx = &pctrl->saved_pin_context[i];
1788
1789                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1790                 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1791
1792                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1793                 ctx->padctrl1 = readl(reg);
1794         }
1795
1796         raw_spin_unlock_irqrestore(&chv_lock, flags);
1797
1798         return 0;
1799 }
1800
1801 static int chv_pinctrl_resume_noirq(struct device *dev)
1802 {
1803         struct platform_device *pdev = to_platform_device(dev);
1804         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1805         unsigned long flags;
1806         int i;
1807
1808         raw_spin_lock_irqsave(&chv_lock, flags);
1809
1810         /*
1811          * Mask all interrupts before restoring per-pin configuration
1812          * registers because we don't know in which state BIOS left them
1813          * upon exiting suspend.
1814          */
1815         chv_writel(0, pctrl->regs + CHV_INTMASK);
1816
1817         for (i = 0; i < pctrl->community->npins; i++) {
1818                 const struct pinctrl_pin_desc *desc;
1819                 const struct chv_pin_context *ctx;
1820                 void __iomem *reg;
1821                 u32 val;
1822
1823                 desc = &pctrl->community->pins[i];
1824                 if (chv_pad_locked(pctrl, desc->number))
1825                         continue;
1826
1827                 ctx = &pctrl->saved_pin_context[i];
1828
1829                 /* Only restore if our saved state differs from the current */
1830                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1831                 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1832                 if (ctx->padctrl0 != val) {
1833                         chv_writel(ctx->padctrl0, reg);
1834                         dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1835                                 desc->number, readl(reg));
1836                 }
1837
1838                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1839                 val = readl(reg);
1840                 if (ctx->padctrl1 != val) {
1841                         chv_writel(ctx->padctrl1, reg);
1842                         dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1843                                 desc->number, readl(reg));
1844                 }
1845         }
1846
1847         /*
1848          * Now that all pins are restored to known state, we can restore
1849          * the interrupt mask register as well.
1850          */
1851         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1852         chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1853
1854         raw_spin_unlock_irqrestore(&chv_lock, flags);
1855
1856         return 0;
1857 }
1858 #endif
1859
1860 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1861         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1862                                       chv_pinctrl_resume_noirq)
1863 };
1864
1865 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1866         { "INT33FF" },
1867         { }
1868 };
1869 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1870
1871 static struct platform_driver chv_pinctrl_driver = {
1872         .probe = chv_pinctrl_probe,
1873         .remove = chv_pinctrl_remove,
1874         .driver = {
1875                 .name = "cherryview-pinctrl",
1876                 .pm = &chv_pinctrl_pm_ops,
1877                 .acpi_match_table = chv_pinctrl_acpi_match,
1878         },
1879 };
1880
1881 static int __init chv_pinctrl_init(void)
1882 {
1883         return platform_driver_register(&chv_pinctrl_driver);
1884 }
1885 subsys_initcall(chv_pinctrl_init);
1886
1887 static void __exit chv_pinctrl_exit(void)
1888 {
1889         platform_driver_unregister(&chv_pinctrl_driver);
1890 }
1891 module_exit(chv_pinctrl_exit);
1892
1893 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1894 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1895 MODULE_LICENSE("GPL v2");