drivers/pinctrl/intel/pinctrl-cherryview.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cherryview/Braswell pinctrl driver
   4  *
   5  * Copyright (C) 2014, 2020 Intel Corporation
   6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This driver is based on the original Cherryview GPIO driver by
   9  *   Ning Li <ning.li@intel.com>
  10  *   Alan Cox <alan@linux.intel.com>
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/dmi.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/types.h>
  20
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25
  26 #include "pinctrl-intel.h"
  27
  28 #define CHV_INTSTAT                     0x300
  29 #define CHV_INTMASK                     0x380
  30
  31 #define FAMILY_PAD_REGS_OFF             0x4400
  32 #define FAMILY_PAD_REGS_SIZE            0x400
  33 #define MAX_FAMILY_PAD_GPIO_NO          15
  34 #define GPIO_REGS_SIZE                  8
  35
  36 #define CHV_PADCTRL0                    0x000
  37 #define CHV_PADCTRL0_INTSEL_SHIFT       28
  38 #define CHV_PADCTRL0_INTSEL_MASK        GENMASK(31, 28)
  39 #define CHV_PADCTRL0_TERM_UP            BIT(23)
  40 #define CHV_PADCTRL0_TERM_SHIFT         20
  41 #define CHV_PADCTRL0_TERM_MASK          GENMASK(22, 20)
  42 #define CHV_PADCTRL0_TERM_20K           1
  43 #define CHV_PADCTRL0_TERM_5K            2
  44 #define CHV_PADCTRL0_TERM_1K            4
  45 #define CHV_PADCTRL0_PMODE_SHIFT        16
  46 #define CHV_PADCTRL0_PMODE_MASK         GENMASK(19, 16)
  47 #define CHV_PADCTRL0_GPIOEN             BIT(15)
  48 #define CHV_PADCTRL0_GPIOCFG_SHIFT      8
  49 #define CHV_PADCTRL0_GPIOCFG_MASK       GENMASK(10, 8)
  50 #define CHV_PADCTRL0_GPIOCFG_GPIO       0
  51 #define CHV_PADCTRL0_GPIOCFG_GPO        1
  52 #define CHV_PADCTRL0_GPIOCFG_GPI        2
  53 #define CHV_PADCTRL0_GPIOCFG_HIZ        3
  54 #define CHV_PADCTRL0_GPIOTXSTATE        BIT(1)
  55 #define CHV_PADCTRL0_GPIORXSTATE        BIT(0)
  56
  57 #define CHV_PADCTRL1                    0x004
  58 #define CHV_PADCTRL1_CFGLOCK            BIT(31)
  59 #define CHV_PADCTRL1_INVRXTX_SHIFT      4
  60 #define CHV_PADCTRL1_INVRXTX_MASK       GENMASK(7, 4)
  61 #define CHV_PADCTRL1_INVRXTX_TXDATA     BIT(7)
  62 #define CHV_PADCTRL1_INVRXTX_RXDATA     BIT(6)
  63 #define CHV_PADCTRL1_INVRXTX_TXENABLE   BIT(5)
  64 #define CHV_PADCTRL1_ODEN               BIT(3)
  65 #define CHV_PADCTRL1_INTWAKECFG_MASK    GENMASK(2, 0)
  66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
  67 #define CHV_PADCTRL1_INTWAKECFG_RISING  2
  68 #define CHV_PADCTRL1_INTWAKECFG_BOTH    3
  69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL   4
  70
  71 struct intel_pad_context {
  72         u32 padctrl0;
  73         u32 padctrl1;
  74 };
  75
  76 /**
  77  * struct intel_community_context - community context for Cherryview
  78  * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
  79  * @saved_intmask: Interrupt mask saved for system sleep
  80  */
  81 struct intel_community_context {
  82         unsigned int intr_lines[16];
  83         u32 saved_intmask;
  84 };
  85
  86 #define PINMODE_INVERT_OE       BIT(15)
  87
  88 #define PINMODE(m, i)           ((m) | ((i) * PINMODE_INVERT_OE))
  89
  90 #define CHV_GPP(start, end)                     \
  91         {                                       \
  92                 .base = (start),                \
  93                 .size = (end) - (start) + 1,    \
  94         }
  95
  96 #define CHV_COMMUNITY(g, i, a)                  \
  97         {                                       \
  98                 .gpps = (g),                    \
  99                 .ngpps = ARRAY_SIZE(g),         \
 100                 .nirqs = (i),                   \
 101                 .acpi_space_id = (a),           \
 102         }
 103
 104 static const struct pinctrl_pin_desc southwest_pins[] = {
 105         PINCTRL_PIN(0, "FST_SPI_D2"),
 106         PINCTRL_PIN(1, "FST_SPI_D0"),
 107         PINCTRL_PIN(2, "FST_SPI_CLK"),
 108         PINCTRL_PIN(3, "FST_SPI_D3"),
 109         PINCTRL_PIN(4, "FST_SPI_CS1_B"),
 110         PINCTRL_PIN(5, "FST_SPI_D1"),
 111         PINCTRL_PIN(6, "FST_SPI_CS0_B"),
 112         PINCTRL_PIN(7, "FST_SPI_CS2_B"),
 113
 114         PINCTRL_PIN(15, "UART1_RTS_B"),
 115         PINCTRL_PIN(16, "UART1_RXD"),
 116         PINCTRL_PIN(17, "UART2_RXD"),
 117         PINCTRL_PIN(18, "UART1_CTS_B"),
 118         PINCTRL_PIN(19, "UART2_RTS_B"),
 119         PINCTRL_PIN(20, "UART1_TXD"),
 120         PINCTRL_PIN(21, "UART2_TXD"),
 121         PINCTRL_PIN(22, "UART2_CTS_B"),
 122
 123         PINCTRL_PIN(30, "MF_HDA_CLK"),
 124         PINCTRL_PIN(31, "MF_HDA_RSTB"),
 125         PINCTRL_PIN(32, "MF_HDA_SDIO"),
 126         PINCTRL_PIN(33, "MF_HDA_SDO"),
 127         PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
 128         PINCTRL_PIN(35, "MF_HDA_SYNC"),
 129         PINCTRL_PIN(36, "MF_HDA_SDI1"),
 130         PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
 131
 132         PINCTRL_PIN(45, "I2C5_SDA"),
 133         PINCTRL_PIN(46, "I2C4_SDA"),
 134         PINCTRL_PIN(47, "I2C6_SDA"),
 135         PINCTRL_PIN(48, "I2C5_SCL"),
 136         PINCTRL_PIN(49, "I2C_NFC_SDA"),
 137         PINCTRL_PIN(50, "I2C4_SCL"),
 138         PINCTRL_PIN(51, "I2C6_SCL"),
 139         PINCTRL_PIN(52, "I2C_NFC_SCL"),
 140
 141         PINCTRL_PIN(60, "I2C1_SDA"),
 142         PINCTRL_PIN(61, "I2C0_SDA"),
 143         PINCTRL_PIN(62, "I2C2_SDA"),
 144         PINCTRL_PIN(63, "I2C1_SCL"),
 145         PINCTRL_PIN(64, "I2C3_SDA"),
 146         PINCTRL_PIN(65, "I2C0_SCL"),
 147         PINCTRL_PIN(66, "I2C2_SCL"),
 148         PINCTRL_PIN(67, "I2C3_SCL"),
 149
 150         PINCTRL_PIN(75, "SATA_GP0"),
 151         PINCTRL_PIN(76, "SATA_GP1"),
 152         PINCTRL_PIN(77, "SATA_LEDN"),
 153         PINCTRL_PIN(78, "SATA_GP2"),
 154         PINCTRL_PIN(79, "MF_SMB_ALERTB"),
 155         PINCTRL_PIN(80, "SATA_GP3"),
 156         PINCTRL_PIN(81, "MF_SMB_CLK"),
 157         PINCTRL_PIN(82, "MF_SMB_DATA"),
 158
 159         PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
 160         PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
 161         PINCTRL_PIN(92, "GP_SSP_2_CLK"),
 162         PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
 163         PINCTRL_PIN(94, "GP_SSP_2_RXD"),
 164         PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
 165         PINCTRL_PIN(96, "GP_SSP_2_FS"),
 166         PINCTRL_PIN(97, "GP_SSP_2_TXD"),
 167 };
 168
 169 static const unsigned southwest_uart0_pins[] = { 16, 20 };
 170 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
 171 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
 172 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
 173 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
 174 static const unsigned southwest_lpe_pins[] = {
 175         30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
 176 };
 177 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
 178 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
 179 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
 180 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
 181 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
 182 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
 183 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
 184 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
 185
 186 /* Some of LPE I2S TXD pins need to have OE inversion set */
 187 static const unsigned int southwest_lpe_altfuncs[] = {
 188         PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
 189         PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
 190         PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
 191 };
 192
 193 /*
 194  * Two spi3 chipselects are available in different mode than the main spi3
 195  * functionality, which is using mode 2.
 196  */
 197 static const unsigned int southwest_spi3_altfuncs[] = {
 198         PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
 199         PINMODE(2, 0),                                              /* 82 */
 200 };
 201
 202 static const struct intel_pingroup southwest_groups[] = {
 203         PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
 204         PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
 205         PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
 206         PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
 207         PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
 208         PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
 209         PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
 210         PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
 211         PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
 212         PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
 213         PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
 214         PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
 215         PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
 216         PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
 217 };
 218
 219 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
 220 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
 221 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
 222 static const char * const southwest_hda_groups[] = { "hda_grp" };
 223 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
 224 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
 225 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
 226 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
 227 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
 228 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
 229 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
 230 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
 231 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
 232 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
 233
 234 /*
 235  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
 236  * enabled only as GPIOs.
 237  */
 238 static const struct intel_function southwest_functions[] = {
 239         FUNCTION("uart0", southwest_uart0_groups),
 240         FUNCTION("uart1", southwest_uart1_groups),
 241         FUNCTION("uart2", southwest_uart2_groups),
 242         FUNCTION("hda", southwest_hda_groups),
 243         FUNCTION("lpe", southwest_lpe_groups),
 244         FUNCTION("i2c0", southwest_i2c0_groups),
 245         FUNCTION("i2c1", southwest_i2c1_groups),
 246         FUNCTION("i2c2", southwest_i2c2_groups),
 247         FUNCTION("i2c3", southwest_i2c3_groups),
 248         FUNCTION("i2c4", southwest_i2c4_groups),
 249         FUNCTION("i2c5", southwest_i2c5_groups),
 250         FUNCTION("i2c6", southwest_i2c6_groups),
 251         FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
 252         FUNCTION("spi3", southwest_spi3_groups),
 253 };
 254
 255 static const struct intel_padgroup southwest_gpps[] = {
 256         CHV_GPP(0, 7),
 257         CHV_GPP(15, 22),
 258         CHV_GPP(30, 37),
 259         CHV_GPP(45, 52),
 260         CHV_GPP(60, 67),
 261         CHV_GPP(75, 82),
 262         CHV_GPP(90, 97),
 263 };
 264
 265 /*
 266  * Southwest community can generate GPIO interrupts only for the first 8
 267  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
 268  */
 269 static const struct intel_community southwest_communities[] = {
 270         CHV_COMMUNITY(southwest_gpps, 8, 0x91),
 271 };
 272
 273 static const struct intel_pinctrl_soc_data southwest_soc_data = {
 274         .uid = "1",
 275         .pins = southwest_pins,
 276         .npins = ARRAY_SIZE(southwest_pins),
 277         .groups = southwest_groups,
 278         .ngroups = ARRAY_SIZE(southwest_groups),
 279         .functions = southwest_functions,
 280         .nfunctions = ARRAY_SIZE(southwest_functions),
 281         .communities = southwest_communities,
 282         .ncommunities = ARRAY_SIZE(southwest_communities),
 283 };
 284
 285 static const struct pinctrl_pin_desc north_pins[] = {
 286         PINCTRL_PIN(0, "GPIO_DFX_0"),
 287         PINCTRL_PIN(1, "GPIO_DFX_3"),
 288         PINCTRL_PIN(2, "GPIO_DFX_7"),
 289         PINCTRL_PIN(3, "GPIO_DFX_1"),
 290         PINCTRL_PIN(4, "GPIO_DFX_5"),
 291         PINCTRL_PIN(5, "GPIO_DFX_4"),
 292         PINCTRL_PIN(6, "GPIO_DFX_8"),
 293         PINCTRL_PIN(7, "GPIO_DFX_2"),
 294         PINCTRL_PIN(8, "GPIO_DFX_6"),
 295
 296         PINCTRL_PIN(15, "GPIO_SUS0"),
 297         PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
 298         PINCTRL_PIN(17, "GPIO_SUS3"),
 299         PINCTRL_PIN(18, "GPIO_SUS7"),
 300         PINCTRL_PIN(19, "GPIO_SUS1"),
 301         PINCTRL_PIN(20, "GPIO_SUS5"),
 302         PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
 303         PINCTRL_PIN(22, "GPIO_SUS4"),
 304         PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
 305         PINCTRL_PIN(24, "GPIO_SUS2"),
 306         PINCTRL_PIN(25, "GPIO_SUS6"),
 307         PINCTRL_PIN(26, "CX_PREQ_B"),
 308         PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
 309
 310         PINCTRL_PIN(30, "TRST_B"),
 311         PINCTRL_PIN(31, "TCK"),
 312         PINCTRL_PIN(32, "PROCHOT_B"),
 313         PINCTRL_PIN(33, "SVIDO_DATA"),
 314         PINCTRL_PIN(34, "TMS"),
 315         PINCTRL_PIN(35, "CX_PRDY_B_2"),
 316         PINCTRL_PIN(36, "TDO_2"),
 317         PINCTRL_PIN(37, "CX_PRDY_B"),
 318         PINCTRL_PIN(38, "SVIDO_ALERT_B"),
 319         PINCTRL_PIN(39, "TDO"),
 320         PINCTRL_PIN(40, "SVIDO_CLK"),
 321         PINCTRL_PIN(41, "TDI"),
 322
 323         PINCTRL_PIN(45, "GP_CAMERASB_05"),
 324         PINCTRL_PIN(46, "GP_CAMERASB_02"),
 325         PINCTRL_PIN(47, "GP_CAMERASB_08"),
 326         PINCTRL_PIN(48, "GP_CAMERASB_00"),
 327         PINCTRL_PIN(49, "GP_CAMERASB_06"),
 328         PINCTRL_PIN(50, "GP_CAMERASB_10"),
 329         PINCTRL_PIN(51, "GP_CAMERASB_03"),
 330         PINCTRL_PIN(52, "GP_CAMERASB_09"),
 331         PINCTRL_PIN(53, "GP_CAMERASB_01"),
 332         PINCTRL_PIN(54, "GP_CAMERASB_07"),
 333         PINCTRL_PIN(55, "GP_CAMERASB_11"),
 334         PINCTRL_PIN(56, "GP_CAMERASB_04"),
 335
 336         PINCTRL_PIN(60, "PANEL0_BKLTEN"),
 337         PINCTRL_PIN(61, "HV_DDI0_HPD"),
 338         PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
 339         PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
 340         PINCTRL_PIN(64, "HV_DDI1_HPD"),
 341         PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
 342         PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
 343         PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
 344         PINCTRL_PIN(68, "HV_DDI2_HPD"),
 345         PINCTRL_PIN(69, "PANEL1_VDDEN"),
 346         PINCTRL_PIN(70, "PANEL1_BKLTEN"),
 347         PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
 348         PINCTRL_PIN(72, "PANEL0_VDDEN"),
 349 };
 350
 351 static const struct intel_padgroup north_gpps[] = {
 352         CHV_GPP(0, 8),
 353         CHV_GPP(15, 27),
 354         CHV_GPP(30, 41),
 355         CHV_GPP(45, 56),
 356         CHV_GPP(60, 72),
 357 };
 358
 359 /*
 360  * North community can generate GPIO interrupts only for the first 8
 361  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
 362  */
 363 static const struct intel_community north_communities[] = {
 364         CHV_COMMUNITY(north_gpps, 8, 0x92),
 365 };
 366
 367 static const struct intel_pinctrl_soc_data north_soc_data = {
 368         .uid = "2",
 369         .pins = north_pins,
 370         .npins = ARRAY_SIZE(north_pins),
 371         .communities = north_communities,
 372         .ncommunities = ARRAY_SIZE(north_communities),
 373 };
 374
 375 static const struct pinctrl_pin_desc east_pins[] = {
 376         PINCTRL_PIN(0, "PMU_SLP_S3_B"),
 377         PINCTRL_PIN(1, "PMU_BATLOW_B"),
 378         PINCTRL_PIN(2, "SUS_STAT_B"),
 379         PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
 380         PINCTRL_PIN(4, "PMU_AC_PRESENT"),
 381         PINCTRL_PIN(5, "PMU_PLTRST_B"),
 382         PINCTRL_PIN(6, "PMU_SUSCLK"),
 383         PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
 384         PINCTRL_PIN(8, "PMU_PWRBTN_B"),
 385         PINCTRL_PIN(9, "PMU_SLP_S4_B"),
 386         PINCTRL_PIN(10, "PMU_WAKE_B"),
 387         PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
 388
 389         PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
 390         PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
 391         PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
 392         PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
 393         PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
 394         PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
 395         PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
 396         PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
 397         PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
 398         PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
 399         PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
 400         PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
 401 };
 402
 403 static const struct intel_padgroup east_gpps[] = {
 404         CHV_GPP(0, 11),
 405         CHV_GPP(15, 26),
 406 };
 407
 408 static const struct intel_community east_communities[] = {
 409         CHV_COMMUNITY(east_gpps, 16, 0x93),
 410 };
 411
 412 static const struct intel_pinctrl_soc_data east_soc_data = {
 413         .uid = "3",
 414         .pins = east_pins,
 415         .npins = ARRAY_SIZE(east_pins),
 416         .communities = east_communities,
 417         .ncommunities = ARRAY_SIZE(east_communities),
 418 };
 419
 420 static const struct pinctrl_pin_desc southeast_pins[] = {
 421         PINCTRL_PIN(0, "MF_PLT_CLK0"),
 422         PINCTRL_PIN(1, "PWM1"),
 423         PINCTRL_PIN(2, "MF_PLT_CLK1"),
 424         PINCTRL_PIN(3, "MF_PLT_CLK4"),
 425         PINCTRL_PIN(4, "MF_PLT_CLK3"),
 426         PINCTRL_PIN(5, "PWM0"),
 427         PINCTRL_PIN(6, "MF_PLT_CLK5"),
 428         PINCTRL_PIN(7, "MF_PLT_CLK2"),
 429
 430         PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
 431         PINCTRL_PIN(16, "SDMMC1_CLK"),
 432         PINCTRL_PIN(17, "SDMMC1_D0"),
 433         PINCTRL_PIN(18, "SDMMC2_D1"),
 434         PINCTRL_PIN(19, "SDMMC2_CLK"),
 435         PINCTRL_PIN(20, "SDMMC1_D2"),
 436         PINCTRL_PIN(21, "SDMMC2_D2"),
 437         PINCTRL_PIN(22, "SDMMC2_CMD"),
 438         PINCTRL_PIN(23, "SDMMC1_CMD"),
 439         PINCTRL_PIN(24, "SDMMC1_D1"),
 440         PINCTRL_PIN(25, "SDMMC2_D0"),
 441         PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
 442
 443         PINCTRL_PIN(30, "SDMMC3_D1"),
 444         PINCTRL_PIN(31, "SDMMC3_CLK"),
 445         PINCTRL_PIN(32, "SDMMC3_D3"),
 446         PINCTRL_PIN(33, "SDMMC3_D2"),
 447         PINCTRL_PIN(34, "SDMMC3_CMD"),
 448         PINCTRL_PIN(35, "SDMMC3_D0"),
 449
 450         PINCTRL_PIN(45, "MF_LPC_AD2"),
 451         PINCTRL_PIN(46, "LPC_CLKRUNB"),
 452         PINCTRL_PIN(47, "MF_LPC_AD0"),
 453         PINCTRL_PIN(48, "LPC_FRAMEB"),
 454         PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
 455         PINCTRL_PIN(50, "MF_LPC_AD3"),
 456         PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
 457         PINCTRL_PIN(52, "MF_LPC_AD1"),
 458
 459         PINCTRL_PIN(60, "SPI1_MISO"),
 460         PINCTRL_PIN(61, "SPI1_CSO_B"),
 461         PINCTRL_PIN(62, "SPI1_CLK"),
 462         PINCTRL_PIN(63, "MMC1_D6"),
 463         PINCTRL_PIN(64, "SPI1_MOSI"),
 464         PINCTRL_PIN(65, "MMC1_D5"),
 465         PINCTRL_PIN(66, "SPI1_CS1_B"),
 466         PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
 467         PINCTRL_PIN(68, "MMC1_D7"),
 468         PINCTRL_PIN(69, "MMC1_RCLK"),
 469
 470         PINCTRL_PIN(75, "USB_OC1_B"),
 471         PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
 472         PINCTRL_PIN(77, "GPIO_ALERT"),
 473         PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
 474         PINCTRL_PIN(79, "ILB_SERIRQ"),
 475         PINCTRL_PIN(80, "USB_OC0_B"),
 476         PINCTRL_PIN(81, "SDMMC3_CD_B"),
 477         PINCTRL_PIN(82, "SPKR"),
 478         PINCTRL_PIN(83, "SUSPWRDNACK"),
 479         PINCTRL_PIN(84, "SPARE_PIN"),
 480         PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
 481 };
 482
 483 static const unsigned southeast_pwm0_pins[] = { 5 };
 484 static const unsigned southeast_pwm1_pins[] = { 1 };
 485 static const unsigned southeast_sdmmc1_pins[] = {
 486         16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
 487 };
 488 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
 489 static const unsigned southeast_sdmmc3_pins[] = {
 490         30, 31, 32, 33, 34, 35, 78, 81, 85,
 491 };
 492 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
 493 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
 494
 495 static const struct intel_pingroup southeast_groups[] = {
 496         PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
 497         PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
 498         PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
 499         PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
 500         PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
 501         PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
 502         PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
 503 };
 504
 505 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
 506 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
 507 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
 508 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
 509 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
 510 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
 511 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
 512
 513 static const struct intel_function southeast_functions[] = {
 514         FUNCTION("pwm0", southeast_pwm0_groups),
 515         FUNCTION("pwm1", southeast_pwm1_groups),
 516         FUNCTION("sdmmc1", southeast_sdmmc1_groups),
 517         FUNCTION("sdmmc2", southeast_sdmmc2_groups),
 518         FUNCTION("sdmmc3", southeast_sdmmc3_groups),
 519         FUNCTION("spi1", southeast_spi1_groups),
 520         FUNCTION("spi2", southeast_spi2_groups),
 521 };
 522
 523 static const struct intel_padgroup southeast_gpps[] = {
 524         CHV_GPP(0, 7),
 525         CHV_GPP(15, 26),
 526         CHV_GPP(30, 35),
 527         CHV_GPP(45, 52),
 528         CHV_GPP(60, 69),
 529         CHV_GPP(75, 85),
 530 };
 531
 532 static const struct intel_community southeast_communities[] = {
 533         CHV_COMMUNITY(southeast_gpps, 16, 0x94),
 534 };
 535
 536 static const struct intel_pinctrl_soc_data southeast_soc_data = {
 537         .uid = "4",
 538         .pins = southeast_pins,
 539         .npins = ARRAY_SIZE(southeast_pins),
 540         .groups = southeast_groups,
 541         .ngroups = ARRAY_SIZE(southeast_groups),
 542         .functions = southeast_functions,
 543         .nfunctions = ARRAY_SIZE(southeast_functions),
 544         .communities = southeast_communities,
 545         .ncommunities = ARRAY_SIZE(southeast_communities),
 546 };
 547
 548 static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
 549         &southwest_soc_data,
 550         &north_soc_data,
 551         &east_soc_data,
 552         &southeast_soc_data,
 553         NULL
 554 };
 555
 556 /*
 557  * Lock to serialize register accesses
 558  *
 559  * Due to a silicon issue, a shared lock must be used to prevent
 560  * concurrent accesses across the 4 GPIO controllers.
 561  *
 562  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
 563  * errata #CHT34, for further information.
 564  */
 565 static DEFINE_RAW_SPINLOCK(chv_lock);
 566
 567 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
 568 {
 569         const struct intel_community *community = &pctrl->communities[0];
 570
 571         return readl(community->regs + offset);
 572 }
 573
 574 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
 575 {
 576         const struct intel_community *community = &pctrl->communities[0];
 577         void __iomem *reg = community->regs + offset;
 578
 579         /* Write and simple read back to confirm the bus transferring done */
 580         writel(value, reg);
 581         readl(reg);
 582 }
 583
 584 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
 585                                 unsigned int reg)
 586 {
 587         const struct intel_community *community = &pctrl->communities[0];
 588         unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
 589         unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
 590
 591         offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
 592
 593         return community->pad_regs + offset + reg;
 594 }
 595
 596 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
 597 {
 598         return readl(chv_padreg(pctrl, pin, offset));
 599 }
 600
 601 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
 602 {
 603         void __iomem *reg = chv_padreg(pctrl, pin, offset);
 604
 605         /* Write and simple read back to confirm the bus transferring done */
 606         writel(value, reg);
 607         readl(reg);
 608 }
 609
 610 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
 611 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
 612 {
 613         return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
 614 }
 615
 616 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
 617 {
 618         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 619
 620         return pctrl->soc->ngroups;
 621 }
 622
 623 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
 624                                       unsigned int group)
 625 {
 626         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 627
 628         return pctrl->soc->groups[group].name;
 629 }
 630
 631 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 632                               const unsigned int **pins, unsigned int *npins)
 633 {
 634         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 635
 636         *pins = pctrl->soc->groups[group].pins;
 637         *npins = pctrl->soc->groups[group].npins;
 638         return 0;
 639 }
 640
 641 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 642                              unsigned int offset)
 643 {
 644         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 645         unsigned long flags;
 646         u32 ctrl0, ctrl1;
 647         bool locked;
 648
 649         raw_spin_lock_irqsave(&chv_lock, flags);
 650
 651         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
 652         ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
 653         locked = chv_pad_locked(pctrl, offset);
 654
 655         raw_spin_unlock_irqrestore(&chv_lock, flags);
 656
 657         if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
 658                 seq_puts(s, "GPIO ");
 659         } else {
 660                 u32 mode;
 661
 662                 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
 663                 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
 664
 665                 seq_printf(s, "mode %d ", mode);
 666         }
 667
 668         seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
 669
 670         if (locked)
 671                 seq_puts(s, " [LOCKED]");
 672 }
 673
 674 static const struct pinctrl_ops chv_pinctrl_ops = {
 675         .get_groups_count = chv_get_groups_count,
 676         .get_group_name = chv_get_group_name,
 677         .get_group_pins = chv_get_group_pins,
 678         .pin_dbg_show = chv_pin_dbg_show,
 679 };
 680
 681 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
 682 {
 683         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 684
 685         return pctrl->soc->nfunctions;
 686 }
 687
 688 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
 689                                          unsigned int function)
 690 {
 691         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 692
 693         return pctrl->soc->functions[function].name;
 694 }
 695
 696 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
 697                                    unsigned int function,
 698                                    const char * const **groups,
 699                                    unsigned int * const ngroups)
 700 {
 701         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 702
 703         *groups = pctrl->soc->functions[function].groups;
 704         *ngroups = pctrl->soc->functions[function].ngroups;
 705         return 0;
 706 }
 707
 708 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
 709                               unsigned int function, unsigned int group)
 710 {
 711         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 712         const struct intel_pingroup *grp;
 713         unsigned long flags;
 714         int i;
 715
 716         grp = &pctrl->soc->groups[group];
 717
 718         raw_spin_lock_irqsave(&chv_lock, flags);
 719
 720         /* Check first that the pad is not locked */
 721         for (i = 0; i < grp->npins; i++) {
 722                 if (chv_pad_locked(pctrl, grp->pins[i])) {
 723                         dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
 724                                  grp->pins[i]);
 725                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 726                         return -EBUSY;
 727                 }
 728         }
 729
 730         for (i = 0; i < grp->npins; i++) {
 731                 int pin = grp->pins[i];
 732                 unsigned int mode;
 733                 bool invert_oe;
 734                 u32 value;
 735
 736                 /* Check if there is pin-specific config */
 737                 if (grp->modes)
 738                         mode = grp->modes[i];
 739                 else
 740                         mode = grp->mode;
 741
 742                 /* Extract OE inversion */
 743                 invert_oe = mode & PINMODE_INVERT_OE;
 744                 mode &= ~PINMODE_INVERT_OE;
 745
 746                 value = chv_readl(pctrl, pin, CHV_PADCTRL0);
 747                 /* Disable GPIO mode */
 748                 value &= ~CHV_PADCTRL0_GPIOEN;
 749                 /* Set to desired mode */
 750                 value &= ~CHV_PADCTRL0_PMODE_MASK;
 751                 value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
 752                 chv_writel(pctrl, pin, CHV_PADCTRL0, value);
 753
 754                 /* Update for invert_oe */
 755                 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
 756                 if (invert_oe)
 757                         value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
 758                 chv_writel(pctrl, pin, CHV_PADCTRL1, value);
 759
 760                 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
 761                         pin, mode, invert_oe ? "" : "not ");
 762         }
 763
 764         raw_spin_unlock_irqrestore(&chv_lock, flags);
 765
 766         return 0;
 767 }
 768
 769 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
 770                                       unsigned int offset)
 771 {
 772         u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
 773         u32 value;
 774
 775         /*
 776          * One some devices the GPIO should output the inverted value from what
 777          * device-drivers / ACPI code expects (inverted external buffer?). The
 778          * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
 779          * preserve this flag if the pin is already setup as GPIO.
 780          */
 781         value = chv_readl(pctrl, offset, CHV_PADCTRL0);
 782         if (value & CHV_PADCTRL0_GPIOEN)
 783                 invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
 784
 785         value = chv_readl(pctrl, offset, CHV_PADCTRL1);
 786         value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
 787         value &= ~invrxtx_mask;
 788         chv_writel(pctrl, offset, CHV_PADCTRL1, value);
 789 }
 790
 791 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
 792                                    struct pinctrl_gpio_range *range,
 793                                    unsigned int offset)
 794 {
 795         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 796         unsigned long flags;
 797         u32 value;
 798
 799         raw_spin_lock_irqsave(&chv_lock, flags);
 800
 801         if (chv_pad_locked(pctrl, offset)) {
 802                 value = chv_readl(pctrl, offset, CHV_PADCTRL0);
 803                 if (!(value & CHV_PADCTRL0_GPIOEN)) {
 804                         /* Locked so cannot enable */
 805                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 806                         return -EBUSY;
 807                 }
 808         } else {
 809                 struct intel_community_context *cctx = &pctrl->context.communities[0];
 810                 int i;
 811
 812                 /* Reset the interrupt mapping */
 813                 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
 814                         if (cctx->intr_lines[i] == offset) {
 815                                 cctx->intr_lines[i] = 0;
 816                                 break;
 817                         }
 818                 }
 819
 820                 /* Disable interrupt generation */
 821                 chv_gpio_clear_triggering(pctrl, offset);
 822
 823                 value = chv_readl(pctrl, offset, CHV_PADCTRL0);
 824
 825                 /*
 826                  * If the pin is in HiZ mode (both TX and RX buffers are
 827                  * disabled) we turn it to be input now.
 828                  */
 829                 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
 830                      (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
 831                         value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
 832                         value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 833                 }
 834
 835                 /* Switch to a GPIO mode */
 836                 value |= CHV_PADCTRL0_GPIOEN;
 837                 chv_writel(pctrl, offset, CHV_PADCTRL0, value);
 838         }
 839
 840         raw_spin_unlock_irqrestore(&chv_lock, flags);
 841
 842         return 0;
 843 }
 844
 845 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
 846                                   struct pinctrl_gpio_range *range,
 847                                   unsigned int offset)
 848 {
 849         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 850         unsigned long flags;
 851
 852         raw_spin_lock_irqsave(&chv_lock, flags);
 853
 854         if (!chv_pad_locked(pctrl, offset))
 855                 chv_gpio_clear_triggering(pctrl, offset);
 856
 857         raw_spin_unlock_irqrestore(&chv_lock, flags);
 858 }
 859
 860 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
 861                                   struct pinctrl_gpio_range *range,
 862                                   unsigned int offset, bool input)
 863 {
 864         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 865         unsigned long flags;
 866         u32 ctrl0;
 867
 868         raw_spin_lock_irqsave(&chv_lock, flags);
 869
 870         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
 871         if (input)
 872                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 873         else
 874                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
 875         chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
 876
 877         raw_spin_unlock_irqrestore(&chv_lock, flags);
 878
 879         return 0;
 880 }
 881
 882 static const struct pinmux_ops chv_pinmux_ops = {
 883         .get_functions_count = chv_get_functions_count,
 884         .get_function_name = chv_get_function_name,
 885         .get_function_groups = chv_get_function_groups,
 886         .set_mux = chv_pinmux_set_mux,
 887         .gpio_request_enable = chv_gpio_request_enable,
 888         .gpio_disable_free = chv_gpio_disable_free,
 889         .gpio_set_direction = chv_gpio_set_direction,
 890 };
 891
 892 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 893                           unsigned long *config)
 894 {
 895         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 896         enum pin_config_param param = pinconf_to_config_param(*config);
 897         unsigned long flags;
 898         u32 ctrl0, ctrl1;
 899         u16 arg = 0;
 900         u32 term;
 901
 902         raw_spin_lock_irqsave(&chv_lock, flags);
 903         ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
 904         ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
 905         raw_spin_unlock_irqrestore(&chv_lock, flags);
 906
 907         term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
 908
 909         switch (param) {
 910         case PIN_CONFIG_BIAS_DISABLE:
 911                 if (term)
 912                         return -EINVAL;
 913                 break;
 914
 915         case PIN_CONFIG_BIAS_PULL_UP:
 916                 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
 917                         return -EINVAL;
 918
 919                 switch (term) {
 920                 case CHV_PADCTRL0_TERM_20K:
 921                         arg = 20000;
 922                         break;
 923                 case CHV_PADCTRL0_TERM_5K:
 924                         arg = 5000;
 925                         break;
 926                 case CHV_PADCTRL0_TERM_1K:
 927                         arg = 1000;
 928                         break;
 929                 }
 930
 931                 break;
 932
 933         case PIN_CONFIG_BIAS_PULL_DOWN:
 934                 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
 935                         return -EINVAL;
 936
 937                 switch (term) {
 938                 case CHV_PADCTRL0_TERM_20K:
 939                         arg = 20000;
 940                         break;
 941                 case CHV_PADCTRL0_TERM_5K:
 942                         arg = 5000;
 943                         break;
 944                 }
 945
 946                 break;
 947
 948         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
 949                 u32 cfg;
 950
 951                 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
 952                 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
 953                 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
 954                         return -EINVAL;
 955
 956                 break;
 957
 958         case PIN_CONFIG_DRIVE_PUSH_PULL:
 959                 if (ctrl1 & CHV_PADCTRL1_ODEN)
 960                         return -EINVAL;
 961                 break;
 962
 963         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 964                 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
 965                         return -EINVAL;
 966                 break;
 967         }
 968
 969         default:
 970                 return -ENOTSUPP;
 971         }
 972
 973         *config = pinconf_to_config_packed(param, arg);
 974         return 0;
 975 }
 976
 977 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 978                                enum pin_config_param param, u32 arg)
 979 {
 980         unsigned long flags;
 981         u32 ctrl0, pull;
 982
 983         raw_spin_lock_irqsave(&chv_lock, flags);
 984         ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
 985
 986         switch (param) {
 987         case PIN_CONFIG_BIAS_DISABLE:
 988                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
 989                 break;
 990
 991         case PIN_CONFIG_BIAS_PULL_UP:
 992                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
 993
 994                 switch (arg) {
 995                 case 1000:
 996                         /* For 1k there is only pull up */
 997                         pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
 998                         break;
 999                 case 5000:
1000                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1001                         break;
1002                 case 20000:
1003                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1004                         break;
1005                 default:
1006                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1007                         return -EINVAL;
1008                 }
1009
1010                 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1011                 break;
1012
1013         case PIN_CONFIG_BIAS_PULL_DOWN:
1014                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1015
1016                 switch (arg) {
1017                 case 5000:
1018                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1019                         break;
1020                 case 20000:
1021                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1022                         break;
1023                 default:
1024                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1025                         return -EINVAL;
1026                 }
1027
1028                 ctrl0 |= pull;
1029                 break;
1030
1031         default:
1032                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1033                 return -EINVAL;
1034         }
1035
1036         chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
1037         raw_spin_unlock_irqrestore(&chv_lock, flags);
1038
1039         return 0;
1040 }
1041
1042 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
1043                                bool enable)
1044 {
1045         unsigned long flags;
1046         u32 ctrl1;
1047
1048         raw_spin_lock_irqsave(&chv_lock, flags);
1049         ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
1050
1051         if (enable)
1052                 ctrl1 |= CHV_PADCTRL1_ODEN;
1053         else
1054                 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1055
1056         chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
1057         raw_spin_unlock_irqrestore(&chv_lock, flags);
1058
1059         return 0;
1060 }
1061
1062 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1063                           unsigned long *configs, unsigned int nconfigs)
1064 {
1065         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1066         enum pin_config_param param;
1067         int i, ret;
1068         u32 arg;
1069
1070         if (chv_pad_locked(pctrl, pin))
1071                 return -EBUSY;
1072
1073         for (i = 0; i < nconfigs; i++) {
1074                 param = pinconf_to_config_param(configs[i]);
1075                 arg = pinconf_to_config_argument(configs[i]);
1076
1077                 switch (param) {
1078                 case PIN_CONFIG_BIAS_DISABLE:
1079                 case PIN_CONFIG_BIAS_PULL_UP:
1080                 case PIN_CONFIG_BIAS_PULL_DOWN:
1081                         ret = chv_config_set_pull(pctrl, pin, param, arg);
1082                         if (ret)
1083                                 return ret;
1084                         break;
1085
1086                 case PIN_CONFIG_DRIVE_PUSH_PULL:
1087                         ret = chv_config_set_oden(pctrl, pin, false);
1088                         if (ret)
1089                                 return ret;
1090                         break;
1091
1092                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1093                         ret = chv_config_set_oden(pctrl, pin, true);
1094                         if (ret)
1095                                 return ret;
1096                         break;
1097
1098                 default:
1099                         return -ENOTSUPP;
1100                 }
1101
1102                 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1103                         param, arg);
1104         }
1105
1106         return 0;
1107 }
1108
1109 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1110                                 unsigned int group,
1111                                 unsigned long *config)
1112 {
1113         const unsigned int *pins;
1114         unsigned int npins;
1115         int ret;
1116
1117         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1118         if (ret)
1119                 return ret;
1120
1121         ret = chv_config_get(pctldev, pins[0], config);
1122         if (ret)
1123                 return ret;
1124
1125         return 0;
1126 }
1127
1128 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1129                                 unsigned int group, unsigned long *configs,
1130                                 unsigned int num_configs)
1131 {
1132         const unsigned int *pins;
1133         unsigned int npins;
1134         int i, ret;
1135
1136         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1137         if (ret)
1138                 return ret;
1139
1140         for (i = 0; i < npins; i++) {
1141                 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1142                 if (ret)
1143                         return ret;
1144         }
1145
1146         return 0;
1147 }
1148
1149 static const struct pinconf_ops chv_pinconf_ops = {
1150         .is_generic = true,
1151         .pin_config_set = chv_config_set,
1152         .pin_config_get = chv_config_get,
1153         .pin_config_group_get = chv_config_group_get,
1154         .pin_config_group_set = chv_config_group_set,
1155 };
1156
1157 static struct pinctrl_desc chv_pinctrl_desc = {
1158         .pctlops = &chv_pinctrl_ops,
1159         .pmxops = &chv_pinmux_ops,
1160         .confops = &chv_pinconf_ops,
1161         .owner = THIS_MODULE,
1162 };
1163
1164 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1165 {
1166         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1167         unsigned long flags;
1168         u32 ctrl0, cfg;
1169
1170         raw_spin_lock_irqsave(&chv_lock, flags);
1171         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1172         raw_spin_unlock_irqrestore(&chv_lock, flags);
1173
1174         cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1175         cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1176
1177         if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1178                 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1179         return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1180 }
1181
1182 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1183 {
1184         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1185         unsigned long flags;
1186         u32 ctrl0;
1187
1188         raw_spin_lock_irqsave(&chv_lock, flags);
1189
1190         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1191
1192         if (value)
1193                 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1194         else
1195                 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1196
1197         chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
1198
1199         raw_spin_unlock_irqrestore(&chv_lock, flags);
1200 }
1201
1202 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1203 {
1204         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1205         u32 ctrl0, direction;
1206         unsigned long flags;
1207
1208         raw_spin_lock_irqsave(&chv_lock, flags);
1209         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1210         raw_spin_unlock_irqrestore(&chv_lock, flags);
1211
1212         direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1213         direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1214
1215         if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1216                 return GPIO_LINE_DIRECTION_OUT;
1217
1218         return GPIO_LINE_DIRECTION_IN;
1219 }
1220
1221 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1222 {
1223         return pinctrl_gpio_direction_input(chip->base + offset);
1224 }
1225
1226 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1227                                      int value)
1228 {
1229         chv_gpio_set(chip, offset, value);
1230         return pinctrl_gpio_direction_output(chip->base + offset);
1231 }
1232
1233 static const struct gpio_chip chv_gpio_chip = {
1234         .owner = THIS_MODULE,
1235         .request = gpiochip_generic_request,
1236         .free = gpiochip_generic_free,
1237         .get_direction = chv_gpio_get_direction,
1238         .direction_input = chv_gpio_direction_input,
1239         .direction_output = chv_gpio_direction_output,
1240         .get = chv_gpio_get,
1241         .set = chv_gpio_set,
1242 };
1243
1244 static void chv_gpio_irq_ack(struct irq_data *d)
1245 {
1246         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1247         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1248         int pin = irqd_to_hwirq(d);
1249         u32 intr_line;
1250
1251         raw_spin_lock(&chv_lock);
1252
1253         intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
1254         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1255         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1256         chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
1257
1258         raw_spin_unlock(&chv_lock);
1259 }
1260
1261 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1262 {
1263         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1264         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1265         int pin = irqd_to_hwirq(d);
1266         u32 value, intr_line;
1267         unsigned long flags;
1268
1269         raw_spin_lock_irqsave(&chv_lock, flags);
1270
1271         intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
1272         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1273         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1274
1275         value = chv_pctrl_readl(pctrl, CHV_INTMASK);
1276         if (mask)
1277                 value &= ~BIT(intr_line);
1278         else
1279                 value |= BIT(intr_line);
1280         chv_pctrl_writel(pctrl, CHV_INTMASK, value);
1281
1282         raw_spin_unlock_irqrestore(&chv_lock, flags);
1283 }
1284
1285 static void chv_gpio_irq_mask(struct irq_data *d)
1286 {
1287         chv_gpio_irq_mask_unmask(d, true);
1288 }
1289
1290 static void chv_gpio_irq_unmask(struct irq_data *d)
1291 {
1292         chv_gpio_irq_mask_unmask(d, false);
1293 }
1294
1295 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1296 {
1297         /*
1298          * Check if the interrupt has been requested with 0 as triggering
1299          * type. In that case it is assumed that the current values
1300          * programmed to the hardware are used (e.g BIOS configured
1301          * defaults).
1302          *
1303          * In that case ->irq_set_type() will never be called so we need to
1304          * read back the values from hardware now, set correct flow handler
1305          * and update mappings before the interrupt is being used.
1306          */
1307         if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1308                 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1309                 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1310                 struct intel_community_context *cctx = &pctrl->context.communities[0];
1311                 unsigned int pin = irqd_to_hwirq(d);
1312                 irq_flow_handler_t handler;
1313                 unsigned long flags;
1314                 u32 intsel, value;
1315
1316                 raw_spin_lock_irqsave(&chv_lock, flags);
1317                 intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
1318                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1319                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1320
1321                 value = chv_readl(pctrl, pin, CHV_PADCTRL1);
1322                 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1323                         handler = handle_level_irq;
1324                 else
1325                         handler = handle_edge_irq;
1326
1327                 if (!cctx->intr_lines[intsel]) {
1328                         irq_set_handler_locked(d, handler);
1329                         cctx->intr_lines[intsel] = pin;
1330                 }
1331                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1332         }
1333
1334         chv_gpio_irq_unmask(d);
1335         return 0;
1336 }
1337
1338 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1339 {
1340         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1341         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1342         struct intel_community_context *cctx = &pctrl->context.communities[0];
1343         unsigned int pin = irqd_to_hwirq(d);
1344         unsigned long flags;
1345         u32 value;
1346
1347         raw_spin_lock_irqsave(&chv_lock, flags);
1348
1349         /*
1350          * Pins which can be used as shared interrupt are configured in
1351          * BIOS. Driver trusts BIOS configurations and assigns different
1352          * handler according to the irq type.
1353          *
1354          * Driver needs to save the mapping between each pin and
1355          * its interrupt line.
1356          * 1. If the pin cfg is locked in BIOS:
1357          *      Trust BIOS has programmed IntWakeCfg bits correctly,
1358          *      driver just needs to save the mapping.
1359          * 2. If the pin cfg is not locked in BIOS:
1360          *      Driver programs the IntWakeCfg bits and save the mapping.
1361          */
1362         if (!chv_pad_locked(pctrl, pin)) {
1363                 value = chv_readl(pctrl, pin, CHV_PADCTRL1);
1364                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1365                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1366
1367                 if (type & IRQ_TYPE_EDGE_BOTH) {
1368                         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1369                                 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1370                         else if (type & IRQ_TYPE_EDGE_RISING)
1371                                 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1372                         else if (type & IRQ_TYPE_EDGE_FALLING)
1373                                 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1374                 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1375                         value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1376                         if (type & IRQ_TYPE_LEVEL_LOW)
1377                                 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1378                 }
1379
1380                 chv_writel(pctrl, pin, CHV_PADCTRL1, value);
1381         }
1382
1383         value = chv_readl(pctrl, pin, CHV_PADCTRL0);
1384         value &= CHV_PADCTRL0_INTSEL_MASK;
1385         value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1386
1387         cctx->intr_lines[value] = pin;
1388
1389         if (type & IRQ_TYPE_EDGE_BOTH)
1390                 irq_set_handler_locked(d, handle_edge_irq);
1391         else if (type & IRQ_TYPE_LEVEL_MASK)
1392                 irq_set_handler_locked(d, handle_level_irq);
1393
1394         raw_spin_unlock_irqrestore(&chv_lock, flags);
1395
1396         return 0;
1397 }
1398
1399 static void chv_gpio_irq_handler(struct irq_desc *desc)
1400 {
1401         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1402         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1403         const struct intel_community *community = &pctrl->communities[0];
1404         struct intel_community_context *cctx = &pctrl->context.communities[0];
1405         struct irq_chip *chip = irq_desc_get_chip(desc);
1406         unsigned long pending;
1407         unsigned long flags;
1408         u32 intr_line;
1409
1410         chained_irq_enter(chip, desc);
1411
1412         raw_spin_lock_irqsave(&chv_lock, flags);
1413         pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
1414         raw_spin_unlock_irqrestore(&chv_lock, flags);
1415
1416         for_each_set_bit(intr_line, &pending, community->nirqs) {
1417                 unsigned int irq, offset;
1418
1419                 offset = cctx->intr_lines[intr_line];
1420                 irq = irq_find_mapping(gc->irq.domain, offset);
1421                 generic_handle_irq(irq);
1422         }
1423
1424         chained_irq_exit(chip, desc);
1425 }
1426
1427 /*
1428  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1429  * tables. Since we leave GPIOs that are not capable of generating
1430  * interrupts out of the irqdomain the numbering will be different and
1431  * cause devices using the hardcoded IRQ numbers fail. In order not to
1432  * break such machines we will only mask pins from irqdomain if the machine
1433  * is not listed below.
1434  */
1435 static const struct dmi_system_id chv_no_valid_mask[] = {
1436         /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1437         {
1438                 .ident = "Intel_Strago based Chromebooks (All models)",
1439                 .matches = {
1440                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1441                         DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1442                 },
1443         },
1444         {
1445                 .ident = "HP Chromebook 11 G5 (Setzer)",
1446                 .matches = {
1447                         DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1448                         DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1449                 },
1450         },
1451         {
1452                 .ident = "Acer Chromebook R11 (Cyan)",
1453                 .matches = {
1454                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1455                         DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1456                 },
1457         },
1458         {
1459                 .ident = "Samsung Chromebook 3 (Celes)",
1460                 .matches = {
1461                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1462                         DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1463                 },
1464         },
1465         {}
1466 };
1467
1468 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1469                                     unsigned long *valid_mask,
1470                                     unsigned int ngpios)
1471 {
1472         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1473         const struct intel_community *community = &pctrl->communities[0];
1474         int i;
1475
1476         /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1477         for (i = 0; i < pctrl->soc->npins; i++) {
1478                 const struct pinctrl_pin_desc *desc;
1479                 u32 intsel;
1480
1481                 desc = &pctrl->soc->pins[i];
1482
1483                 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1484                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1485                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1486
1487                 if (intsel >= community->nirqs)
1488                         clear_bit(desc->number, valid_mask);
1489         }
1490 }
1491
1492 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1493 {
1494         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1495         const struct intel_community *community = &pctrl->communities[0];
1496
1497         /*
1498          * The same set of machines in chv_no_valid_mask[] have incorrectly
1499          * configured GPIOs that generate spurious interrupts so we use
1500          * this same list to apply another quirk for them.
1501          *
1502          * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1503          */
1504         if (!pctrl->chip.irq.init_valid_mask) {
1505                 /*
1506                  * Mask all interrupts the community is able to generate
1507                  * but leave the ones that can only generate GPEs unmasked.
1508                  */
1509                 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
1510         }
1511
1512         /* Clear all interrupts */
1513         chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1514
1515         return 0;
1516 }
1517
1518 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1519 {
1520         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1521         const struct intel_community *community = &pctrl->communities[0];
1522         const struct intel_padgroup *gpp;
1523         int ret, i;
1524
1525         for (i = 0; i < community->ngpps; i++) {
1526                 gpp = &community->gpps[i];
1527                 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1528                                              gpp->base, gpp->base,
1529                                              gpp->size);
1530                 if (ret) {
1531                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1532                         return ret;
1533                 }
1534         }
1535
1536         return 0;
1537 }
1538
1539 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1540 {
1541         const struct intel_community *community = &pctrl->communities[0];
1542         const struct intel_padgroup *gpp;
1543         struct gpio_chip *chip = &pctrl->chip;
1544         bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1545         int ret, i, irq_base;
1546
1547         *chip = chv_gpio_chip;
1548
1549         chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
1550         chip->label = dev_name(pctrl->dev);
1551         chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1552         chip->parent = pctrl->dev;
1553         chip->base = -1;
1554
1555         pctrl->irq = irq;
1556         pctrl->irqchip.name = "chv-gpio";
1557         pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1558         pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1559         pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1560         pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1561         pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1562         pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1563
1564         chip->irq.chip = &pctrl->irqchip;
1565         chip->irq.init_hw = chv_gpio_irq_init_hw;
1566         chip->irq.parent_handler = chv_gpio_irq_handler;
1567         chip->irq.num_parents = 1;
1568         chip->irq.parents = &pctrl->irq;
1569         chip->irq.default_type = IRQ_TYPE_NONE;
1570         chip->irq.handler = handle_bad_irq;
1571         if (need_valid_mask) {
1572                 chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1573         } else {
1574                 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1575                                                 pctrl->soc->npins, NUMA_NO_NODE);
1576                 if (irq_base < 0) {
1577                         dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1578                         return irq_base;
1579                 }
1580         }
1581
1582         ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1583         if (ret) {
1584                 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1585                 return ret;
1586         }
1587
1588         if (!need_valid_mask) {
1589                 for (i = 0; i < community->ngpps; i++) {
1590                         gpp = &community->gpps[i];
1591
1592                         irq_domain_associate_many(chip->irq.domain, irq_base,
1593                                                   gpp->base, gpp->size);
1594                         irq_base += gpp->size;
1595                 }
1596         }
1597
1598         return 0;
1599 }
1600
1601 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1602         acpi_physical_address address, u32 bits, u64 *value,
1603         void *handler_context, void *region_context)
1604 {
1605         struct intel_pinctrl *pctrl = region_context;
1606         unsigned long flags;
1607         acpi_status ret = AE_OK;
1608
1609         raw_spin_lock_irqsave(&chv_lock, flags);
1610
1611         if (function == ACPI_WRITE)
1612                 chv_pctrl_writel(pctrl, address, *value);
1613         else if (function == ACPI_READ)
1614                 *value = chv_pctrl_readl(pctrl, address);
1615         else
1616                 ret = AE_BAD_PARAMETER;
1617
1618         raw_spin_unlock_irqrestore(&chv_lock, flags);
1619
1620         return ret;
1621 }
1622
1623 static int chv_pinctrl_probe(struct platform_device *pdev)
1624 {
1625         const struct intel_pinctrl_soc_data *soc_data;
1626         struct intel_community *community;
1627         struct device *dev = &pdev->dev;
1628         struct intel_pinctrl *pctrl;
1629         acpi_status status;
1630         int ret, irq;
1631
1632         soc_data = intel_pinctrl_get_soc_data(pdev);
1633         if (IS_ERR(soc_data))
1634                 return PTR_ERR(soc_data);
1635
1636         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1637         if (!pctrl)
1638                 return -ENOMEM;
1639
1640         pctrl->dev = dev;
1641         pctrl->soc = soc_data;
1642
1643         pctrl->ncommunities = pctrl->soc->ncommunities;
1644         pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
1645                                           pctrl->ncommunities * sizeof(*pctrl->communities),
1646                                           GFP_KERNEL);
1647         if (!pctrl->communities)
1648                 return -ENOMEM;
1649
1650         community = &pctrl->communities[0];
1651         community->regs = devm_platform_ioremap_resource(pdev, 0);
1652         if (IS_ERR(community->regs))
1653                 return PTR_ERR(community->regs);
1654
1655         community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
1656
1657 #ifdef CONFIG_PM_SLEEP
1658         pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
1659                                            sizeof(*pctrl->context.pads),
1660                                            GFP_KERNEL);
1661         if (!pctrl->context.pads)
1662                 return -ENOMEM;
1663 #endif
1664
1665         pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
1666                                                   sizeof(*pctrl->context.communities),
1667                                                   GFP_KERNEL);
1668         if (!pctrl->context.communities)
1669                 return -ENOMEM;
1670
1671         irq = platform_get_irq(pdev, 0);
1672         if (irq < 0)
1673                 return irq;
1674
1675         pctrl->pctldesc = chv_pinctrl_desc;
1676         pctrl->pctldesc.name = dev_name(dev);
1677         pctrl->pctldesc.pins = pctrl->soc->pins;
1678         pctrl->pctldesc.npins = pctrl->soc->npins;
1679
1680         pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1681         if (IS_ERR(pctrl->pctldev)) {
1682                 dev_err(dev, "failed to register pinctrl driver\n");
1683                 return PTR_ERR(pctrl->pctldev);
1684         }
1685
1686         ret = chv_gpio_probe(pctrl, irq);
1687         if (ret)
1688                 return ret;
1689
1690         status = acpi_install_address_space_handler(ACPI_HANDLE(dev),
1691                                         community->acpi_space_id,
1692                                         chv_pinctrl_mmio_access_handler,
1693                                         NULL, pctrl);
1694         if (ACPI_FAILURE(status))
1695                 dev_err(dev, "failed to install ACPI addr space handler\n");
1696
1697         platform_set_drvdata(pdev, pctrl);
1698
1699         return 0;
1700 }
1701
1702 static int chv_pinctrl_remove(struct platform_device *pdev)
1703 {
1704         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1705         const struct intel_community *community = &pctrl->communities[0];
1706
1707         acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),
1708                                           community->acpi_space_id,
1709                                           chv_pinctrl_mmio_access_handler);
1710
1711         return 0;
1712 }
1713
1714 #ifdef CONFIG_PM_SLEEP
1715 static int chv_pinctrl_suspend_noirq(struct device *dev)
1716 {
1717         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1718         struct intel_community_context *cctx = &pctrl->context.communities[0];
1719         unsigned long flags;
1720         int i;
1721
1722         raw_spin_lock_irqsave(&chv_lock, flags);
1723
1724         cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
1725
1726         for (i = 0; i < pctrl->soc->npins; i++) {
1727                 const struct pinctrl_pin_desc *desc;
1728                 struct intel_pad_context *ctx = &pctrl->context.pads[i];
1729
1730                 desc = &pctrl->soc->pins[i];
1731                 if (chv_pad_locked(pctrl, desc->number))
1732                         continue;
1733
1734                 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1735                 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
1736
1737                 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1738         }
1739
1740         raw_spin_unlock_irqrestore(&chv_lock, flags);
1741
1742         return 0;
1743 }
1744
1745 static int chv_pinctrl_resume_noirq(struct device *dev)
1746 {
1747         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1748         struct intel_community_context *cctx = &pctrl->context.communities[0];
1749         unsigned long flags;
1750         int i;
1751
1752         raw_spin_lock_irqsave(&chv_lock, flags);
1753
1754         /*
1755          * Mask all interrupts before restoring per-pin configuration
1756          * registers because we don't know in which state BIOS left them
1757          * upon exiting suspend.
1758          */
1759         chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
1760
1761         for (i = 0; i < pctrl->soc->npins; i++) {
1762                 const struct pinctrl_pin_desc *desc;
1763                 struct intel_pad_context *ctx = &pctrl->context.pads[i];
1764                 u32 val;
1765
1766                 desc = &pctrl->soc->pins[i];
1767                 if (chv_pad_locked(pctrl, desc->number))
1768                         continue;
1769
1770                 /* Only restore if our saved state differs from the current */
1771                 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1772                 val &= ~CHV_PADCTRL0_GPIORXSTATE;
1773                 if (ctx->padctrl0 != val) {
1774                         chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
1775                         dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1776                                 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
1777                 }
1778
1779                 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1780                 if (ctx->padctrl1 != val) {
1781                         chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
1782                         dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1783                                 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
1784                 }
1785         }
1786
1787         /*
1788          * Now that all pins are restored to known state, we can restore
1789          * the interrupt mask register as well.
1790          */
1791         chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1792         chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
1793
1794         raw_spin_unlock_irqrestore(&chv_lock, flags);
1795
1796         return 0;
1797 }
1798 #endif
1799
1800 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1801         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1802                                       chv_pinctrl_resume_noirq)
1803 };
1804
1805 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1806         { "INT33FF", (kernel_ulong_t)chv_soc_data },
1807         { }
1808 };
1809 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1810
1811 static struct platform_driver chv_pinctrl_driver = {
1812         .probe = chv_pinctrl_probe,
1813         .remove = chv_pinctrl_remove,
1814         .driver = {
1815                 .name = "cherryview-pinctrl",
1816                 .pm = &chv_pinctrl_pm_ops,
1817                 .acpi_match_table = chv_pinctrl_acpi_match,
1818         },
1819 };
1820
1821 static int __init chv_pinctrl_init(void)
1822 {
1823         return platform_driver_register(&chv_pinctrl_driver);
1824 }
1825 subsys_initcall(chv_pinctrl_init);
1826
1827 static void __exit chv_pinctrl_exit(void)
1828 {
1829         platform_driver_unregister(&chv_pinctrl_driver);
1830 }
1831 module_exit(chv_pinctrl_exit);
1832
1833 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1834 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1835 MODULE_LICENSE("GPL v2");