1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl GPIO driver for Intel Baytrail
5 * Copyright (c) 2012-2013, Intel Corporation
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/bitops.h>
13 #include <linux/interrupt.h>
14 #include <linux/gpio.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/acpi.h>
17 #include <linux/platform_device.h>
18 #include <linux/seq_file.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
26 /* memory mapped register offsets */
27 #define BYT_CONF0_REG 0x000
28 #define BYT_CONF1_REG 0x004
29 #define BYT_VAL_REG 0x008
30 #define BYT_DFT_REG 0x00c
31 #define BYT_INT_STAT_REG 0x800
32 #define BYT_DEBOUNCE_REG 0x9d0
34 /* BYT_CONF0_REG register bits */
35 #define BYT_IODEN BIT(31)
36 #define BYT_DIRECT_IRQ_EN BIT(27)
37 #define BYT_TRIG_NEG BIT(26)
38 #define BYT_TRIG_POS BIT(25)
39 #define BYT_TRIG_LVL BIT(24)
40 #define BYT_DEBOUNCE_EN BIT(20)
41 #define BYT_GLITCH_FILTER_EN BIT(19)
42 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
43 #define BYT_GLITCH_F_FAST_CLK BIT(16)
44 #define BYT_PULL_STR_SHIFT 9
45 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
46 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
47 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
48 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
49 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
50 #define BYT_PULL_ASSIGN_SHIFT 7
51 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
52 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
53 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
54 #define BYT_PIN_MUX 0x07
56 /* BYT_VAL_REG register bits */
57 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
58 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
59 #define BYT_LEVEL BIT(0)
61 #define BYT_DIR_MASK (BIT(1) | BIT(2))
62 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
64 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
66 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
68 /* BYT_DEBOUNCE_REG bits */
69 #define BYT_DEBOUNCE_PULSE_MASK 0x7
70 #define BYT_DEBOUNCE_PULSE_375US 1
71 #define BYT_DEBOUNCE_PULSE_750US 2
72 #define BYT_DEBOUNCE_PULSE_1500US 3
73 #define BYT_DEBOUNCE_PULSE_3MS 4
74 #define BYT_DEBOUNCE_PULSE_6MS 5
75 #define BYT_DEBOUNCE_PULSE_12MS 6
76 #define BYT_DEBOUNCE_PULSE_24MS 7
78 #define BYT_NGPIO_SCORE 102
79 #define BYT_NGPIO_NCORE 28
80 #define BYT_NGPIO_SUS 44
82 #define BYT_SCORE_ACPI_UID "1"
83 #define BYT_NCORE_ACPI_UID "2"
84 #define BYT_SUS_ACPI_UID "3"
87 * This is the function value most pins have for GPIO muxing. If the value
88 * differs from the default one, it must be explicitly mentioned. Otherwise, the
89 * pin control implementation will set the muxing value to default GPIO if it
90 * does not find a match for the requested function.
92 #define BYT_DEFAULT_GPIO_MUX 0
94 struct byt_gpio_pin_context {
99 struct byt_simple_func_mux {
104 struct byt_mixed_func_mux {
106 const unsigned short *func_values;
109 struct byt_pingroup {
111 const unsigned int *pins;
113 unsigned short has_simple_funcs;
115 const struct byt_simple_func_mux *simple_funcs;
116 const struct byt_mixed_func_mux *mixed_funcs;
121 struct byt_function {
123 const char * const *groups;
127 struct byt_community {
128 unsigned int pin_base;
130 const unsigned int *pad_map;
131 void __iomem *reg_base;
134 #define SIMPLE_FUNC(n, f) \
139 #define MIXED_FUNC(n, f) \
142 .func_values = (f), \
145 #define PIN_GROUP_SIMPLE(n, p, f) \
149 .npins = ARRAY_SIZE((p)), \
150 .has_simple_funcs = 1, \
152 .simple_funcs = (f), \
154 .nfuncs = ARRAY_SIZE((f)), \
156 #define PIN_GROUP_MIXED(n, p, f) \
160 .npins = ARRAY_SIZE((p)), \
161 .has_simple_funcs = 0, \
163 .mixed_funcs = (f), \
165 .nfuncs = ARRAY_SIZE((f)), \
168 #define FUNCTION(n, g) \
172 .ngroups = ARRAY_SIZE((g)), \
175 #define COMMUNITY(p, n, map) \
182 struct byt_pinctrl_soc_data {
184 const struct pinctrl_pin_desc *pins;
186 const struct byt_pingroup *groups;
188 const struct byt_function *functions;
190 const struct byt_community *communities;
195 struct gpio_chip chip;
196 struct platform_device *pdev;
197 struct pinctrl_dev *pctl_dev;
198 struct pinctrl_desc pctl_desc;
199 const struct byt_pinctrl_soc_data *soc_data;
200 struct byt_community *communities_copy;
201 struct byt_gpio_pin_context *saved_context;
204 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
205 static const struct pinctrl_pin_desc byt_score_pins[] = {
206 PINCTRL_PIN(0, "SATA_GP0"),
207 PINCTRL_PIN(1, "SATA_GP1"),
208 PINCTRL_PIN(2, "SATA_LED#"),
209 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
210 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
211 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
212 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
213 PINCTRL_PIN(7, "SD3_WP"),
214 PINCTRL_PIN(8, "HDA_RST"),
215 PINCTRL_PIN(9, "HDA_SYNC"),
216 PINCTRL_PIN(10, "HDA_CLK"),
217 PINCTRL_PIN(11, "HDA_SDO"),
218 PINCTRL_PIN(12, "HDA_SDI0"),
219 PINCTRL_PIN(13, "HDA_SDI1"),
220 PINCTRL_PIN(14, "GPIO_S0_SC14"),
221 PINCTRL_PIN(15, "GPIO_S0_SC15"),
222 PINCTRL_PIN(16, "MMC1_CLK"),
223 PINCTRL_PIN(17, "MMC1_D0"),
224 PINCTRL_PIN(18, "MMC1_D1"),
225 PINCTRL_PIN(19, "MMC1_D2"),
226 PINCTRL_PIN(20, "MMC1_D3"),
227 PINCTRL_PIN(21, "MMC1_D4"),
228 PINCTRL_PIN(22, "MMC1_D5"),
229 PINCTRL_PIN(23, "MMC1_D6"),
230 PINCTRL_PIN(24, "MMC1_D7"),
231 PINCTRL_PIN(25, "MMC1_CMD"),
232 PINCTRL_PIN(26, "MMC1_RST"),
233 PINCTRL_PIN(27, "SD2_CLK"),
234 PINCTRL_PIN(28, "SD2_D0"),
235 PINCTRL_PIN(29, "SD2_D1"),
236 PINCTRL_PIN(30, "SD2_D2"),
237 PINCTRL_PIN(31, "SD2_D3_CD"),
238 PINCTRL_PIN(32, "SD2_CMD"),
239 PINCTRL_PIN(33, "SD3_CLK"),
240 PINCTRL_PIN(34, "SD3_D0"),
241 PINCTRL_PIN(35, "SD3_D1"),
242 PINCTRL_PIN(36, "SD3_D2"),
243 PINCTRL_PIN(37, "SD3_D3"),
244 PINCTRL_PIN(38, "SD3_CD"),
245 PINCTRL_PIN(39, "SD3_CMD"),
246 PINCTRL_PIN(40, "SD3_1P8EN"),
247 PINCTRL_PIN(41, "SD3_PWREN#"),
248 PINCTRL_PIN(42, "ILB_LPC_AD0"),
249 PINCTRL_PIN(43, "ILB_LPC_AD1"),
250 PINCTRL_PIN(44, "ILB_LPC_AD2"),
251 PINCTRL_PIN(45, "ILB_LPC_AD3"),
252 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
253 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
254 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
255 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
256 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
257 PINCTRL_PIN(51, "PCU_SMB_DATA"),
258 PINCTRL_PIN(52, "PCU_SMB_CLK"),
259 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
260 PINCTRL_PIN(54, "ILB_8254_SPKR"),
261 PINCTRL_PIN(55, "GPIO_S0_SC55"),
262 PINCTRL_PIN(56, "GPIO_S0_SC56"),
263 PINCTRL_PIN(57, "GPIO_S0_SC57"),
264 PINCTRL_PIN(58, "GPIO_S0_SC58"),
265 PINCTRL_PIN(59, "GPIO_S0_SC59"),
266 PINCTRL_PIN(60, "GPIO_S0_SC60"),
267 PINCTRL_PIN(61, "GPIO_S0_SC61"),
268 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
269 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
270 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
271 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
272 PINCTRL_PIN(66, "SIO_SPI_CS"),
273 PINCTRL_PIN(67, "SIO_SPI_MISO"),
274 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
275 PINCTRL_PIN(69, "SIO_SPI_CLK"),
276 PINCTRL_PIN(70, "SIO_UART1_RXD"),
277 PINCTRL_PIN(71, "SIO_UART1_TXD"),
278 PINCTRL_PIN(72, "SIO_UART1_RTS"),
279 PINCTRL_PIN(73, "SIO_UART1_CTS"),
280 PINCTRL_PIN(74, "SIO_UART2_RXD"),
281 PINCTRL_PIN(75, "SIO_UART2_TXD"),
282 PINCTRL_PIN(76, "SIO_UART2_RTS"),
283 PINCTRL_PIN(77, "SIO_UART2_CTS"),
284 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
285 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
286 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
287 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
288 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
289 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
290 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
291 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
292 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
293 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
294 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
295 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
296 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
297 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
298 PINCTRL_PIN(92, "GPIO_S0_SC92"),
299 PINCTRL_PIN(93, "GPIO_S0_SC93"),
300 PINCTRL_PIN(94, "SIO_PWM0"),
301 PINCTRL_PIN(95, "SIO_PWM1"),
302 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
303 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
304 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
305 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
306 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
307 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
310 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
311 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
312 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
313 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
314 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
315 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
316 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
317 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
318 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
319 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
320 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
325 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
326 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
327 static const struct byt_simple_func_mux byt_score_uart_mux[] = {
328 SIMPLE_FUNC("uart", 1),
331 static const unsigned int byt_score_pwm0_pins[] = { 94 };
332 static const unsigned int byt_score_pwm1_pins[] = { 95 };
333 static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
334 SIMPLE_FUNC("pwm", 1),
337 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
338 static const struct byt_simple_func_mux byt_score_spi_mux[] = {
339 SIMPLE_FUNC("spi", 1),
342 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
343 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
344 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
345 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
346 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
347 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
348 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
349 static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
350 SIMPLE_FUNC("i2c", 1),
353 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
354 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
355 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
356 static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
357 SIMPLE_FUNC("ssp", 1),
360 static const unsigned int byt_score_sdcard_pins[] = {
361 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
363 static const unsigned short byt_score_sdcard_mux_values[] = {
364 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
366 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
367 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
370 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
371 static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
372 SIMPLE_FUNC("sdio", 1),
375 static const unsigned int byt_score_emmc_pins[] = {
376 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
378 static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
379 SIMPLE_FUNC("emmc", 1),
382 static const unsigned int byt_score_ilb_lpc_pins[] = {
383 42, 43, 44, 45, 46, 47, 48, 49, 50,
385 static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
386 SIMPLE_FUNC("lpc", 1),
389 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
390 static const struct byt_simple_func_mux byt_score_sata_mux[] = {
391 SIMPLE_FUNC("sata", 1),
394 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
395 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
396 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
397 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
398 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
399 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
400 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
401 SIMPLE_FUNC("plt_clk", 1),
404 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
405 static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
406 SIMPLE_FUNC("smbus", 1),
409 static const struct byt_pingroup byt_score_groups[] = {
410 PIN_GROUP_SIMPLE("uart1_grp",
411 byt_score_uart1_pins, byt_score_uart_mux),
412 PIN_GROUP_SIMPLE("uart2_grp",
413 byt_score_uart2_pins, byt_score_uart_mux),
414 PIN_GROUP_SIMPLE("pwm0_grp",
415 byt_score_pwm0_pins, byt_score_pwm_mux),
416 PIN_GROUP_SIMPLE("pwm1_grp",
417 byt_score_pwm1_pins, byt_score_pwm_mux),
418 PIN_GROUP_SIMPLE("ssp2_grp",
419 byt_score_ssp2_pins, byt_score_pwm_mux),
420 PIN_GROUP_SIMPLE("sio_spi_grp",
421 byt_score_sio_spi_pins, byt_score_spi_mux),
422 PIN_GROUP_SIMPLE("i2c5_grp",
423 byt_score_i2c5_pins, byt_score_i2c_mux),
424 PIN_GROUP_SIMPLE("i2c6_grp",
425 byt_score_i2c6_pins, byt_score_i2c_mux),
426 PIN_GROUP_SIMPLE("i2c4_grp",
427 byt_score_i2c4_pins, byt_score_i2c_mux),
428 PIN_GROUP_SIMPLE("i2c3_grp",
429 byt_score_i2c3_pins, byt_score_i2c_mux),
430 PIN_GROUP_SIMPLE("i2c2_grp",
431 byt_score_i2c2_pins, byt_score_i2c_mux),
432 PIN_GROUP_SIMPLE("i2c1_grp",
433 byt_score_i2c1_pins, byt_score_i2c_mux),
434 PIN_GROUP_SIMPLE("i2c0_grp",
435 byt_score_i2c0_pins, byt_score_i2c_mux),
436 PIN_GROUP_SIMPLE("ssp0_grp",
437 byt_score_ssp0_pins, byt_score_ssp_mux),
438 PIN_GROUP_SIMPLE("ssp1_grp",
439 byt_score_ssp1_pins, byt_score_ssp_mux),
440 PIN_GROUP_MIXED("sdcard_grp",
441 byt_score_sdcard_pins, byt_score_sdcard_mux),
442 PIN_GROUP_SIMPLE("sdio_grp",
443 byt_score_sdio_pins, byt_score_sdio_mux),
444 PIN_GROUP_SIMPLE("emmc_grp",
445 byt_score_emmc_pins, byt_score_emmc_mux),
446 PIN_GROUP_SIMPLE("lpc_grp",
447 byt_score_ilb_lpc_pins, byt_score_lpc_mux),
448 PIN_GROUP_SIMPLE("sata_grp",
449 byt_score_sata_pins, byt_score_sata_mux),
450 PIN_GROUP_SIMPLE("plt_clk0_grp",
451 byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
452 PIN_GROUP_SIMPLE("plt_clk1_grp",
453 byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
454 PIN_GROUP_SIMPLE("plt_clk2_grp",
455 byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
456 PIN_GROUP_SIMPLE("plt_clk3_grp",
457 byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
458 PIN_GROUP_SIMPLE("plt_clk4_grp",
459 byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
460 PIN_GROUP_SIMPLE("plt_clk5_grp",
461 byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
462 PIN_GROUP_SIMPLE("smbus_grp",
463 byt_score_smbus_pins, byt_score_smbus_mux),
466 static const char * const byt_score_uart_groups[] = {
467 "uart1_grp", "uart2_grp",
469 static const char * const byt_score_pwm_groups[] = {
470 "pwm0_grp", "pwm1_grp",
472 static const char * const byt_score_ssp_groups[] = {
473 "ssp0_grp", "ssp1_grp", "ssp2_grp",
475 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
476 static const char * const byt_score_i2c_groups[] = {
477 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
480 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
481 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
482 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
483 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
484 static const char * const byt_score_sata_groups[] = { "sata_grp" };
485 static const char * const byt_score_plt_clk_groups[] = {
486 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
487 "plt_clk4_grp", "plt_clk5_grp",
489 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
490 static const char * const byt_score_gpio_groups[] = {
491 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
492 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
493 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
494 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
495 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
496 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
500 static const struct byt_function byt_score_functions[] = {
501 FUNCTION("uart", byt_score_uart_groups),
502 FUNCTION("pwm", byt_score_pwm_groups),
503 FUNCTION("ssp", byt_score_ssp_groups),
504 FUNCTION("spi", byt_score_spi_groups),
505 FUNCTION("i2c", byt_score_i2c_groups),
506 FUNCTION("sdcard", byt_score_sdcard_groups),
507 FUNCTION("sdio", byt_score_sdio_groups),
508 FUNCTION("emmc", byt_score_emmc_groups),
509 FUNCTION("lpc", byt_score_lpc_groups),
510 FUNCTION("sata", byt_score_sata_groups),
511 FUNCTION("plt_clk", byt_score_plt_clk_groups),
512 FUNCTION("smbus", byt_score_smbus_groups),
513 FUNCTION("gpio", byt_score_gpio_groups),
516 static const struct byt_community byt_score_communities[] = {
517 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
520 static const struct byt_pinctrl_soc_data byt_score_soc_data = {
521 .uid = BYT_SCORE_ACPI_UID,
522 .pins = byt_score_pins,
523 .npins = ARRAY_SIZE(byt_score_pins),
524 .groups = byt_score_groups,
525 .ngroups = ARRAY_SIZE(byt_score_groups),
526 .functions = byt_score_functions,
527 .nfunctions = ARRAY_SIZE(byt_score_functions),
528 .communities = byt_score_communities,
529 .ncommunities = ARRAY_SIZE(byt_score_communities),
532 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
533 static const struct pinctrl_pin_desc byt_sus_pins[] = {
534 PINCTRL_PIN(0, "GPIO_S50"),
535 PINCTRL_PIN(1, "GPIO_S51"),
536 PINCTRL_PIN(2, "GPIO_S52"),
537 PINCTRL_PIN(3, "GPIO_S53"),
538 PINCTRL_PIN(4, "GPIO_S54"),
539 PINCTRL_PIN(5, "GPIO_S55"),
540 PINCTRL_PIN(6, "GPIO_S56"),
541 PINCTRL_PIN(7, "GPIO_S57"),
542 PINCTRL_PIN(8, "GPIO_S58"),
543 PINCTRL_PIN(9, "GPIO_S59"),
544 PINCTRL_PIN(10, "GPIO_S510"),
545 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
546 PINCTRL_PIN(12, "PMC_SUSCLK0"),
547 PINCTRL_PIN(13, "GPIO_S513"),
548 PINCTRL_PIN(14, "USB_ULPI_RST"),
549 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
550 PINCTRL_PIN(16, "PMC_PWRBTN"),
551 PINCTRL_PIN(17, "GPIO_S517"),
552 PINCTRL_PIN(18, "PMC_SUS_STAT"),
553 PINCTRL_PIN(19, "USB_OC0"),
554 PINCTRL_PIN(20, "USB_OC1"),
555 PINCTRL_PIN(21, "PCU_SPI_CS1"),
556 PINCTRL_PIN(22, "GPIO_S522"),
557 PINCTRL_PIN(23, "GPIO_S523"),
558 PINCTRL_PIN(24, "GPIO_S524"),
559 PINCTRL_PIN(25, "GPIO_S525"),
560 PINCTRL_PIN(26, "GPIO_S526"),
561 PINCTRL_PIN(27, "GPIO_S527"),
562 PINCTRL_PIN(28, "GPIO_S528"),
563 PINCTRL_PIN(29, "GPIO_S529"),
564 PINCTRL_PIN(30, "GPIO_S530"),
565 PINCTRL_PIN(31, "USB_ULPI_CLK"),
566 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
567 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
568 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
569 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
570 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
571 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
572 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
573 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
574 PINCTRL_PIN(40, "USB_ULPI_DIR"),
575 PINCTRL_PIN(41, "USB_ULPI_NXT"),
576 PINCTRL_PIN(42, "USB_ULPI_STP"),
577 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
580 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
581 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
582 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
583 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
584 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
588 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
589 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
590 SIMPLE_FUNC("usb", 0),
591 SIMPLE_FUNC("gpio", 1),
594 static const unsigned int byt_sus_usb_ulpi_pins[] = {
595 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
597 static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
598 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
600 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
601 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
603 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
604 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
605 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
608 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
609 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
610 SIMPLE_FUNC("spi", 0),
611 SIMPLE_FUNC("gpio", 1),
614 static const struct byt_pingroup byt_sus_groups[] = {
615 PIN_GROUP_SIMPLE("usb_oc_grp",
616 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
617 PIN_GROUP_MIXED("usb_ulpi_grp",
618 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
619 PIN_GROUP_SIMPLE("pcu_spi_grp",
620 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
623 static const char * const byt_sus_usb_groups[] = {
624 "usb_oc_grp", "usb_ulpi_grp",
626 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
627 static const char * const byt_sus_gpio_groups[] = {
628 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
631 static const struct byt_function byt_sus_functions[] = {
632 FUNCTION("usb", byt_sus_usb_groups),
633 FUNCTION("spi", byt_sus_spi_groups),
634 FUNCTION("gpio", byt_sus_gpio_groups),
637 static const struct byt_community byt_sus_communities[] = {
638 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
641 static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
642 .uid = BYT_SUS_ACPI_UID,
643 .pins = byt_sus_pins,
644 .npins = ARRAY_SIZE(byt_sus_pins),
645 .groups = byt_sus_groups,
646 .ngroups = ARRAY_SIZE(byt_sus_groups),
647 .functions = byt_sus_functions,
648 .nfunctions = ARRAY_SIZE(byt_sus_functions),
649 .communities = byt_sus_communities,
650 .ncommunities = ARRAY_SIZE(byt_sus_communities),
653 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
654 PINCTRL_PIN(0, "GPIO_NCORE0"),
655 PINCTRL_PIN(1, "GPIO_NCORE1"),
656 PINCTRL_PIN(2, "GPIO_NCORE2"),
657 PINCTRL_PIN(3, "GPIO_NCORE3"),
658 PINCTRL_PIN(4, "GPIO_NCORE4"),
659 PINCTRL_PIN(5, "GPIO_NCORE5"),
660 PINCTRL_PIN(6, "GPIO_NCORE6"),
661 PINCTRL_PIN(7, "GPIO_NCORE7"),
662 PINCTRL_PIN(8, "GPIO_NCORE8"),
663 PINCTRL_PIN(9, "GPIO_NCORE9"),
664 PINCTRL_PIN(10, "GPIO_NCORE10"),
665 PINCTRL_PIN(11, "GPIO_NCORE11"),
666 PINCTRL_PIN(12, "GPIO_NCORE12"),
667 PINCTRL_PIN(13, "GPIO_NCORE13"),
668 PINCTRL_PIN(14, "GPIO_NCORE14"),
669 PINCTRL_PIN(15, "GPIO_NCORE15"),
670 PINCTRL_PIN(16, "GPIO_NCORE16"),
671 PINCTRL_PIN(17, "GPIO_NCORE17"),
672 PINCTRL_PIN(18, "GPIO_NCORE18"),
673 PINCTRL_PIN(19, "GPIO_NCORE19"),
674 PINCTRL_PIN(20, "GPIO_NCORE20"),
675 PINCTRL_PIN(21, "GPIO_NCORE21"),
676 PINCTRL_PIN(22, "GPIO_NCORE22"),
677 PINCTRL_PIN(23, "GPIO_NCORE23"),
678 PINCTRL_PIN(24, "GPIO_NCORE24"),
679 PINCTRL_PIN(25, "GPIO_NCORE25"),
680 PINCTRL_PIN(26, "GPIO_NCORE26"),
681 PINCTRL_PIN(27, "GPIO_NCORE27"),
684 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
685 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
686 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
687 3, 6, 10, 13, 2, 5, 9, 7,
690 static const struct byt_community byt_ncore_communities[] = {
691 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
694 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
695 .uid = BYT_NCORE_ACPI_UID,
696 .pins = byt_ncore_pins,
697 .npins = ARRAY_SIZE(byt_ncore_pins),
698 .communities = byt_ncore_communities,
699 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
702 static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
709 static DEFINE_RAW_SPINLOCK(byt_lock);
711 static struct byt_community *byt_get_community(struct byt_gpio *vg,
714 struct byt_community *comm;
717 for (i = 0; i < vg->soc_data->ncommunities; i++) {
718 comm = vg->communities_copy + i;
719 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
726 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
729 struct byt_community *comm = byt_get_community(vg, offset);
735 offset -= comm->pin_base;
737 case BYT_INT_STAT_REG:
738 reg_offset = (offset / 32) * 4;
740 case BYT_DEBOUNCE_REG:
744 reg_offset = comm->pad_map[offset] * 16;
748 return comm->reg_base + reg_offset + reg;
751 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
753 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
755 return vg->soc_data->ngroups;
758 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
759 unsigned int selector)
761 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
763 return vg->soc_data->groups[selector].name;
766 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
767 unsigned int selector,
768 const unsigned int **pins,
769 unsigned int *num_pins)
771 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
773 *pins = vg->soc_data->groups[selector].pins;
774 *num_pins = vg->soc_data->groups[selector].npins;
779 static const struct pinctrl_ops byt_pinctrl_ops = {
780 .get_groups_count = byt_get_groups_count,
781 .get_group_name = byt_get_group_name,
782 .get_group_pins = byt_get_group_pins,
785 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
787 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
789 return vg->soc_data->nfunctions;
792 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
793 unsigned int selector)
795 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
797 return vg->soc_data->functions[selector].name;
800 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
801 unsigned int selector,
802 const char * const **groups,
803 unsigned int *num_groups)
805 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
807 *groups = vg->soc_data->functions[selector].groups;
808 *num_groups = vg->soc_data->functions[selector].ngroups;
813 static int byt_get_group_simple_mux(const struct byt_pingroup group,
814 const char *func_name,
815 unsigned short *func)
819 for (i = 0; i < group.nfuncs; i++) {
820 if (!strcmp(group.simple_funcs[i].name, func_name)) {
821 *func = group.simple_funcs[i].func;
829 static int byt_get_group_mixed_mux(const struct byt_pingroup group,
830 const char *func_name,
831 const unsigned short **func)
835 for (i = 0; i < group.nfuncs; i++) {
836 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
837 *func = group.mixed_funcs[i].func_values;
845 static void byt_set_group_simple_mux(struct byt_gpio *vg,
846 const struct byt_pingroup group,
852 raw_spin_lock_irqsave(&byt_lock, flags);
854 for (i = 0; i < group.npins; i++) {
855 void __iomem *padcfg0;
858 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
860 dev_warn(&vg->pdev->dev,
861 "Group %s, pin %i not muxed (no padcfg0)\n",
866 value = readl(padcfg0);
867 value &= ~BYT_PIN_MUX;
869 writel(value, padcfg0);
872 raw_spin_unlock_irqrestore(&byt_lock, flags);
875 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
876 const struct byt_pingroup group,
877 const unsigned short *func)
882 raw_spin_lock_irqsave(&byt_lock, flags);
884 for (i = 0; i < group.npins; i++) {
885 void __iomem *padcfg0;
888 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
890 dev_warn(&vg->pdev->dev,
891 "Group %s, pin %i not muxed (no padcfg0)\n",
896 value = readl(padcfg0);
897 value &= ~BYT_PIN_MUX;
899 writel(value, padcfg0);
902 raw_spin_unlock_irqrestore(&byt_lock, flags);
905 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
906 unsigned int group_selector)
908 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
909 const struct byt_function func = vg->soc_data->functions[func_selector];
910 const struct byt_pingroup group = vg->soc_data->groups[group_selector];
911 const unsigned short *mixed_func;
912 unsigned short simple_func;
915 if (group.has_simple_funcs)
916 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
918 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
921 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
922 else if (group.has_simple_funcs)
923 byt_set_group_simple_mux(vg, group, simple_func);
925 byt_set_group_mixed_mux(vg, group, mixed_func);
930 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
932 /* SCORE pin 92-93 */
933 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
934 offset >= 92 && offset <= 93)
938 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
939 offset >= 11 && offset <= 21)
945 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
947 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
951 raw_spin_lock_irqsave(&byt_lock, flags);
954 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
955 if (value & BYT_DIRECT_IRQ_EN)
956 /* nothing to do */ ;
958 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
961 raw_spin_unlock_irqrestore(&byt_lock, flags);
964 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
965 struct pinctrl_gpio_range *range,
968 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
969 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
973 raw_spin_lock_irqsave(&byt_lock, flags);
976 * In most cases, func pin mux 000 means GPIO function.
977 * But, some pins may have func pin mux 001 represents
980 * Because there are devices out there where some pins were not
981 * configured correctly we allow changing the mux value from
982 * request (but print out warning about that).
984 value = readl(reg) & BYT_PIN_MUX;
985 gpio_mux = byt_get_gpio_mux(vg, offset);
986 if (gpio_mux != value) {
987 value = readl(reg) & ~BYT_PIN_MUX;
991 dev_warn(&vg->pdev->dev, FW_BUG
992 "pin %u forcibly re-configured as GPIO\n", offset);
995 raw_spin_unlock_irqrestore(&byt_lock, flags);
997 pm_runtime_get(&vg->pdev->dev);
1002 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
1003 struct pinctrl_gpio_range *range,
1004 unsigned int offset)
1006 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1008 byt_gpio_clear_triggering(vg, offset);
1009 pm_runtime_put(&vg->pdev->dev);
1012 static void byt_gpio_direct_irq_check(struct byt_gpio *vg,
1013 unsigned int offset)
1015 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1018 * Before making any direction modifications, do a check if gpio is set
1019 * for direct IRQ. On Bay Trail, setting GPIO to output does not make
1020 * sense, so let's at least inform the caller before they shoot
1021 * themselves in the foot.
1023 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
1024 dev_info_once(&vg->pdev->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
1027 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1028 struct pinctrl_gpio_range *range,
1029 unsigned int offset,
1032 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1033 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1034 unsigned long flags;
1037 raw_spin_lock_irqsave(&byt_lock, flags);
1039 value = readl(val_reg);
1040 value &= ~BYT_DIR_MASK;
1042 value |= BYT_OUTPUT_EN;
1044 byt_gpio_direct_irq_check(vg, offset);
1046 writel(value, val_reg);
1048 raw_spin_unlock_irqrestore(&byt_lock, flags);
1053 static const struct pinmux_ops byt_pinmux_ops = {
1054 .get_functions_count = byt_get_functions_count,
1055 .get_function_name = byt_get_function_name,
1056 .get_function_groups = byt_get_function_groups,
1057 .set_mux = byt_set_mux,
1058 .gpio_request_enable = byt_gpio_request_enable,
1059 .gpio_disable_free = byt_gpio_disable_free,
1060 .gpio_set_direction = byt_gpio_set_direction,
1063 static void byt_get_pull_strength(u32 reg, u16 *strength)
1065 switch (reg & BYT_PULL_STR_MASK) {
1066 case BYT_PULL_STR_2K:
1069 case BYT_PULL_STR_10K:
1072 case BYT_PULL_STR_20K:
1075 case BYT_PULL_STR_40K:
1081 static int byt_set_pull_strength(u32 *reg, u16 strength)
1083 *reg &= ~BYT_PULL_STR_MASK;
1087 *reg |= BYT_PULL_STR_2K;
1090 *reg |= BYT_PULL_STR_10K;
1093 *reg |= BYT_PULL_STR_20K;
1096 *reg |= BYT_PULL_STR_40K;
1105 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1106 unsigned long *config)
1108 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1109 enum pin_config_param param = pinconf_to_config_param(*config);
1110 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1111 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1112 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1113 unsigned long flags;
1114 u32 conf, pull, val, debounce;
1117 raw_spin_lock_irqsave(&byt_lock, flags);
1118 conf = readl(conf_reg);
1119 pull = conf & BYT_PULL_ASSIGN_MASK;
1120 val = readl(val_reg);
1121 raw_spin_unlock_irqrestore(&byt_lock, flags);
1124 case PIN_CONFIG_BIAS_DISABLE:
1128 case PIN_CONFIG_BIAS_PULL_DOWN:
1129 /* Pull assignment is only applicable in input mode */
1130 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1133 byt_get_pull_strength(conf, &arg);
1136 case PIN_CONFIG_BIAS_PULL_UP:
1137 /* Pull assignment is only applicable in input mode */
1138 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1141 byt_get_pull_strength(conf, &arg);
1144 case PIN_CONFIG_INPUT_DEBOUNCE:
1145 if (!(conf & BYT_DEBOUNCE_EN))
1148 raw_spin_lock_irqsave(&byt_lock, flags);
1149 debounce = readl(db_reg);
1150 raw_spin_unlock_irqrestore(&byt_lock, flags);
1152 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1153 case BYT_DEBOUNCE_PULSE_375US:
1156 case BYT_DEBOUNCE_PULSE_750US:
1159 case BYT_DEBOUNCE_PULSE_1500US:
1162 case BYT_DEBOUNCE_PULSE_3MS:
1165 case BYT_DEBOUNCE_PULSE_6MS:
1168 case BYT_DEBOUNCE_PULSE_12MS:
1171 case BYT_DEBOUNCE_PULSE_24MS:
1183 *config = pinconf_to_config_packed(param, arg);
1188 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1189 unsigned int offset,
1190 unsigned long *configs,
1191 unsigned int num_configs)
1193 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1194 unsigned int param, arg;
1195 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1196 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1197 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1198 unsigned long flags;
1199 u32 conf, val, debounce;
1202 raw_spin_lock_irqsave(&byt_lock, flags);
1204 conf = readl(conf_reg);
1205 val = readl(val_reg);
1207 for (i = 0; i < num_configs; i++) {
1208 param = pinconf_to_config_param(configs[i]);
1209 arg = pinconf_to_config_argument(configs[i]);
1212 case PIN_CONFIG_BIAS_DISABLE:
1213 conf &= ~BYT_PULL_ASSIGN_MASK;
1215 case PIN_CONFIG_BIAS_PULL_DOWN:
1216 /* Set default strength value in case none is given */
1221 * Pull assignment is only applicable in input mode. If
1222 * chip is not in input mode, set it and warn about it.
1224 if (val & BYT_INPUT_EN) {
1225 val &= ~BYT_INPUT_EN;
1226 writel(val, val_reg);
1227 dev_warn(&vg->pdev->dev,
1228 "pin %u forcibly set to input mode\n",
1232 conf &= ~BYT_PULL_ASSIGN_MASK;
1233 conf |= BYT_PULL_ASSIGN_DOWN;
1234 ret = byt_set_pull_strength(&conf, arg);
1237 case PIN_CONFIG_BIAS_PULL_UP:
1238 /* Set default strength value in case none is given */
1243 * Pull assignment is only applicable in input mode. If
1244 * chip is not in input mode, set it and warn about it.
1246 if (val & BYT_INPUT_EN) {
1247 val &= ~BYT_INPUT_EN;
1248 writel(val, val_reg);
1249 dev_warn(&vg->pdev->dev,
1250 "pin %u forcibly set to input mode\n",
1254 conf &= ~BYT_PULL_ASSIGN_MASK;
1255 conf |= BYT_PULL_ASSIGN_UP;
1256 ret = byt_set_pull_strength(&conf, arg);
1259 case PIN_CONFIG_INPUT_DEBOUNCE:
1260 debounce = readl(db_reg);
1263 conf |= BYT_DEBOUNCE_EN;
1265 conf &= ~BYT_DEBOUNCE_EN;
1269 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1270 debounce |= BYT_DEBOUNCE_PULSE_375US;
1273 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1274 debounce |= BYT_DEBOUNCE_PULSE_750US;
1277 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1278 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1281 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1282 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1285 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1286 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1289 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1290 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1293 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1294 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1303 writel(debounce, db_reg);
1314 writel(conf, conf_reg);
1316 raw_spin_unlock_irqrestore(&byt_lock, flags);
1321 static const struct pinconf_ops byt_pinconf_ops = {
1323 .pin_config_get = byt_pin_config_get,
1324 .pin_config_set = byt_pin_config_set,
1327 static const struct pinctrl_desc byt_pinctrl_desc = {
1328 .pctlops = &byt_pinctrl_ops,
1329 .pmxops = &byt_pinmux_ops,
1330 .confops = &byt_pinconf_ops,
1331 .owner = THIS_MODULE,
1334 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1336 struct byt_gpio *vg = gpiochip_get_data(chip);
1337 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1338 unsigned long flags;
1341 raw_spin_lock_irqsave(&byt_lock, flags);
1343 raw_spin_unlock_irqrestore(&byt_lock, flags);
1345 return !!(val & BYT_LEVEL);
1348 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1350 struct byt_gpio *vg = gpiochip_get_data(chip);
1351 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1352 unsigned long flags;
1358 raw_spin_lock_irqsave(&byt_lock, flags);
1359 old_val = readl(reg);
1361 writel(old_val | BYT_LEVEL, reg);
1363 writel(old_val & ~BYT_LEVEL, reg);
1364 raw_spin_unlock_irqrestore(&byt_lock, flags);
1367 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1369 struct byt_gpio *vg = gpiochip_get_data(chip);
1370 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1371 unsigned long flags;
1377 raw_spin_lock_irqsave(&byt_lock, flags);
1379 raw_spin_unlock_irqrestore(&byt_lock, flags);
1381 if (!(value & BYT_OUTPUT_EN))
1382 return GPIOF_DIR_OUT;
1383 if (!(value & BYT_INPUT_EN))
1384 return GPIOF_DIR_IN;
1389 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1391 struct byt_gpio *vg = gpiochip_get_data(chip);
1392 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1393 unsigned long flags;
1396 raw_spin_lock_irqsave(&byt_lock, flags);
1398 reg = readl(val_reg);
1399 reg &= ~BYT_DIR_MASK;
1400 reg |= BYT_OUTPUT_EN;
1401 writel(reg, val_reg);
1403 raw_spin_unlock_irqrestore(&byt_lock, flags);
1408 * Note despite the temptation this MUST NOT be converted into a call to
1409 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1410 * MUST be done as a single BYT_VAL_REG register write.
1411 * See the commit message of the commit adding this comment for details.
1413 static int byt_gpio_direction_output(struct gpio_chip *chip,
1414 unsigned int offset, int value)
1416 struct byt_gpio *vg = gpiochip_get_data(chip);
1417 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1418 unsigned long flags;
1421 raw_spin_lock_irqsave(&byt_lock, flags);
1423 byt_gpio_direct_irq_check(vg, offset);
1425 reg = readl(val_reg);
1426 reg &= ~BYT_DIR_MASK;
1432 writel(reg, val_reg);
1434 raw_spin_unlock_irqrestore(&byt_lock, flags);
1438 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1440 struct byt_gpio *vg = gpiochip_get_data(chip);
1444 for (i = 0; i < vg->soc_data->npins; i++) {
1445 const struct byt_community *comm;
1446 const char *pull_str = NULL;
1447 const char *pull = NULL;
1449 unsigned long flags;
1453 raw_spin_lock_irqsave(&byt_lock, flags);
1454 pin = vg->soc_data->pins[i].number;
1455 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1458 "Could not retrieve pin %i conf0 reg\n",
1460 raw_spin_unlock_irqrestore(&byt_lock, flags);
1465 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1468 "Could not retrieve pin %i val reg\n", pin);
1469 raw_spin_unlock_irqrestore(&byt_lock, flags);
1473 raw_spin_unlock_irqrestore(&byt_lock, flags);
1475 comm = byt_get_community(vg, pin);
1478 "Could not get community for pin %i\n", pin);
1481 label = gpiochip_is_requested(chip, i);
1483 label = "Unrequested";
1485 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1486 case BYT_PULL_ASSIGN_UP:
1489 case BYT_PULL_ASSIGN_DOWN:
1494 switch (conf0 & BYT_PULL_STR_MASK) {
1495 case BYT_PULL_STR_2K:
1498 case BYT_PULL_STR_10K:
1501 case BYT_PULL_STR_20K:
1504 case BYT_PULL_STR_40K:
1510 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1513 val & BYT_INPUT_EN ? " " : "in",
1514 val & BYT_OUTPUT_EN ? " " : "out",
1515 val & BYT_LEVEL ? "hi" : "lo",
1516 comm->pad_map[i], comm->pad_map[i] * 16,
1518 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1519 conf0 & BYT_TRIG_POS ? " rise" : " ",
1520 conf0 & BYT_TRIG_LVL ? " level" : " ");
1522 if (pull && pull_str)
1523 seq_printf(s, " %-4s %-3s", pull, pull_str);
1527 if (conf0 & BYT_IODEN)
1528 seq_puts(s, " open-drain");
1534 static const struct gpio_chip byt_gpio_chip = {
1535 .owner = THIS_MODULE,
1536 .request = gpiochip_generic_request,
1537 .free = gpiochip_generic_free,
1538 .get_direction = byt_gpio_get_direction,
1539 .direction_input = byt_gpio_direction_input,
1540 .direction_output = byt_gpio_direction_output,
1541 .get = byt_gpio_get,
1542 .set = byt_gpio_set,
1543 .set_config = gpiochip_generic_config,
1544 .dbg_show = byt_gpio_dbg_show,
1547 static void byt_irq_ack(struct irq_data *d)
1549 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1550 struct byt_gpio *vg = gpiochip_get_data(gc);
1551 unsigned offset = irqd_to_hwirq(d);
1554 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1558 raw_spin_lock(&byt_lock);
1559 writel(BIT(offset % 32), reg);
1560 raw_spin_unlock(&byt_lock);
1563 static void byt_irq_mask(struct irq_data *d)
1565 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1566 struct byt_gpio *vg = gpiochip_get_data(gc);
1568 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1571 static void byt_irq_unmask(struct irq_data *d)
1573 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1574 struct byt_gpio *vg = gpiochip_get_data(gc);
1575 unsigned offset = irqd_to_hwirq(d);
1576 unsigned long flags;
1580 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1584 raw_spin_lock_irqsave(&byt_lock, flags);
1587 switch (irqd_get_trigger_type(d)) {
1588 case IRQ_TYPE_LEVEL_HIGH:
1589 value |= BYT_TRIG_LVL;
1591 case IRQ_TYPE_EDGE_RISING:
1592 value |= BYT_TRIG_POS;
1594 case IRQ_TYPE_LEVEL_LOW:
1595 value |= BYT_TRIG_LVL;
1597 case IRQ_TYPE_EDGE_FALLING:
1598 value |= BYT_TRIG_NEG;
1600 case IRQ_TYPE_EDGE_BOTH:
1601 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1607 raw_spin_unlock_irqrestore(&byt_lock, flags);
1610 static int byt_irq_type(struct irq_data *d, unsigned int type)
1612 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1613 u32 offset = irqd_to_hwirq(d);
1615 unsigned long flags;
1616 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1618 if (!reg || offset >= vg->chip.ngpio)
1621 raw_spin_lock_irqsave(&byt_lock, flags);
1624 WARN(value & BYT_DIRECT_IRQ_EN,
1625 "Bad pad config for io mode, force direct_irq_en bit clearing");
1627 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1628 * are used to indicate high and low level triggering
1630 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1632 /* Enable glitch filtering */
1633 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1634 BYT_GLITCH_F_FAST_CLK;
1638 if (type & IRQ_TYPE_EDGE_BOTH)
1639 irq_set_handler_locked(d, handle_edge_irq);
1640 else if (type & IRQ_TYPE_LEVEL_MASK)
1641 irq_set_handler_locked(d, handle_level_irq);
1643 raw_spin_unlock_irqrestore(&byt_lock, flags);
1648 static struct irq_chip byt_irqchip = {
1650 .irq_ack = byt_irq_ack,
1651 .irq_mask = byt_irq_mask,
1652 .irq_unmask = byt_irq_unmask,
1653 .irq_set_type = byt_irq_type,
1654 .flags = IRQCHIP_SKIP_SET_WAKE,
1657 static void byt_gpio_irq_handler(struct irq_desc *desc)
1659 struct irq_data *data = irq_desc_get_irq_data(desc);
1660 struct byt_gpio *vg = gpiochip_get_data(
1661 irq_desc_get_handler_data(desc));
1662 struct irq_chip *chip = irq_data_get_irq_chip(data);
1665 unsigned long pending;
1668 /* check from GPIO controller which pin triggered the interrupt */
1669 for (base = 0; base < vg->chip.ngpio; base += 32) {
1670 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1673 dev_warn(&vg->pdev->dev,
1674 "Pin %i: could not retrieve interrupt status register\n",
1679 raw_spin_lock(&byt_lock);
1680 pending = readl(reg);
1681 raw_spin_unlock(&byt_lock);
1682 for_each_set_bit(pin, &pending, 32) {
1683 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1684 generic_handle_irq(virq);
1687 chip->irq_eoi(data);
1690 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1692 struct gpio_chip *gc = &vg->chip;
1693 struct device *dev = &vg->pdev->dev;
1699 * Clear interrupt triggers for all pins that are GPIOs and
1700 * do not use direct IRQ mode. This will prevent spurious
1701 * interrupts from misconfigured pins.
1703 for (i = 0; i < vg->soc_data->npins; i++) {
1704 unsigned int pin = vg->soc_data->pins[i].number;
1706 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1708 dev_warn(&vg->pdev->dev,
1709 "Pin %i: could not retrieve conf0 register\n",
1715 if (value & BYT_DIRECT_IRQ_EN) {
1716 clear_bit(i, gc->irq.valid_mask);
1717 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1718 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1719 byt_gpio_clear_triggering(vg, i);
1720 dev_dbg(dev, "disabling GPIO %d\n", i);
1724 /* clear interrupt status trigger registers */
1725 for (base = 0; base < vg->soc_data->npins; base += 32) {
1726 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1729 dev_warn(&vg->pdev->dev,
1730 "Pin %i: could not retrieve irq status reg\n",
1735 writel(0xffffffff, reg);
1736 /* make sure trigger bits are cleared, if not then a pin
1737 might be misconfigured in bios */
1740 dev_err(&vg->pdev->dev,
1741 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1746 static int byt_gpio_probe(struct byt_gpio *vg)
1748 struct gpio_chip *gc;
1749 struct resource *irq_rc;
1752 /* Set up gpio chip */
1753 vg->chip = byt_gpio_chip;
1755 gc->label = dev_name(&vg->pdev->dev);
1757 gc->can_sleep = false;
1758 gc->parent = &vg->pdev->dev;
1759 gc->ngpio = vg->soc_data->npins;
1760 gc->irq.need_valid_mask = true;
1762 #ifdef CONFIG_PM_SLEEP
1763 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1764 sizeof(*vg->saved_context), GFP_KERNEL);
1766 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1768 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1772 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1773 0, 0, vg->soc_data->npins);
1775 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1779 /* set up interrupts */
1780 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1781 if (irq_rc && irq_rc->start) {
1782 byt_gpio_irq_init_hw(vg);
1783 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1784 handle_bad_irq, IRQ_TYPE_NONE);
1786 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1790 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1791 (unsigned)irq_rc->start,
1792 byt_gpio_irq_handler);
1798 static int byt_set_soc_data(struct byt_gpio *vg,
1799 const struct byt_pinctrl_soc_data *soc_data)
1803 vg->soc_data = soc_data;
1804 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1805 soc_data->ncommunities,
1806 sizeof(*vg->communities_copy),
1808 if (!vg->communities_copy)
1811 for (i = 0; i < soc_data->ncommunities; i++) {
1812 struct byt_community *comm = vg->communities_copy + i;
1813 struct resource *mem_rc;
1815 *comm = vg->soc_data->communities[i];
1817 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1818 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1819 if (IS_ERR(comm->reg_base))
1820 return PTR_ERR(comm->reg_base);
1826 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1827 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1828 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1831 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1833 static int byt_pinctrl_probe(struct platform_device *pdev)
1835 const struct byt_pinctrl_soc_data *soc_data = NULL;
1836 const struct byt_pinctrl_soc_data **soc_table;
1837 const struct acpi_device_id *acpi_id;
1838 struct acpi_device *acpi_dev;
1839 struct byt_gpio *vg;
1842 acpi_dev = ACPI_COMPANION(&pdev->dev);
1846 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1850 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1852 for (i = 0; soc_table[i]; i++) {
1853 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1854 soc_data = soc_table[i];
1862 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1867 ret = byt_set_soc_data(vg, soc_data);
1869 dev_err(&pdev->dev, "failed to set soc data\n");
1873 vg->pctl_desc = byt_pinctrl_desc;
1874 vg->pctl_desc.name = dev_name(&pdev->dev);
1875 vg->pctl_desc.pins = vg->soc_data->pins;
1876 vg->pctl_desc.npins = vg->soc_data->npins;
1878 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1879 if (IS_ERR(vg->pctl_dev)) {
1880 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1881 return PTR_ERR(vg->pctl_dev);
1884 ret = byt_gpio_probe(vg);
1888 platform_set_drvdata(pdev, vg);
1889 pm_runtime_enable(&pdev->dev);
1894 #ifdef CONFIG_PM_SLEEP
1895 static int byt_gpio_suspend(struct device *dev)
1897 struct platform_device *pdev = to_platform_device(dev);
1898 struct byt_gpio *vg = platform_get_drvdata(pdev);
1899 unsigned long flags;
1902 raw_spin_lock_irqsave(&byt_lock, flags);
1904 for (i = 0; i < vg->soc_data->npins; i++) {
1907 unsigned int pin = vg->soc_data->pins[i].number;
1909 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1911 dev_warn(&vg->pdev->dev,
1912 "Pin %i: could not retrieve conf0 register\n",
1916 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1917 vg->saved_context[i].conf0 = value;
1919 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1920 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1921 vg->saved_context[i].val = value;
1924 raw_spin_unlock_irqrestore(&byt_lock, flags);
1928 static int byt_gpio_resume(struct device *dev)
1930 struct platform_device *pdev = to_platform_device(dev);
1931 struct byt_gpio *vg = platform_get_drvdata(pdev);
1932 unsigned long flags;
1935 raw_spin_lock_irqsave(&byt_lock, flags);
1937 for (i = 0; i < vg->soc_data->npins; i++) {
1940 unsigned int pin = vg->soc_data->pins[i].number;
1942 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1944 dev_warn(&vg->pdev->dev,
1945 "Pin %i: could not retrieve conf0 register\n",
1950 if ((value & BYT_CONF0_RESTORE_MASK) !=
1951 vg->saved_context[i].conf0) {
1952 value &= ~BYT_CONF0_RESTORE_MASK;
1953 value |= vg->saved_context[i].conf0;
1955 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1958 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1960 if ((value & BYT_VAL_RESTORE_MASK) !=
1961 vg->saved_context[i].val) {
1964 v = value & ~BYT_VAL_RESTORE_MASK;
1965 v |= vg->saved_context[i].val;
1968 dev_dbg(dev, "restored pin %d val %#08x\n",
1974 raw_spin_unlock_irqrestore(&byt_lock, flags);
1980 static int byt_gpio_runtime_suspend(struct device *dev)
1985 static int byt_gpio_runtime_resume(struct device *dev)
1991 static const struct dev_pm_ops byt_gpio_pm_ops = {
1992 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1993 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1997 static struct platform_driver byt_gpio_driver = {
1998 .probe = byt_pinctrl_probe,
2001 .pm = &byt_gpio_pm_ops,
2002 .suppress_bind_attrs = true,
2004 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
2008 static int __init byt_gpio_init(void)
2010 return platform_driver_register(&byt_gpio_driver);
2012 subsys_initcall(byt_gpio_init);