1 # SPDX-License-Identifier: GPL-2.0
2 # Intel pin control drivers
4 if (X86 || COMPILE_TEST)
6 config PINCTRL_BAYTRAIL
7 bool "Intel Baytrail GPIO pin control"
11 driver for memory mapped GPIO functionality on Intel Baytrail
12 platforms. Supports 3 banks with 102, 28 and 44 gpios.
13 Most pins are usually muxed to some other functionality by firmware,
14 so only a small amount is available for gpio use.
16 Requires ACPI device enumeration code to set up a platform device.
18 config PINCTRL_CHERRYVIEW
19 tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
23 Cherryview/Braswell pinctrl driver provides an interface that
24 allows configuring of SoC pins and using them as GPIOs.
26 config PINCTRL_LYNXPOINT
27 tristate "Intel Lynxpoint pinctrl and GPIO driver"
31 select GENERIC_PINCONF
33 select GPIOLIB_IRQCHIP
35 Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
36 provides an interface that allows configuring of PCH pins and
39 config PINCTRL_MERRIFIELD
40 tristate "Intel Merrifield pinctrl driver"
41 depends on X86_INTEL_MID
44 select GENERIC_PINCONF
46 Merrifield Family-Level Interface Shim (FLIS) driver provides an
47 interface that allows configuring of SoC pins and using them as
54 select GENERIC_PINCONF
56 select GPIOLIB_IRQCHIP
58 config PINCTRL_BROXTON
59 tristate "Intel Broxton pinctrl and GPIO driver"
63 Broxton pinctrl driver provides an interface that allows
64 configuring of SoC pins and using them as GPIOs.
66 config PINCTRL_CANNONLAKE
67 tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
71 This pinctrl driver provides an interface that allows configuring
72 of Intel Cannon Lake PCH pins and using them as GPIOs.
74 config PINCTRL_CEDARFORK
75 tristate "Intel Cedar Fork pinctrl and GPIO driver"
79 This pinctrl driver provides an interface that allows configuring
80 of Intel Cedar Fork PCH pins and using them as GPIOs.
82 config PINCTRL_DENVERTON
83 tristate "Intel Denverton pinctrl and GPIO driver"
87 This pinctrl driver provides an interface that allows configuring
88 of Intel Denverton SoC pins and using them as GPIOs.
90 config PINCTRL_EMMITSBURG
91 tristate "Intel Emmitsburg pinctrl and GPIO driver"
95 This pinctrl driver provides an interface that allows configuring
96 of Intel Emmitsburg pins and using them as GPIOs.
98 config PINCTRL_GEMINILAKE
99 tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
103 This pinctrl driver provides an interface that allows configuring
104 of Intel Gemini Lake SoC pins and using them as GPIOs.
106 config PINCTRL_ICELAKE
107 tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
111 This pinctrl driver provides an interface that allows configuring
112 of Intel Ice Lake PCH pins and using them as GPIOs.
114 config PINCTRL_JASPERLAKE
115 tristate "Intel Jasper Lake PCH pinctrl and GPIO driver"
119 This pinctrl driver provides an interface that allows configuring
120 of Intel Jasper Lake PCH pins and using them as GPIOs.
122 config PINCTRL_LEWISBURG
123 tristate "Intel Lewisburg pinctrl and GPIO driver"
127 This pinctrl driver provides an interface that allows configuring
128 of Intel Lewisburg pins and using them as GPIOs.
130 config PINCTRL_SUNRISEPOINT
131 tristate "Intel Sunrisepoint pinctrl and GPIO driver"
135 Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
136 provides an interface that allows configuring of PCH pins and
139 config PINCTRL_TIGERLAKE
140 tristate "Intel Tiger Lake pinctrl and GPIO driver"
144 This pinctrl driver provides an interface that allows configuring
145 of Intel Tiger Lake PCH pins and using them as GPIOs.