drivers/pinctrl/bcm/pinctrl-nsp-mux.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (C) 2015 Broadcom Corporation
   3  *
   4  * This file contains the Northstar plus (NSP) IOMUX driver that supports
   5  * group based PINMUX configuration. The Northstar plus IOMUX controller
   6  * allows pins to be individually muxed to GPIO function. The NAND and MMC is
   7  * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
   8  * To select PWM, one need to enable the corresponding gpio_b as well.
   9  *
  10  *                              gpio_a (8 - 11)
  11  *                              +----------
  12  *                              |
  13  *              gpio_a (8-11)   |       gpio_b (0 - 3)
  14  *      ------------------------+-------+----------
  15  *                                      |
  16  *                                      |       pwm (0 - 3)
  17  *                                      +----------
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29
  30 #include "../core.h"
  31 #include "../pinctrl-utils.h"
  32
  33 #define NSP_MUX_BASE0   0x00
  34 #define NSP_MUX_BASE1   0x01
  35 #define NSP_MUX_BASE2   0x02
  36 /*
  37  * nsp IOMUX register description
  38  *
  39  * @base: base 0 or base 1
  40  * @shift: bit shift for mux configuration of a group
  41  * @mask: bit mask of the function
  42  * @alt: alternate function to set to
  43  */
  44 struct nsp_mux {
  45         unsigned int base;
  46         unsigned int shift;
  47         unsigned int mask;
  48         unsigned int alt;
  49 };
  50
  51 /*
  52  * Keep track of nsp IOMUX configuration and prevent double configuration
  53  *
  54  * @nsp_mux: nsp IOMUX register description
  55  * @is_configured: flag to indicate whether a mux setting has already been
  56  * configured
  57  */
  58 struct nsp_mux_log {
  59         struct nsp_mux mux;
  60         bool is_configured;
  61 };
  62
  63 /*
  64  * Group based IOMUX configuration
  65  *
  66  * @name: name of the group
  67  * @pins: array of pins used by this group
  68  * @num_pins: total number of pins used by this group
  69  * @mux: nsp group based IOMUX configuration
  70  */
  71 struct nsp_pin_group {
  72         const char *name;
  73         const unsigned int *pins;
  74         const unsigned int num_pins;
  75         const struct nsp_mux mux;
  76 };
  77
  78 /*
  79  * nsp mux function and supported pin groups
  80  *
  81  * @name: name of the function
  82  * @groups: array of groups that can be supported by this function
  83  * @num_groups: total number of groups that can be supported by this function
  84  */
  85 struct nsp_pin_function {
  86         const char *name;
  87         const char * const *groups;
  88         const unsigned int num_groups;
  89 };
  90
  91 /*
  92  * nsp IOMUX pinctrl core
  93  *
  94  * @pctl: pointer to pinctrl_dev
  95  * @dev: pointer to device
  96  * @base0: first mux register
  97  * @base1: second mux register
  98  * @base2: third mux register
  99  * @groups: pointer to array of groups
 100  * @num_groups: total number of groups
 101  * @functions: pointer to array of functions
 102  * @num_functions: total number of functions
 103  * @mux_log: pointer to the array of mux logs
 104  * @lock: lock to protect register access
 105  */
 106 struct nsp_pinctrl {
 107         struct pinctrl_dev *pctl;
 108         struct device *dev;
 109         void __iomem *base0;
 110         void __iomem *base1;
 111         void __iomem *base2;
 112         const struct nsp_pin_group *groups;
 113         unsigned int num_groups;
 114         const struct nsp_pin_function *functions;
 115         unsigned int num_functions;
 116         struct nsp_mux_log *mux_log;
 117         spinlock_t lock;
 118 };
 119
 120 /*
 121  * Description of a pin in nsp
 122  *
 123  * @pin: pin number
 124  * @name: pin name
 125  * @gpio_select: reg data to select GPIO
 126  */
 127 struct nsp_pin {
 128         unsigned int pin;
 129         char *name;
 130         unsigned int gpio_select;
 131 };
 132
 133 #define NSP_PIN_DESC(p, n, g)           \
 134 {                                       \
 135         .pin = p,                       \
 136         .name = n,                      \
 137         .gpio_select = g,               \
 138 }
 139
 140 /*
 141  * List of muxable pins in nsp
 142  */
 143 static struct nsp_pin nsp_pins[] = {
 144         NSP_PIN_DESC(0, "spi_clk", 1),
 145         NSP_PIN_DESC(1, "spi_ss", 1),
 146         NSP_PIN_DESC(2, "spi_mosi", 1),
 147         NSP_PIN_DESC(3, "spi_miso", 1),
 148         NSP_PIN_DESC(4, "scl", 1),
 149         NSP_PIN_DESC(5, "sda", 1),
 150         NSP_PIN_DESC(6, "mdc", 1),
 151         NSP_PIN_DESC(7, "mdio", 1),
 152         NSP_PIN_DESC(8, "pwm0", 1),
 153         NSP_PIN_DESC(9, "pwm1", 1),
 154         NSP_PIN_DESC(10, "pwm2", 1),
 155         NSP_PIN_DESC(11, "pwm3", 1),
 156         NSP_PIN_DESC(12, "uart1_rx", 1),
 157         NSP_PIN_DESC(13, "uart1_tx", 1),
 158         NSP_PIN_DESC(14, "uart1_cts", 1),
 159         NSP_PIN_DESC(15, "uart1_rts", 1),
 160         NSP_PIN_DESC(16, "uart2_rx", 1),
 161         NSP_PIN_DESC(17, "uart2_tx", 1),
 162         NSP_PIN_DESC(18, "synce", 0),
 163         NSP_PIN_DESC(19, "sata0_led", 0),
 164         NSP_PIN_DESC(20, "sata1_led", 0),
 165         NSP_PIN_DESC(21, "xtal_out", 1),
 166         NSP_PIN_DESC(22, "sdio_pwr", 1),
 167         NSP_PIN_DESC(23, "sdio_en_1p8v", 1),
 168         NSP_PIN_DESC(24, "gpio_24", 1),
 169         NSP_PIN_DESC(25, "gpio_25", 1),
 170         NSP_PIN_DESC(26, "p5_led0", 0),
 171         NSP_PIN_DESC(27, "p5_led1", 0),
 172         NSP_PIN_DESC(28, "gpio_28", 1),
 173         NSP_PIN_DESC(29, "gpio_29", 1),
 174         NSP_PIN_DESC(30, "gpio_30", 1),
 175         NSP_PIN_DESC(31, "gpio_31", 1),
 176         NSP_PIN_DESC(32, "nand_ale", 0),
 177         NSP_PIN_DESC(33, "nand_ce0", 0),
 178         NSP_PIN_DESC(34, "nand_r/b", 0),
 179         NSP_PIN_DESC(35, "nand_dq0", 0),
 180         NSP_PIN_DESC(36, "nand_dq1", 0),
 181         NSP_PIN_DESC(37, "nand_dq2", 0),
 182         NSP_PIN_DESC(38, "nand_dq3", 0),
 183         NSP_PIN_DESC(39, "nand_dq4", 0),
 184         NSP_PIN_DESC(40, "nand_dq5", 0),
 185         NSP_PIN_DESC(41, "nand_dq6", 0),
 186         NSP_PIN_DESC(42, "nand_dq7", 0),
 187 };
 188
 189 /*
 190  * List of groups of pins
 191  */
 192
 193 static const unsigned int spi_pins[] = {0, 1, 2, 3};
 194 static const unsigned int i2c_pins[] = {4, 5};
 195 static const unsigned int mdio_pins[] = {6, 7};
 196 static const unsigned int pwm0_pins[] = {8};
 197 static const unsigned int gpio_b_0_pins[] = {8};
 198 static const unsigned int pwm1_pins[] = {9};
 199 static const unsigned int gpio_b_1_pins[] = {9};
 200 static const unsigned int pwm2_pins[] = {10};
 201 static const unsigned int gpio_b_2_pins[] = {10};
 202 static const unsigned int pwm3_pins[] = {11};
 203 static const unsigned int gpio_b_3_pins[] = {11};
 204 static const unsigned int uart1_pins[] = {12, 13, 14, 15};
 205 static const unsigned int uart2_pins[] = {16, 17};
 206 static const unsigned int synce_pins[] = {18};
 207 static const unsigned int sata0_led_pins[] = {19};
 208 static const unsigned int sata1_led_pins[] = {20};
 209 static const unsigned int xtal_out_pins[] = {21};
 210 static const unsigned int sdio_pwr_pins[] = {22};
 211 static const unsigned int sdio_1p8v_pins[] = {23};
 212 static const unsigned int switch_p05_led0_pins[] = {26};
 213 static const unsigned int switch_p05_led1_pins[] = {27};
 214 static const unsigned int nand_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
 215                                                         40, 41, 42};
 216 static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
 217                                                         40, 41, 42};
 218
 219 #define NSP_PIN_GROUP(group_name, ba, sh, ma, al)       \
 220 {                                                       \
 221         .name = __stringify(group_name) "_grp",         \
 222         .pins = group_name ## _pins,                    \
 223         .num_pins = ARRAY_SIZE(group_name ## _pins),    \
 224         .mux = {                                        \
 225                 .base = ba,                             \
 226                 .shift = sh,                            \
 227                 .mask = ma,                             \
 228                 .alt = al,                              \
 229         }                                               \
 230 }
 231
 232 /*
 233  * List of nsp pin groups
 234  */
 235 static const struct nsp_pin_group nsp_pin_groups[] = {
 236         NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00),
 237         NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00),
 238         NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00),
 239         NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00),
 240         NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01),
 241         NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00),
 242         NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01),
 243         NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00),
 244         NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01),
 245         NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00),
 246         NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01),
 247         NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00),
 248         NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00),
 249         NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01),
 250         NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01),
 251         NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01),
 252         NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00),
 253         NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00),
 254         NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00),
 255         NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01),
 256         NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01),
 257         NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00),
 258         NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01)
 259 };
 260
 261 /*
 262  * List of groups supported by functions
 263  */
 264
 265 static const char * const spi_grps[] = {"spi_grp"};
 266 static const char * const i2c_grps[] = {"i2c_grp"};
 267 static const char * const mdio_grps[] = {"mdio_grp"};
 268 static const char * const pwm_grps[] = {"pwm0_grp", "pwm1_grp", "pwm2_grp"
 269                                                 , "pwm3_grp"};
 270 static const char * const gpio_b_grps[] = {"gpio_b_0_grp", "gpio_b_1_grp",
 271                                         "gpio_b_2_grp", "gpio_b_3_grp"};
 272 static const char * const uart1_grps[] = {"uart1_grp"};
 273 static const char * const uart2_grps[] = {"uart2_grp"};
 274 static const char * const synce_grps[] = {"synce_grp"};
 275 static const char * const sata_led_grps[] = {"sata0_led_grp", "sata1_led_grp"};
 276 static const char * const xtal_out_grps[] = {"xtal_out_grp"};
 277 static const char * const sdio_grps[] = {"sdio_pwr_grp", "sdio_1p8v_grp"};
 278 static const char * const switch_led_grps[] = {"switch_p05_led0_grp",
 279                                                 "switch_p05_led1_grp"};
 280 static const char * const nand_grps[] = {"nand_grp"};
 281 static const char * const emmc_grps[] = {"emmc_grp"};
 282
 283 #define NSP_PIN_FUNCTION(func)                          \
 284 {                                                       \
 285         .name = #func,                                  \
 286         .groups = func ## _grps,                        \
 287         .num_groups = ARRAY_SIZE(func ## _grps),        \
 288 }
 289
 290 /*
 291  * List of supported functions in nsp
 292  */
 293 static const struct nsp_pin_function nsp_pin_functions[] = {
 294         NSP_PIN_FUNCTION(spi),
 295         NSP_PIN_FUNCTION(i2c),
 296         NSP_PIN_FUNCTION(mdio),
 297         NSP_PIN_FUNCTION(pwm),
 298         NSP_PIN_FUNCTION(gpio_b),
 299         NSP_PIN_FUNCTION(uart1),
 300         NSP_PIN_FUNCTION(uart2),
 301         NSP_PIN_FUNCTION(synce),
 302         NSP_PIN_FUNCTION(sata_led),
 303         NSP_PIN_FUNCTION(xtal_out),
 304         NSP_PIN_FUNCTION(sdio),
 305         NSP_PIN_FUNCTION(switch_led),
 306         NSP_PIN_FUNCTION(nand),
 307         NSP_PIN_FUNCTION(emmc)
 308 };
 309
 310 static int nsp_get_groups_count(struct pinctrl_dev *pctrl_dev)
 311 {
 312         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 313
 314         return pinctrl->num_groups;
 315 }
 316
 317 static const char *nsp_get_group_name(struct pinctrl_dev *pctrl_dev,
 318                                       unsigned int selector)
 319 {
 320         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 321
 322         return pinctrl->groups[selector].name;
 323 }
 324
 325 static int nsp_get_group_pins(struct pinctrl_dev *pctrl_dev,
 326                               unsigned int selector, const unsigned int **pins,
 327                               unsigned int *num_pins)
 328 {
 329         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 330
 331         *pins = pinctrl->groups[selector].pins;
 332         *num_pins = pinctrl->groups[selector].num_pins;
 333
 334         return 0;
 335 }
 336
 337 static void nsp_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
 338                              struct seq_file *s, unsigned int offset)
 339 {
 340         seq_printf(s, " %s", dev_name(pctrl_dev->dev));
 341 }
 342
 343 static const struct pinctrl_ops nsp_pinctrl_ops = {
 344         .get_groups_count = nsp_get_groups_count,
 345         .get_group_name = nsp_get_group_name,
 346         .get_group_pins = nsp_get_group_pins,
 347         .pin_dbg_show = nsp_pin_dbg_show,
 348         .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
 349         .dt_free_map = pinctrl_utils_free_map,
 350 };
 351
 352 static int nsp_get_functions_count(struct pinctrl_dev *pctrl_dev)
 353 {
 354         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 355
 356         return pinctrl->num_functions;
 357 }
 358
 359 static const char *nsp_get_function_name(struct pinctrl_dev *pctrl_dev,
 360                                          unsigned int selector)
 361 {
 362         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 363
 364         return pinctrl->functions[selector].name;
 365 }
 366
 367 static int nsp_get_function_groups(struct pinctrl_dev *pctrl_dev,
 368                                    unsigned int selector,
 369                                    const char * const **groups,
 370                                    unsigned * const num_groups)
 371 {
 372         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 373
 374         *groups = pinctrl->functions[selector].groups;
 375         *num_groups = pinctrl->functions[selector].num_groups;
 376
 377         return 0;
 378 }
 379
 380 static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl,
 381                           const struct nsp_pin_function *func,
 382                           const struct nsp_pin_group *grp,
 383                           struct nsp_mux_log *mux_log)
 384 {
 385         const struct nsp_mux *mux = &grp->mux;
 386         int i;
 387         u32 val, mask;
 388         unsigned long flags;
 389         void __iomem *base_address;
 390
 391         for (i = 0; i < pinctrl->num_groups; i++) {
 392                 if ((mux->shift != mux_log[i].mux.shift) ||
 393                         (mux->base != mux_log[i].mux.base))
 394                         continue;
 395
 396                 /* if this is a new configuration, just do it! */
 397                 if (!mux_log[i].is_configured)
 398                         break;
 399
 400                 /*
 401                  * IOMUX has been configured previously and one is trying to
 402                  * configure it to a different function
 403                  */
 404                 if (mux_log[i].mux.alt != mux->alt) {
 405                         dev_err(pinctrl->dev,
 406                                 "double configuration error detected!\n");
 407                         dev_err(pinctrl->dev, "func:%s grp:%s\n",
 408                                 func->name, grp->name);
 409                         return -EINVAL;
 410                 }
 411
 412                 return 0;
 413         }
 414         if (i == pinctrl->num_groups)
 415                 return -EINVAL;
 416
 417         mask = mux->mask;
 418         mux_log[i].mux.alt = mux->alt;
 419         mux_log[i].is_configured = true;
 420
 421         switch (mux->base) {
 422         case NSP_MUX_BASE0:
 423                 base_address = pinctrl->base0;
 424                 break;
 425
 426         case NSP_MUX_BASE1:
 427                 base_address = pinctrl->base1;
 428                 break;
 429
 430         case NSP_MUX_BASE2:
 431                 base_address = pinctrl->base2;
 432                 break;
 433
 434         default:
 435                 return -EINVAL;
 436         }
 437
 438         spin_lock_irqsave(&pinctrl->lock, flags);
 439         val = readl(base_address);
 440         val &= ~(mask << grp->mux.shift);
 441         val |= grp->mux.alt << grp->mux.shift;
 442         writel(val, base_address);
 443         spin_unlock_irqrestore(&pinctrl->lock, flags);
 444
 445         return 0;
 446 }
 447
 448 static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
 449                              unsigned int func_select, unsigned int grp_select)
 450 {
 451         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 452         const struct nsp_pin_function *func;
 453         const struct nsp_pin_group *grp;
 454
 455         if (grp_select >= pinctrl->num_groups ||
 456             func_select >= pinctrl->num_functions)
 457                 return -EINVAL;
 458
 459         func = &pinctrl->functions[func_select];
 460         grp = &pinctrl->groups[grp_select];
 461
 462         dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
 463                 func_select, func->name, grp_select, grp->name);
 464
 465         dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift,
 466                 grp->mux.alt);
 467
 468         return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
 469 }
 470
 471
 472 static int nsp_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
 473                                    struct pinctrl_gpio_range *range,
 474                                    unsigned int pin)
 475 {
 476         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 477         u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
 478         u32 val;
 479         unsigned long flags;
 480
 481         spin_lock_irqsave(&pinctrl->lock, flags);
 482         val = readl(pinctrl->base0);
 483         if ((val & BIT(pin)) != (*gpio_select << pin)) {
 484                 val &= ~BIT(pin);
 485                 val |= *gpio_select << pin;
 486                 writel(val, pinctrl->base0);
 487         }
 488         spin_unlock_irqrestore(&pinctrl->lock, flags);
 489
 490         return 0;
 491 }
 492
 493 static void nsp_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
 494                                   struct pinctrl_gpio_range *range,
 495                                   unsigned int pin)
 496 {
 497         struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 498         u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
 499         u32 val;
 500         unsigned long flags;
 501
 502         spin_lock_irqsave(&pinctrl->lock, flags);
 503         val = readl(pinctrl->base0);
 504         if ((val & (1 << pin)) == (*gpio_select << pin)) {
 505                 val &= ~(1 << pin);
 506                 if (!(*gpio_select))
 507                         val |= (1 << pin);
 508                 writel(val, pinctrl->base0);
 509         }
 510         spin_unlock_irqrestore(&pinctrl->lock, flags);
 511 }
 512
 513 static const struct pinmux_ops nsp_pinmux_ops = {
 514         .get_functions_count = nsp_get_functions_count,
 515         .get_function_name = nsp_get_function_name,
 516         .get_function_groups = nsp_get_function_groups,
 517         .set_mux = nsp_pinmux_enable,
 518         .gpio_request_enable = nsp_gpio_request_enable,
 519         .gpio_disable_free = nsp_gpio_disable_free,
 520 };
 521
 522 static struct pinctrl_desc nsp_pinctrl_desc = {
 523         .name = "nsp-pinmux",
 524         .pctlops = &nsp_pinctrl_ops,
 525         .pmxops = &nsp_pinmux_ops,
 526 };
 527
 528 static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)
 529 {
 530         struct nsp_mux_log *log;
 531         unsigned int i;
 532         u32 no_of_groups = ARRAY_SIZE(nsp_pin_groups);
 533
 534         pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups,
 535                                         sizeof(struct nsp_mux_log),
 536                                         GFP_KERNEL);
 537         if (!pinctrl->mux_log)
 538                 return -ENOMEM;
 539
 540         for (i = 0; i < no_of_groups; i++) {
 541                 log = &pinctrl->mux_log[i];
 542                 log->mux.base = nsp_pin_groups[i].mux.base;
 543                 log->mux.shift = nsp_pin_groups[i].mux.shift;
 544                 log->mux.alt = 0;
 545                 log->is_configured = false;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static int nsp_pinmux_probe(struct platform_device *pdev)
 552 {
 553         struct nsp_pinctrl *pinctrl;
 554         struct resource *res;
 555         int i, ret;
 556         struct pinctrl_pin_desc *pins;
 557         unsigned int num_pins = ARRAY_SIZE(nsp_pins);
 558
 559         pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
 560         if (!pinctrl)
 561                 return -ENOMEM;
 562         pinctrl->dev = &pdev->dev;
 563         platform_set_drvdata(pdev, pinctrl);
 564         spin_lock_init(&pinctrl->lock);
 565
 566         pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
 567         if (IS_ERR(pinctrl->base0))
 568                 return PTR_ERR(pinctrl->base0);
 569
 570         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 571         if (!res)
 572                 return -EINVAL;
 573         pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
 574                                               resource_size(res));
 575         if (!pinctrl->base1) {
 576                 dev_err(&pdev->dev, "unable to map I/O space\n");
 577                 return -ENOMEM;
 578         }
 579
 580         pinctrl->base2 = devm_platform_ioremap_resource(pdev, 2);
 581         if (IS_ERR(pinctrl->base2))
 582                 return PTR_ERR(pinctrl->base2);
 583
 584         ret = nsp_mux_log_init(pinctrl);
 585         if (ret) {
 586                 dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
 587                 return ret;
 588         }
 589
 590         pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
 591         if (!pins)
 592                 return -ENOMEM;
 593
 594         for (i = 0; i < num_pins; i++) {
 595                 pins[i].number = nsp_pins[i].pin;
 596                 pins[i].name = nsp_pins[i].name;
 597                 pins[i].drv_data = &nsp_pins[i].gpio_select;
 598         }
 599
 600         pinctrl->groups = nsp_pin_groups;
 601         pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups);
 602         pinctrl->functions = nsp_pin_functions;
 603         pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);
 604         nsp_pinctrl_desc.pins = pins;
 605         nsp_pinctrl_desc.npins = num_pins;
 606
 607         pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,
 608                                          pinctrl);
 609         if (IS_ERR(pinctrl->pctl)) {
 610                 dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n");
 611                 return PTR_ERR(pinctrl->pctl);
 612         }
 613
 614         return 0;
 615 }
 616
 617 static const struct of_device_id nsp_pinmux_of_match[] = {
 618         { .compatible = "brcm,nsp-pinmux" },
 619         { }
 620 };
 621
 622 static struct platform_driver nsp_pinmux_driver = {
 623         .driver = {
 624                 .name = "nsp-pinmux",
 625                 .of_match_table = nsp_pinmux_of_match,
 626         },
 627         .probe = nsp_pinmux_probe,
 628 };
 629
 630 static int __init nsp_pinmux_init(void)
 631 {
 632         return platform_driver_register(&nsp_pinmux_driver);
 633 }
 634 arch_initcall(nsp_pinmux_init);