2 * Copyright (C) 2014-2017 Broadcom
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
16 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
17 * pull up/down, slew and drive strength are also supported in this driver.
19 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
20 * through the interaction with the NSP IOMUX controller.
23 #include <linux/gpio/driver.h>
24 #include <linux/interrupt.h>
26 #include <linux/ioport.h>
27 #include <linux/kernel.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_irq.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/slab.h>
36 #include "../pinctrl-utils.h"
38 #define NSP_CHIP_A_INT_STATUS 0x00
39 #define NSP_CHIP_A_INT_MASK 0x04
40 #define NSP_GPIO_DATA_IN 0x40
41 #define NSP_GPIO_DATA_OUT 0x44
42 #define NSP_GPIO_OUT_EN 0x48
43 #define NSP_GPIO_INT_POLARITY 0x50
44 #define NSP_GPIO_INT_MASK 0x54
45 #define NSP_GPIO_EVENT 0x58
46 #define NSP_GPIO_EVENT_INT_MASK 0x5c
47 #define NSP_GPIO_EVENT_INT_POLARITY 0x64
48 #define NSP_CHIP_A_GPIO_INT_BIT 0x01
50 /* I/O parameters offset for chipcommon A GPIO */
51 #define NSP_GPIO_DRV_CTRL 0x00
52 #define NSP_GPIO_HYSTERESIS_EN 0x10
53 #define NSP_GPIO_SLEW_RATE_EN 0x14
54 #define NSP_PULL_UP_EN 0x18
55 #define NSP_PULL_DOWN_EN 0x1c
56 #define GPIO_DRV_STRENGTH_BITS 0x03
61 * @dev: pointer to device
62 * @base: I/O register base for nsp GPIO controller
63 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
65 * @pctl: pointer to pinctrl_dev
66 * @pctldesc: pinctrl descriptor
67 * @lock: lock to protect access to I/O registers
72 void __iomem *io_ctrl;
73 struct irq_chip irqchip;
75 struct pinctrl_dev *pctl;
76 struct pinctrl_desc pctldesc;
86 * Mapping from PINCONF pins to GPIO pins is 1-to-1
88 static inline unsigned nsp_pin_to_gpio(unsigned pin)
94 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
97 * @nsp_gpio: nsp GPIO device
98 * @base_type: reg base to modify
99 * @reg: register offset
103 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
104 unsigned int reg, unsigned gpio, bool set)
107 void __iomem *base_address;
109 if (address == IO_CTRL)
110 base_address = chip->io_ctrl;
112 base_address = chip->base;
114 val = readl(base_address + reg);
120 writel(val, base_address + reg);
124 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
127 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
128 unsigned int reg, unsigned gpio)
130 if (address == IO_CTRL)
131 return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
133 return !!(readl(chip->base + reg) & BIT(gpio));
136 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
138 struct gpio_chip *gc = (struct gpio_chip *)data;
139 struct nsp_gpio *chip = gpiochip_get_data(gc);
141 unsigned long int_bits = 0;
144 /* go through the entire GPIOs and handle all interrupts */
145 int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
146 if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
147 unsigned int event, level;
149 /* Get level and edge interrupts */
150 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
151 readl(chip->base + NSP_GPIO_EVENT);
152 level = readl(chip->base + NSP_GPIO_DATA_IN) ^
153 readl(chip->base + NSP_GPIO_INT_POLARITY);
154 level &= readl(chip->base + NSP_GPIO_INT_MASK);
155 int_bits = level | event;
157 for_each_set_bit(bit, &int_bits, gc->ngpio)
158 generic_handle_domain_irq(gc->irq.domain, bit);
161 return int_bits ? IRQ_HANDLED : IRQ_NONE;
164 static void nsp_gpio_irq_ack(struct irq_data *d)
166 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
167 struct nsp_gpio *chip = gpiochip_get_data(gc);
168 unsigned gpio = d->hwirq;
172 trigger_type = irq_get_trigger_type(d->irq);
173 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
174 writel(val, chip->base + NSP_GPIO_EVENT);
178 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
181 * @unmask: mask/unmask GPIO interrupt
183 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
185 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
186 struct nsp_gpio *chip = gpiochip_get_data(gc);
187 unsigned gpio = d->hwirq;
190 trigger_type = irq_get_trigger_type(d->irq);
191 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
192 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
194 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
197 static void nsp_gpio_irq_mask(struct irq_data *d)
199 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
200 struct nsp_gpio *chip = gpiochip_get_data(gc);
203 raw_spin_lock_irqsave(&chip->lock, flags);
204 nsp_gpio_irq_set_mask(d, false);
205 raw_spin_unlock_irqrestore(&chip->lock, flags);
208 static void nsp_gpio_irq_unmask(struct irq_data *d)
210 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
211 struct nsp_gpio *chip = gpiochip_get_data(gc);
214 raw_spin_lock_irqsave(&chip->lock, flags);
215 nsp_gpio_irq_set_mask(d, true);
216 raw_spin_unlock_irqrestore(&chip->lock, flags);
219 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
221 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
222 struct nsp_gpio *chip = gpiochip_get_data(gc);
223 unsigned gpio = d->hwirq;
228 raw_spin_lock_irqsave(&chip->lock, flags);
229 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
230 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
232 switch (type & IRQ_TYPE_SENSE_MASK) {
233 case IRQ_TYPE_EDGE_RISING:
237 case IRQ_TYPE_EDGE_FALLING:
241 case IRQ_TYPE_LEVEL_HIGH:
245 case IRQ_TYPE_LEVEL_LOW:
250 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
252 raw_spin_unlock_irqrestore(&chip->lock, flags);
256 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
257 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
259 if (type & IRQ_TYPE_EDGE_BOTH)
260 irq_set_handler_locked(d, handle_edge_irq);
262 irq_set_handler_locked(d, handle_level_irq);
264 raw_spin_unlock_irqrestore(&chip->lock, flags);
266 dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
267 level_low ? "true" : "false", falling ? "true" : "false");
271 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
273 struct nsp_gpio *chip = gpiochip_get_data(gc);
276 raw_spin_lock_irqsave(&chip->lock, flags);
277 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
278 raw_spin_unlock_irqrestore(&chip->lock, flags);
280 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
284 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
287 struct nsp_gpio *chip = gpiochip_get_data(gc);
290 raw_spin_lock_irqsave(&chip->lock, flags);
291 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
292 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
293 raw_spin_unlock_irqrestore(&chip->lock, flags);
295 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
299 static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
301 struct nsp_gpio *chip = gpiochip_get_data(gc);
305 raw_spin_lock_irqsave(&chip->lock, flags);
306 val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
307 raw_spin_unlock_irqrestore(&chip->lock, flags);
312 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
314 struct nsp_gpio *chip = gpiochip_get_data(gc);
317 raw_spin_lock_irqsave(&chip->lock, flags);
318 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
319 raw_spin_unlock_irqrestore(&chip->lock, flags);
321 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
324 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
326 struct nsp_gpio *chip = gpiochip_get_data(gc);
328 return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
331 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
337 * Only one group: "gpio_grp", since this local pinctrl device only performs
338 * GPIO specific PINCONF configurations
340 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
346 static const struct pinctrl_ops nsp_pctrl_ops = {
347 .get_groups_count = nsp_get_groups_count,
348 .get_group_name = nsp_get_group_name,
349 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
350 .dt_free_map = pinctrl_utils_free_map,
353 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
356 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
358 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
363 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
364 bool pull_up, bool pull_down)
368 raw_spin_lock_irqsave(&chip->lock, flags);
369 nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
370 nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
371 raw_spin_unlock_irqrestore(&chip->lock, flags);
373 dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
374 gpio, pull_up, pull_down);
378 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
379 bool *pull_up, bool *pull_down)
383 raw_spin_lock_irqsave(&chip->lock, flags);
384 *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
385 *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
386 raw_spin_unlock_irqrestore(&chip->lock, flags);
389 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
392 u32 offset, shift, i;
396 /* make sure drive strength is supported */
397 if (strength < 2 || strength > 16 || (strength % 2))
401 offset = NSP_GPIO_DRV_CTRL;
402 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
404 raw_spin_lock_irqsave(&chip->lock, flags);
405 strength = (strength / 2) - 1;
406 for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
407 val = readl(chip->io_ctrl + offset);
409 val |= ((strength >> (i-1)) & 0x1) << shift;
410 writel(val, chip->io_ctrl + offset);
413 raw_spin_unlock_irqrestore(&chip->lock, flags);
418 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
421 unsigned int offset, shift;
426 offset = NSP_GPIO_DRV_CTRL;
429 raw_spin_lock_irqsave(&chip->lock, flags);
431 for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
432 val = readl(chip->io_ctrl + offset) & BIT(shift);
434 *strength += (val << i);
439 *strength = (*strength + 1) * 2;
440 raw_spin_unlock_irqrestore(&chip->lock, flags);
445 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
447 unsigned long *config)
452 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
454 unsigned long *configs, unsigned num_configs)
459 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
460 unsigned long *config)
462 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
463 enum pin_config_param param = pinconf_to_config_param(*config);
466 bool pull_up, pull_down;
469 gpio = nsp_pin_to_gpio(pin);
471 case PIN_CONFIG_BIAS_DISABLE:
472 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
473 if ((pull_up == false) && (pull_down == false))
478 case PIN_CONFIG_BIAS_PULL_UP:
479 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
485 case PIN_CONFIG_BIAS_PULL_DOWN:
486 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
492 case PIN_CONFIG_DRIVE_STRENGTH:
493 ret = nsp_gpio_get_strength(chip, gpio, &arg);
496 *config = pinconf_to_config_packed(param, arg);
504 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
505 unsigned long *configs, unsigned num_configs)
507 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
508 enum pin_config_param param;
510 unsigned int i, gpio;
513 gpio = nsp_pin_to_gpio(pin);
514 for (i = 0; i < num_configs; i++) {
515 param = pinconf_to_config_param(configs[i]);
516 arg = pinconf_to_config_argument(configs[i]);
519 case PIN_CONFIG_BIAS_DISABLE:
520 ret = nsp_gpio_set_pull(chip, gpio, false, false);
525 case PIN_CONFIG_BIAS_PULL_UP:
526 ret = nsp_gpio_set_pull(chip, gpio, true, false);
531 case PIN_CONFIG_BIAS_PULL_DOWN:
532 ret = nsp_gpio_set_pull(chip, gpio, false, true);
537 case PIN_CONFIG_DRIVE_STRENGTH:
538 ret = nsp_gpio_set_strength(chip, gpio, arg);
543 case PIN_CONFIG_SLEW_RATE:
544 ret = nsp_gpio_set_slew(chip, gpio, arg);
550 dev_err(chip->dev, "invalid configuration\n");
559 static const struct pinconf_ops nsp_pconf_ops = {
561 .pin_config_get = nsp_pin_config_get,
562 .pin_config_set = nsp_pin_config_set,
563 .pin_config_group_get = nsp_pin_config_group_get,
564 .pin_config_group_set = nsp_pin_config_group_set,
568 * NSP GPIO controller supports some PINCONF related configurations such as
569 * pull up, pull down, slew and drive strength, when the pin is configured
572 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
575 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
577 struct pinctrl_desc *pctldesc = &chip->pctldesc;
578 struct pinctrl_pin_desc *pins;
579 struct gpio_chip *gc = &chip->gc;
582 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
585 for (i = 0; i < gc->ngpio; i++) {
587 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
592 pctldesc->name = dev_name(chip->dev);
593 pctldesc->pctlops = &nsp_pctrl_ops;
594 pctldesc->pins = pins;
595 pctldesc->npins = gc->ngpio;
596 pctldesc->confops = &nsp_pconf_ops;
598 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
599 if (IS_ERR(chip->pctl)) {
600 dev_err(chip->dev, "unable to register pinctrl device\n");
601 return PTR_ERR(chip->pctl);
607 static const struct of_device_id nsp_gpio_of_match[] = {
608 {.compatible = "brcm,nsp-gpio-a",},
612 static int nsp_gpio_probe(struct platform_device *pdev)
614 struct device *dev = &pdev->dev;
615 struct nsp_gpio *chip;
616 struct gpio_chip *gc;
620 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
621 dev_err(&pdev->dev, "Missing ngpios OF property\n");
625 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
630 platform_set_drvdata(pdev, chip);
632 chip->base = devm_platform_ioremap_resource(pdev, 0);
633 if (IS_ERR(chip->base)) {
634 dev_err(dev, "unable to map I/O memory\n");
635 return PTR_ERR(chip->base);
638 chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
639 if (IS_ERR(chip->io_ctrl)) {
640 dev_err(dev, "unable to map I/O memory\n");
641 return PTR_ERR(chip->io_ctrl);
644 raw_spin_lock_init(&chip->lock);
647 gc->can_sleep = false;
649 gc->label = dev_name(dev);
651 gc->of_node = dev->of_node;
652 gc->request = gpiochip_generic_request;
653 gc->free = gpiochip_generic_free;
654 gc->direction_input = nsp_gpio_direction_input;
655 gc->direction_output = nsp_gpio_direction_output;
656 gc->get_direction = nsp_gpio_get_direction;
657 gc->set = nsp_gpio_set;
658 gc->get = nsp_gpio_get;
660 /* optional GPIO interrupt support */
661 irq = platform_get_irq(pdev, 0);
663 struct gpio_irq_chip *girq;
664 struct irq_chip *irqc;
666 irqc = &chip->irqchip;
667 irqc->name = "gpio-a";
668 irqc->irq_ack = nsp_gpio_irq_ack;
669 irqc->irq_mask = nsp_gpio_irq_mask;
670 irqc->irq_unmask = nsp_gpio_irq_unmask;
671 irqc->irq_set_type = nsp_gpio_irq_set_type;
673 val = readl(chip->base + NSP_CHIP_A_INT_MASK);
674 val = val | NSP_CHIP_A_GPIO_INT_BIT;
675 writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
677 /* Install ISR for this GPIO controller. */
678 ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
679 IRQF_SHARED, "gpio-a", &chip->gc);
681 dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
686 girq = &chip->gc.irq;
688 /* This will let us handle the parent IRQ in the driver */
689 girq->parent_handler = NULL;
690 girq->num_parents = 0;
691 girq->parents = NULL;
692 girq->default_type = IRQ_TYPE_NONE;
693 girq->handler = handle_bad_irq;
696 ret = devm_gpiochip_add_data(dev, gc, chip);
698 dev_err(dev, "unable to add GPIO chip\n");
702 ret = nsp_gpio_register_pinconf(chip);
704 dev_err(dev, "unable to register pinconf\n");
711 static struct platform_driver nsp_gpio_driver = {
713 .name = "nsp-gpio-a",
714 .of_match_table = nsp_gpio_of_match,
716 .probe = nsp_gpio_probe,
719 static int __init nsp_gpio_init(void)
721 return platform_driver_register(&nsp_gpio_driver);
723 arch_initcall_sync(nsp_gpio_init);