2 * Copyright (C) 2014-2017 Broadcom
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
16 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
17 * pull up/down, slew and drive strength are also supported in this driver.
19 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
20 * through the interaction with the NSP IOMUX controller.
23 #include <linux/gpio/driver.h>
24 #include <linux/interrupt.h>
26 #include <linux/ioport.h>
27 #include <linux/kernel.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_irq.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/slab.h>
36 #include "../pinctrl-utils.h"
38 #define NSP_CHIP_A_INT_STATUS 0x00
39 #define NSP_CHIP_A_INT_MASK 0x04
40 #define NSP_GPIO_DATA_IN 0x40
41 #define NSP_GPIO_DATA_OUT 0x44
42 #define NSP_GPIO_OUT_EN 0x48
43 #define NSP_GPIO_INT_POLARITY 0x50
44 #define NSP_GPIO_INT_MASK 0x54
45 #define NSP_GPIO_EVENT 0x58
46 #define NSP_GPIO_EVENT_INT_MASK 0x5c
47 #define NSP_GPIO_EVENT_INT_POLARITY 0x64
48 #define NSP_CHIP_A_GPIO_INT_BIT 0x01
50 /* I/O parameters offset for chipcommon A GPIO */
51 #define NSP_GPIO_DRV_CTRL 0x00
52 #define NSP_GPIO_HYSTERESIS_EN 0x10
53 #define NSP_GPIO_SLEW_RATE_EN 0x14
54 #define NSP_PULL_UP_EN 0x18
55 #define NSP_PULL_DOWN_EN 0x1c
56 #define GPIO_DRV_STRENGTH_BITS 0x03
61 * @dev: pointer to device
62 * @base: I/O register base for nsp GPIO controller
63 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
65 * @pctl: pointer to pinctrl_dev
66 * @pctldesc: pinctrl descriptor
67 * @irq_domain: pointer to irq domain
68 * @lock: lock to protect access to I/O registers
73 void __iomem *io_ctrl;
75 struct pinctrl_dev *pctl;
76 struct pinctrl_desc pctldesc;
77 struct irq_domain *irq_domain;
87 * Mapping from PINCONF pins to GPIO pins is 1-to-1
89 static inline unsigned nsp_pin_to_gpio(unsigned pin)
95 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
98 * @nsp_gpio: nsp GPIO device
99 * @base_type: reg base to modify
100 * @reg: register offset
104 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
105 unsigned int reg, unsigned gpio, bool set)
108 void __iomem *base_address;
110 if (address == IO_CTRL)
111 base_address = chip->io_ctrl;
113 base_address = chip->base;
115 val = readl(base_address + reg);
121 writel(val, base_address + reg);
125 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
128 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
129 unsigned int reg, unsigned gpio)
131 if (address == IO_CTRL)
132 return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
134 return !!(readl(chip->base + reg) & BIT(gpio));
137 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
139 struct nsp_gpio *chip = (struct nsp_gpio *)data;
140 struct gpio_chip gc = chip->gc;
142 unsigned long int_bits = 0;
145 /* go through the entire GPIOs and handle all interrupts */
146 int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
147 if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
148 unsigned int event, level;
150 /* Get level and edge interrupts */
151 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
152 readl(chip->base + NSP_GPIO_EVENT);
153 level = readl(chip->base + NSP_GPIO_DATA_IN) ^
154 readl(chip->base + NSP_GPIO_INT_POLARITY);
155 level &= readl(chip->base + NSP_GPIO_INT_MASK);
156 int_bits = level | event;
158 for_each_set_bit(bit, &int_bits, gc.ngpio) {
160 * Clear the interrupt before invoking the
161 * handler, so we do not leave any window
163 writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
165 irq_linear_revmap(chip->irq_domain, bit));
169 return int_bits ? IRQ_HANDLED : IRQ_NONE;
172 static void nsp_gpio_irq_ack(struct irq_data *d)
174 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
175 unsigned gpio = d->hwirq;
179 trigger_type = irq_get_trigger_type(d->irq);
180 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
181 nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
185 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
188 * @unmask: mask/unmask GPIO interrupt
190 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
192 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
193 unsigned gpio = d->hwirq;
196 trigger_type = irq_get_trigger_type(d->irq);
197 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
198 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
200 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
203 static void nsp_gpio_irq_mask(struct irq_data *d)
205 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
208 raw_spin_lock_irqsave(&chip->lock, flags);
209 nsp_gpio_irq_set_mask(d, false);
210 raw_spin_unlock_irqrestore(&chip->lock, flags);
213 static void nsp_gpio_irq_unmask(struct irq_data *d)
215 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
218 raw_spin_lock_irqsave(&chip->lock, flags);
219 nsp_gpio_irq_set_mask(d, true);
220 raw_spin_unlock_irqrestore(&chip->lock, flags);
223 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
225 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
226 unsigned gpio = d->hwirq;
231 raw_spin_lock_irqsave(&chip->lock, flags);
232 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
233 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
235 switch (type & IRQ_TYPE_SENSE_MASK) {
236 case IRQ_TYPE_EDGE_RISING:
240 case IRQ_TYPE_EDGE_FALLING:
244 case IRQ_TYPE_LEVEL_HIGH:
248 case IRQ_TYPE_LEVEL_LOW:
253 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
255 raw_spin_unlock_irqrestore(&chip->lock, flags);
259 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
260 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
261 raw_spin_unlock_irqrestore(&chip->lock, flags);
263 dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
264 level_low ? "true" : "false", falling ? "true" : "false");
268 static struct irq_chip nsp_gpio_irq_chip = {
270 .irq_enable = nsp_gpio_irq_unmask,
271 .irq_disable = nsp_gpio_irq_mask,
272 .irq_ack = nsp_gpio_irq_ack,
273 .irq_mask = nsp_gpio_irq_mask,
274 .irq_unmask = nsp_gpio_irq_unmask,
275 .irq_set_type = nsp_gpio_irq_set_type,
279 * Request the nsp IOMUX pinmux controller to mux individual pins to GPIO
281 static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset)
283 unsigned gpio = gc->base + offset;
285 return pinctrl_request_gpio(gpio);
288 static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset)
290 unsigned gpio = gc->base + offset;
292 pinctrl_free_gpio(gpio);
295 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
297 struct nsp_gpio *chip = gpiochip_get_data(gc);
300 raw_spin_lock_irqsave(&chip->lock, flags);
301 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
302 raw_spin_unlock_irqrestore(&chip->lock, flags);
304 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
308 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
311 struct nsp_gpio *chip = gpiochip_get_data(gc);
314 raw_spin_lock_irqsave(&chip->lock, flags);
315 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
316 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
317 raw_spin_unlock_irqrestore(&chip->lock, flags);
319 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
323 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
325 struct nsp_gpio *chip = gpiochip_get_data(gc);
328 raw_spin_lock_irqsave(&chip->lock, flags);
329 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
330 raw_spin_unlock_irqrestore(&chip->lock, flags);
332 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
335 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
337 struct nsp_gpio *chip = gpiochip_get_data(gc);
339 return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
342 static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
344 struct nsp_gpio *chip = gpiochip_get_data(gc);
346 return irq_linear_revmap(chip->irq_domain, offset);
349 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
355 * Only one group: "gpio_grp", since this local pinctrl device only performs
356 * GPIO specific PINCONF configurations
358 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
364 static const struct pinctrl_ops nsp_pctrl_ops = {
365 .get_groups_count = nsp_get_groups_count,
366 .get_group_name = nsp_get_group_name,
367 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
368 .dt_free_map = pinctrl_utils_free_map,
371 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
374 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
376 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
381 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
382 bool pull_up, bool pull_down)
386 raw_spin_lock_irqsave(&chip->lock, flags);
387 nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
388 nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
389 raw_spin_unlock_irqrestore(&chip->lock, flags);
391 dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
392 gpio, pull_up, pull_down);
396 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
397 bool *pull_up, bool *pull_down)
401 raw_spin_lock_irqsave(&chip->lock, flags);
402 *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
403 *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
404 raw_spin_unlock_irqrestore(&chip->lock, flags);
407 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
410 u32 offset, shift, i;
414 /* make sure drive strength is supported */
415 if (strength < 2 || strength > 16 || (strength % 2))
419 offset = NSP_GPIO_DRV_CTRL;
420 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
422 raw_spin_lock_irqsave(&chip->lock, flags);
423 strength = (strength / 2) - 1;
424 for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
425 val = readl(chip->io_ctrl + offset);
427 val |= ((strength >> (i-1)) & 0x1) << shift;
428 writel(val, chip->io_ctrl + offset);
431 raw_spin_unlock_irqrestore(&chip->lock, flags);
436 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
439 unsigned int offset, shift;
444 offset = NSP_GPIO_DRV_CTRL;
447 raw_spin_lock_irqsave(&chip->lock, flags);
449 for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
450 val = readl(chip->io_ctrl + offset) & BIT(shift);
452 *strength += (val << i);
457 *strength = (*strength + 1) * 2;
458 raw_spin_unlock_irqrestore(&chip->lock, flags);
463 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
465 unsigned long *config)
470 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
472 unsigned long *configs, unsigned num_configs)
477 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
478 unsigned long *config)
480 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
481 enum pin_config_param param = pinconf_to_config_param(*config);
484 bool pull_up, pull_down;
487 gpio = nsp_pin_to_gpio(pin);
489 case PIN_CONFIG_BIAS_DISABLE:
490 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
491 if ((pull_up == false) && (pull_down == false))
496 case PIN_CONFIG_BIAS_PULL_UP:
497 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
503 case PIN_CONFIG_BIAS_PULL_DOWN:
504 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
510 case PIN_CONFIG_DRIVE_STRENGTH:
511 ret = nsp_gpio_get_strength(chip, gpio, &arg);
514 *config = pinconf_to_config_packed(param, arg);
522 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
523 unsigned long *configs, unsigned num_configs)
525 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
526 enum pin_config_param param;
528 unsigned int i, gpio;
531 gpio = nsp_pin_to_gpio(pin);
532 for (i = 0; i < num_configs; i++) {
533 param = pinconf_to_config_param(configs[i]);
534 arg = pinconf_to_config_argument(configs[i]);
537 case PIN_CONFIG_BIAS_DISABLE:
538 ret = nsp_gpio_set_pull(chip, gpio, false, false);
543 case PIN_CONFIG_BIAS_PULL_UP:
544 ret = nsp_gpio_set_pull(chip, gpio, true, false);
549 case PIN_CONFIG_BIAS_PULL_DOWN:
550 ret = nsp_gpio_set_pull(chip, gpio, false, true);
555 case PIN_CONFIG_DRIVE_STRENGTH:
556 ret = nsp_gpio_set_strength(chip, gpio, arg);
561 case PIN_CONFIG_SLEW_RATE:
562 ret = nsp_gpio_set_slew(chip, gpio, arg);
568 dev_err(chip->dev, "invalid configuration\n");
577 static const struct pinconf_ops nsp_pconf_ops = {
579 .pin_config_get = nsp_pin_config_get,
580 .pin_config_set = nsp_pin_config_set,
581 .pin_config_group_get = nsp_pin_config_group_get,
582 .pin_config_group_set = nsp_pin_config_group_set,
586 * NSP GPIO controller supports some PINCONF related configurations such as
587 * pull up, pull down, slew and drive strength, when the pin is configured
590 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
593 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
595 struct pinctrl_desc *pctldesc = &chip->pctldesc;
596 struct pinctrl_pin_desc *pins;
597 struct gpio_chip *gc = &chip->gc;
600 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
603 for (i = 0; i < gc->ngpio; i++) {
605 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
610 pctldesc->name = dev_name(chip->dev);
611 pctldesc->pctlops = &nsp_pctrl_ops;
612 pctldesc->pins = pins;
613 pctldesc->npins = gc->ngpio;
614 pctldesc->confops = &nsp_pconf_ops;
616 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
617 if (IS_ERR(chip->pctl)) {
618 dev_err(chip->dev, "unable to register pinctrl device\n");
619 return PTR_ERR(chip->pctl);
625 static const struct of_device_id nsp_gpio_of_match[] = {
626 {.compatible = "brcm,nsp-gpio-a",},
630 static int nsp_gpio_probe(struct platform_device *pdev)
632 struct device *dev = &pdev->dev;
633 struct resource *res;
634 struct nsp_gpio *chip;
635 struct gpio_chip *gc;
639 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
640 dev_err(&pdev->dev, "Missing ngpios OF property\n");
644 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
649 platform_set_drvdata(pdev, chip);
651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 chip->base = devm_ioremap_resource(dev, res);
653 if (IS_ERR(chip->base)) {
654 dev_err(dev, "unable to map I/O memory\n");
655 return PTR_ERR(chip->base);
658 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
659 chip->io_ctrl = devm_ioremap_resource(dev, res);
660 if (IS_ERR(chip->io_ctrl)) {
661 dev_err(dev, "unable to map I/O memory\n");
662 return PTR_ERR(chip->io_ctrl);
665 raw_spin_lock_init(&chip->lock);
668 gc->can_sleep = false;
670 gc->label = dev_name(dev);
672 gc->of_node = dev->of_node;
673 gc->request = nsp_gpio_request;
674 gc->free = nsp_gpio_free;
675 gc->direction_input = nsp_gpio_direction_input;
676 gc->direction_output = nsp_gpio_direction_output;
677 gc->set = nsp_gpio_set;
678 gc->get = nsp_gpio_get;
679 gc->to_irq = nsp_gpio_to_irq;
681 /* optional GPIO interrupt support */
682 irq = platform_get_irq(pdev, 0);
684 /* Create irq domain so that each pin can be assigned an IRQ.*/
685 chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio,
686 &irq_domain_simple_ops,
688 if (!chip->irq_domain) {
689 dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n");
693 /* Map each gpio to an IRQ and set the handler for gpiolib. */
694 for (count = 0; count < gc->ngpio; count++) {
695 int irq = irq_create_mapping(chip->irq_domain, count);
697 irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
699 irq_set_chip_data(irq, chip);
702 /* Install ISR for this GPIO controller. */
703 ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
704 IRQF_SHARED, "gpio-a", chip);
706 dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
708 goto err_rm_gpiochip;
711 val = readl(chip->base + NSP_CHIP_A_INT_MASK);
712 val = val | NSP_CHIP_A_GPIO_INT_BIT;
713 writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
716 ret = gpiochip_add_data(gc, chip);
718 dev_err(dev, "unable to add GPIO chip\n");
722 ret = nsp_gpio_register_pinconf(chip);
724 dev_err(dev, "unable to register pinconf\n");
725 goto err_rm_gpiochip;
736 static struct platform_driver nsp_gpio_driver = {
738 .name = "nsp-gpio-a",
739 .of_match_table = nsp_gpio_of_match,
741 .probe = nsp_gpio_probe,
744 static int __init nsp_gpio_init(void)
746 return platform_driver_register(&nsp_gpio_driver);
748 arch_initcall_sync(nsp_gpio_init);