1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for BCM63268 GPIO unit (pinctrl + GPIO)
5 * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
9 #include <linux/bits.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/kernel.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
17 #include "../pinctrl-utils.h"
19 #include "pinctrl-bcm63xx.h"
21 #define BCM63268_NUM_GPIOS 52
22 #define BCM63268_NUM_LEDS 24
24 #define BCM63268_LED_REG 0x10
25 #define BCM63268_MODE_REG 0x18
26 #define BCM63268_CTRL_REG 0x1c
27 #define BCM63268_BASEMODE_REG 0x38
28 #define BCM63268_BASEMODE_NAND BIT(2) /* GPIOs 2-7, 24-31 */
29 #define BCM63268_BASEMODE_GPIO35 BIT(4) /* GPIO 35 */
30 #define BCM63268_BASEMODE_DECTPD BIT(5) /* GPIOs 8/9 */
31 #define BCM63268_BASEMODE_VDSL_PHY_0 BIT(6) /* GPIOs 10/11 */
32 #define BCM63268_BASEMODE_VDSL_PHY_1 BIT(7) /* GPIOs 12/13 */
33 #define BCM63268_BASEMODE_VDSL_PHY_2 BIT(8) /* GPIOs 24/25 */
34 #define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9) /* GPIOs 26/27 */
36 enum bcm63268_pinctrl_reg {
43 struct bcm63268_pingroup {
45 const unsigned * const pins;
46 const unsigned num_pins;
49 struct bcm63268_function {
51 const char * const *groups;
52 const unsigned num_groups;
54 enum bcm63268_pinctrl_reg reg;
58 #define BCM63268_PIN(a, b, basemode) \
62 .drv_data = (void *)(basemode) \
65 static const struct pinctrl_pin_desc bcm63268_pins[] = {
66 PINCTRL_PIN(0, "gpio0"),
67 PINCTRL_PIN(1, "gpio1"),
68 BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND),
69 BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND),
70 BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND),
71 BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND),
72 BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND),
73 BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND),
74 BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD),
75 BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD),
76 BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0),
77 BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0),
78 BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1),
79 BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1),
80 PINCTRL_PIN(14, "gpio14"),
81 PINCTRL_PIN(15, "gpio15"),
82 PINCTRL_PIN(16, "gpio16"),
83 PINCTRL_PIN(17, "gpio17"),
84 PINCTRL_PIN(18, "gpio18"),
85 PINCTRL_PIN(19, "gpio19"),
86 PINCTRL_PIN(20, "gpio20"),
87 PINCTRL_PIN(21, "gpio21"),
88 PINCTRL_PIN(22, "gpio22"),
89 PINCTRL_PIN(23, "gpio23"),
90 BCM63268_PIN(24, "gpio24",
91 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
92 BCM63268_PIN(25, "gpio25",
93 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
94 BCM63268_PIN(26, "gpio26",
95 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
96 BCM63268_PIN(27, "gpio27",
97 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
98 BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND),
99 BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND),
100 BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND),
101 BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND),
102 PINCTRL_PIN(32, "gpio32"),
103 PINCTRL_PIN(33, "gpio33"),
104 PINCTRL_PIN(34, "gpio34"),
105 PINCTRL_PIN(35, "gpio35"),
106 PINCTRL_PIN(36, "gpio36"),
107 PINCTRL_PIN(37, "gpio37"),
108 PINCTRL_PIN(38, "gpio38"),
109 PINCTRL_PIN(39, "gpio39"),
110 PINCTRL_PIN(40, "gpio40"),
111 PINCTRL_PIN(41, "gpio41"),
112 PINCTRL_PIN(42, "gpio42"),
113 PINCTRL_PIN(43, "gpio43"),
114 PINCTRL_PIN(44, "gpio44"),
115 PINCTRL_PIN(45, "gpio45"),
116 PINCTRL_PIN(46, "gpio46"),
117 PINCTRL_PIN(47, "gpio47"),
118 PINCTRL_PIN(48, "gpio48"),
119 PINCTRL_PIN(49, "gpio49"),
120 PINCTRL_PIN(50, "gpio50"),
121 PINCTRL_PIN(51, "gpio51"),
124 static unsigned gpio0_pins[] = { 0 };
125 static unsigned gpio1_pins[] = { 1 };
126 static unsigned gpio2_pins[] = { 2 };
127 static unsigned gpio3_pins[] = { 3 };
128 static unsigned gpio4_pins[] = { 4 };
129 static unsigned gpio5_pins[] = { 5 };
130 static unsigned gpio6_pins[] = { 6 };
131 static unsigned gpio7_pins[] = { 7 };
132 static unsigned gpio8_pins[] = { 8 };
133 static unsigned gpio9_pins[] = { 9 };
134 static unsigned gpio10_pins[] = { 10 };
135 static unsigned gpio11_pins[] = { 11 };
136 static unsigned gpio12_pins[] = { 12 };
137 static unsigned gpio13_pins[] = { 13 };
138 static unsigned gpio14_pins[] = { 14 };
139 static unsigned gpio15_pins[] = { 15 };
140 static unsigned gpio16_pins[] = { 16 };
141 static unsigned gpio17_pins[] = { 17 };
142 static unsigned gpio18_pins[] = { 18 };
143 static unsigned gpio19_pins[] = { 19 };
144 static unsigned gpio20_pins[] = { 20 };
145 static unsigned gpio21_pins[] = { 21 };
146 static unsigned gpio22_pins[] = { 22 };
147 static unsigned gpio23_pins[] = { 23 };
148 static unsigned gpio24_pins[] = { 24 };
149 static unsigned gpio25_pins[] = { 25 };
150 static unsigned gpio26_pins[] = { 26 };
151 static unsigned gpio27_pins[] = { 27 };
152 static unsigned gpio28_pins[] = { 28 };
153 static unsigned gpio29_pins[] = { 29 };
154 static unsigned gpio30_pins[] = { 30 };
155 static unsigned gpio31_pins[] = { 31 };
156 static unsigned gpio32_pins[] = { 32 };
157 static unsigned gpio33_pins[] = { 33 };
158 static unsigned gpio34_pins[] = { 34 };
159 static unsigned gpio35_pins[] = { 35 };
160 static unsigned gpio36_pins[] = { 36 };
161 static unsigned gpio37_pins[] = { 37 };
162 static unsigned gpio38_pins[] = { 38 };
163 static unsigned gpio39_pins[] = { 39 };
164 static unsigned gpio40_pins[] = { 40 };
165 static unsigned gpio41_pins[] = { 41 };
166 static unsigned gpio42_pins[] = { 42 };
167 static unsigned gpio43_pins[] = { 43 };
168 static unsigned gpio44_pins[] = { 44 };
169 static unsigned gpio45_pins[] = { 45 };
170 static unsigned gpio46_pins[] = { 46 };
171 static unsigned gpio47_pins[] = { 47 };
172 static unsigned gpio48_pins[] = { 48 };
173 static unsigned gpio49_pins[] = { 49 };
174 static unsigned gpio50_pins[] = { 50 };
175 static unsigned gpio51_pins[] = { 51 };
177 static unsigned nand_grp_pins[] = {
178 2, 3, 4, 5, 6, 7, 24,
179 25, 26, 27, 28, 29, 30, 31,
182 static unsigned dectpd_grp_pins[] = { 8, 9 };
183 static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };
184 static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
185 static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
186 static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
188 #define BCM63268_GROUP(n) \
192 .num_pins = ARRAY_SIZE(n##_pins), \
195 static struct bcm63268_pingroup bcm63268_groups[] = {
196 BCM63268_GROUP(gpio0),
197 BCM63268_GROUP(gpio1),
198 BCM63268_GROUP(gpio2),
199 BCM63268_GROUP(gpio3),
200 BCM63268_GROUP(gpio4),
201 BCM63268_GROUP(gpio5),
202 BCM63268_GROUP(gpio6),
203 BCM63268_GROUP(gpio7),
204 BCM63268_GROUP(gpio8),
205 BCM63268_GROUP(gpio9),
206 BCM63268_GROUP(gpio10),
207 BCM63268_GROUP(gpio11),
208 BCM63268_GROUP(gpio12),
209 BCM63268_GROUP(gpio13),
210 BCM63268_GROUP(gpio14),
211 BCM63268_GROUP(gpio15),
212 BCM63268_GROUP(gpio16),
213 BCM63268_GROUP(gpio17),
214 BCM63268_GROUP(gpio18),
215 BCM63268_GROUP(gpio19),
216 BCM63268_GROUP(gpio20),
217 BCM63268_GROUP(gpio21),
218 BCM63268_GROUP(gpio22),
219 BCM63268_GROUP(gpio23),
220 BCM63268_GROUP(gpio24),
221 BCM63268_GROUP(gpio25),
222 BCM63268_GROUP(gpio26),
223 BCM63268_GROUP(gpio27),
224 BCM63268_GROUP(gpio28),
225 BCM63268_GROUP(gpio29),
226 BCM63268_GROUP(gpio30),
227 BCM63268_GROUP(gpio31),
228 BCM63268_GROUP(gpio32),
229 BCM63268_GROUP(gpio33),
230 BCM63268_GROUP(gpio34),
231 BCM63268_GROUP(gpio35),
232 BCM63268_GROUP(gpio36),
233 BCM63268_GROUP(gpio37),
234 BCM63268_GROUP(gpio38),
235 BCM63268_GROUP(gpio39),
236 BCM63268_GROUP(gpio40),
237 BCM63268_GROUP(gpio41),
238 BCM63268_GROUP(gpio42),
239 BCM63268_GROUP(gpio43),
240 BCM63268_GROUP(gpio44),
241 BCM63268_GROUP(gpio45),
242 BCM63268_GROUP(gpio46),
243 BCM63268_GROUP(gpio47),
244 BCM63268_GROUP(gpio48),
245 BCM63268_GROUP(gpio49),
246 BCM63268_GROUP(gpio50),
247 BCM63268_GROUP(gpio51),
249 /* multi pin groups */
250 BCM63268_GROUP(nand_grp),
251 BCM63268_GROUP(dectpd_grp),
252 BCM63268_GROUP(vdsl_phy0_grp),
253 BCM63268_GROUP(vdsl_phy1_grp),
254 BCM63268_GROUP(vdsl_phy2_grp),
255 BCM63268_GROUP(vdsl_phy3_grp),
258 static const char * const led_groups[] = {
285 static const char * const serial_led_clk_groups[] = {
289 static const char * const serial_led_data_groups[] = {
293 static const char * const hsspi_cs4_groups[] = {
297 static const char * const hsspi_cs5_groups[] = {
301 static const char * const hsspi_cs6_groups[] = {
305 static const char * const hsspi_cs7_groups[] = {
309 static const char * const uart1_scts_groups[] = {
314 static const char * const uart1_srts_groups[] = {
319 static const char * const uart1_sdin_groups[] = {
324 static const char * const uart1_sdout_groups[] = {
329 static const char * const ntr_pulse_in_groups[] = {
334 static const char * const dsl_ntr_pulse_out_groups[] = {
339 static const char * const adsl_spi_miso_groups[] = {
343 static const char * const adsl_spi_mosi_groups[] = {
347 static const char * const vreg_clk_groups[] = {
351 static const char * const pcie_clkreq_b_groups[] = {
355 static const char * const switch_led_clk_groups[] = {
359 static const char * const switch_led_data_groups[] = {
363 static const char * const wifi_groups[] = {
386 static const char * const nand_groups[] = {
390 static const char * const dectpd_groups[] = {
394 static const char * const vdsl_phy_override_0_groups[] = {
395 "vdsl_phy_override_0_grp",
398 static const char * const vdsl_phy_override_1_groups[] = {
399 "vdsl_phy_override_1_grp",
402 static const char * const vdsl_phy_override_2_groups[] = {
403 "vdsl_phy_override_2_grp",
406 static const char * const vdsl_phy_override_3_groups[] = {
407 "vdsl_phy_override_3_grp",
410 #define BCM63268_LED_FUN(n) \
413 .groups = n##_groups, \
414 .num_groups = ARRAY_SIZE(n##_groups), \
415 .reg = BCM63268_LEDCTRL, \
418 #define BCM63268_MODE_FUN(n) \
421 .groups = n##_groups, \
422 .num_groups = ARRAY_SIZE(n##_groups), \
423 .reg = BCM63268_MODE, \
426 #define BCM63268_CTRL_FUN(n) \
429 .groups = n##_groups, \
430 .num_groups = ARRAY_SIZE(n##_groups), \
431 .reg = BCM63268_CTRL, \
434 #define BCM63268_BASEMODE_FUN(n, val) \
437 .groups = n##_groups, \
438 .num_groups = ARRAY_SIZE(n##_groups), \
439 .reg = BCM63268_BASEMODE, \
443 static const struct bcm63268_function bcm63268_funcs[] = {
444 BCM63268_LED_FUN(led),
445 BCM63268_MODE_FUN(serial_led_clk),
446 BCM63268_MODE_FUN(serial_led_data),
447 BCM63268_MODE_FUN(hsspi_cs6),
448 BCM63268_MODE_FUN(hsspi_cs7),
449 BCM63268_MODE_FUN(uart1_scts),
450 BCM63268_MODE_FUN(uart1_srts),
451 BCM63268_MODE_FUN(uart1_sdin),
452 BCM63268_MODE_FUN(uart1_sdout),
453 BCM63268_MODE_FUN(ntr_pulse_in),
454 BCM63268_MODE_FUN(dsl_ntr_pulse_out),
455 BCM63268_MODE_FUN(hsspi_cs4),
456 BCM63268_MODE_FUN(hsspi_cs5),
457 BCM63268_MODE_FUN(adsl_spi_miso),
458 BCM63268_MODE_FUN(adsl_spi_mosi),
459 BCM63268_MODE_FUN(vreg_clk),
460 BCM63268_MODE_FUN(pcie_clkreq_b),
461 BCM63268_MODE_FUN(switch_led_clk),
462 BCM63268_MODE_FUN(switch_led_data),
463 BCM63268_CTRL_FUN(wifi),
464 BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND),
465 BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD),
466 BCM63268_BASEMODE_FUN(vdsl_phy_override_0,
467 BCM63268_BASEMODE_VDSL_PHY_0),
468 BCM63268_BASEMODE_FUN(vdsl_phy_override_1,
469 BCM63268_BASEMODE_VDSL_PHY_1),
470 BCM63268_BASEMODE_FUN(vdsl_phy_override_2,
471 BCM63268_BASEMODE_VDSL_PHY_2),
472 BCM63268_BASEMODE_FUN(vdsl_phy_override_3,
473 BCM63268_BASEMODE_VDSL_PHY_3),
476 static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
478 return ARRAY_SIZE(bcm63268_groups);
481 static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
484 return bcm63268_groups[group].name;
487 static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
489 const unsigned **pins,
492 *pins = bcm63268_groups[group].pins;
493 *num_pins = bcm63268_groups[group].num_pins;
498 static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
500 return ARRAY_SIZE(bcm63268_funcs);
503 static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
506 return bcm63268_funcs[selector].name;
509 static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,
511 const char * const **groups,
512 unsigned * const num_groups)
514 *groups = bcm63268_funcs[selector].groups;
515 *num_groups = bcm63268_funcs[selector].num_groups;
520 static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)
522 const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];
523 unsigned int basemode = (unsigned long) desc->drv_data;
524 unsigned int mask = BIT(bcm63xx_bank_pin(pin));
527 regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode,
530 if (pin < BCM63XX_BANK_GPIOS) {
531 /* base mode: 0 => gpio, 1 => mux function */
532 regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0);
534 /* pins 0-23 might be muxed to led */
535 if (pin < BCM63268_NUM_LEDS)
536 regmap_update_bits(pc->regs, BCM63268_LED_REG, mask,
538 } else if (pin < BCM63268_NUM_GPIOS) {
539 /* ctrl reg: 0 => wifi function, 1 => gpio */
540 regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask);
544 static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
545 unsigned selector, unsigned group)
547 struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
548 const struct bcm63268_pingroup *pg = &bcm63268_groups[group];
549 const struct bcm63268_function *f = &bcm63268_funcs[selector];
552 unsigned int val, mask;
554 for (i = 0; i < pg->num_pins; i++)
555 bcm63268_set_gpio(pc, pg->pins[i]);
558 case BCM63268_LEDCTRL:
559 reg = BCM63268_LED_REG;
560 mask = BIT(pg->pins[0]);
561 val = BIT(pg->pins[0]);
564 reg = BCM63268_MODE_REG;
565 mask = BIT(pg->pins[0]);
566 val = BIT(pg->pins[0]);
569 reg = BCM63268_CTRL_REG;
570 mask = BIT(pg->pins[0]);
573 case BCM63268_BASEMODE:
574 reg = BCM63268_BASEMODE_REG;
583 regmap_update_bits(pc->regs, reg, mask, val);
588 static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,
589 struct pinctrl_gpio_range *range,
592 struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
594 /* disable all functions using this pin */
595 bcm63268_set_gpio(pc, offset);
600 static const struct pinctrl_ops bcm63268_pctl_ops = {
601 .dt_free_map = pinctrl_utils_free_map,
602 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
603 .get_group_name = bcm63268_pinctrl_get_group_name,
604 .get_group_pins = bcm63268_pinctrl_get_group_pins,
605 .get_groups_count = bcm63268_pinctrl_get_group_count,
608 static const struct pinmux_ops bcm63268_pmx_ops = {
609 .get_function_groups = bcm63268_pinctrl_get_groups,
610 .get_function_name = bcm63268_pinctrl_get_func_name,
611 .get_functions_count = bcm63268_pinctrl_get_func_count,
612 .gpio_request_enable = bcm63268_gpio_request_enable,
613 .set_mux = bcm63268_pinctrl_set_mux,
617 static const struct bcm63xx_pinctrl_soc bcm63268_soc = {
618 .ngpios = BCM63268_NUM_GPIOS,
619 .npins = ARRAY_SIZE(bcm63268_pins),
620 .pctl_ops = &bcm63268_pctl_ops,
621 .pins = bcm63268_pins,
622 .pmx_ops = &bcm63268_pmx_ops,
625 static int bcm63268_pinctrl_probe(struct platform_device *pdev)
627 return bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL);
630 static const struct of_device_id bcm63268_pinctrl_match[] = {
631 { .compatible = "brcm,bcm63268-pinctrl", },
635 static struct platform_driver bcm63268_pinctrl_driver = {
636 .probe = bcm63268_pinctrl_probe,
638 .name = "bcm63268-pinctrl",
639 .of_match_table = bcm63268_pinctrl_match,
643 builtin_platform_driver(bcm63268_pinctrl_driver);