1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/types.h>
37 #include <dt-bindings/pinctrl/bcm2835.h>
39 #define MODULE_NAME "pinctrl-bcm2835"
40 #define BCM2835_NUM_GPIOS 54
41 #define BCM2711_NUM_GPIOS 58
42 #define BCM2835_NUM_BANKS 2
43 #define BCM2835_NUM_IRQS 3
45 /* GPIO register offsets */
46 #define GPFSEL0 0x0 /* Function Select */
47 #define GPSET0 0x1c /* Pin Output Set */
48 #define GPCLR0 0x28 /* Pin Output Clear */
49 #define GPLEV0 0x34 /* Pin Level */
50 #define GPEDS0 0x40 /* Pin Event Detect Status */
51 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
52 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
53 #define GPHEN0 0x64 /* Pin High Detect Enable */
54 #define GPLEN0 0x70 /* Pin Low Detect Enable */
55 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
56 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
57 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
58 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
59 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
61 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p) (((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p) ((p) / 32)
64 #define GPIO_REG_SHIFT(p) ((p) % 32)
66 #define PUD_2711_MASK 0x3
67 #define PUD_2711_REG_OFFSET(p) ((p) / 16)
68 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
70 /* argument: bcm2835_pinconf_pull */
71 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
73 #define BCM2711_PULL_NONE 0x0
74 #define BCM2711_PULL_UP 0x1
75 #define BCM2711_PULL_DOWN 0x2
77 struct bcm2835_pinctrl {
82 /* note: locking assumes each bank will have its own unsigned long */
83 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
84 unsigned int irq_type[BCM2711_NUM_GPIOS];
86 struct pinctrl_dev *pctl_dev;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_desc pctl_desc;
89 struct pinctrl_gpio_range gpio_range;
91 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
94 /* pins are just named GPIO0..GPIO53 */
95 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
96 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
107 BCM2835_GPIO_PIN(10),
108 BCM2835_GPIO_PIN(11),
109 BCM2835_GPIO_PIN(12),
110 BCM2835_GPIO_PIN(13),
111 BCM2835_GPIO_PIN(14),
112 BCM2835_GPIO_PIN(15),
113 BCM2835_GPIO_PIN(16),
114 BCM2835_GPIO_PIN(17),
115 BCM2835_GPIO_PIN(18),
116 BCM2835_GPIO_PIN(19),
117 BCM2835_GPIO_PIN(20),
118 BCM2835_GPIO_PIN(21),
119 BCM2835_GPIO_PIN(22),
120 BCM2835_GPIO_PIN(23),
121 BCM2835_GPIO_PIN(24),
122 BCM2835_GPIO_PIN(25),
123 BCM2835_GPIO_PIN(26),
124 BCM2835_GPIO_PIN(27),
125 BCM2835_GPIO_PIN(28),
126 BCM2835_GPIO_PIN(29),
127 BCM2835_GPIO_PIN(30),
128 BCM2835_GPIO_PIN(31),
129 BCM2835_GPIO_PIN(32),
130 BCM2835_GPIO_PIN(33),
131 BCM2835_GPIO_PIN(34),
132 BCM2835_GPIO_PIN(35),
133 BCM2835_GPIO_PIN(36),
134 BCM2835_GPIO_PIN(37),
135 BCM2835_GPIO_PIN(38),
136 BCM2835_GPIO_PIN(39),
137 BCM2835_GPIO_PIN(40),
138 BCM2835_GPIO_PIN(41),
139 BCM2835_GPIO_PIN(42),
140 BCM2835_GPIO_PIN(43),
141 BCM2835_GPIO_PIN(44),
142 BCM2835_GPIO_PIN(45),
143 BCM2835_GPIO_PIN(46),
144 BCM2835_GPIO_PIN(47),
145 BCM2835_GPIO_PIN(48),
146 BCM2835_GPIO_PIN(49),
147 BCM2835_GPIO_PIN(50),
148 BCM2835_GPIO_PIN(51),
149 BCM2835_GPIO_PIN(52),
150 BCM2835_GPIO_PIN(53),
151 BCM2835_GPIO_PIN(54),
152 BCM2835_GPIO_PIN(55),
153 BCM2835_GPIO_PIN(56),
154 BCM2835_GPIO_PIN(57),
157 /* one pin per group */
158 static const char * const bcm2835_gpio_groups[] = {
220 BCM2835_FSEL_COUNT = 8,
221 BCM2835_FSEL_MASK = 0x7,
224 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
225 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
226 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
227 [BCM2835_FSEL_ALT0] = "alt0",
228 [BCM2835_FSEL_ALT1] = "alt1",
229 [BCM2835_FSEL_ALT2] = "alt2",
230 [BCM2835_FSEL_ALT3] = "alt3",
231 [BCM2835_FSEL_ALT4] = "alt4",
232 [BCM2835_FSEL_ALT5] = "alt5",
235 static const char * const irq_type_names[] = {
236 [IRQ_TYPE_NONE] = "none",
237 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
238 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
239 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
240 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
241 [IRQ_TYPE_LEVEL_LOW] = "level-low",
244 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
246 return readl(pc->base + reg);
249 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
252 writel(val, pc->base + reg);
255 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
258 reg += GPIO_REG_OFFSET(bit) * 4;
259 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
262 /* note NOT a read/modify/write cycle */
263 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
264 unsigned reg, unsigned bit)
266 reg += GPIO_REG_OFFSET(bit) * 4;
267 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
270 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
271 struct bcm2835_pinctrl *pc, unsigned pin)
273 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
274 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
276 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
277 bcm2835_functions[status]);
282 static inline void bcm2835_pinctrl_fsel_set(
283 struct bcm2835_pinctrl *pc, unsigned pin,
284 enum bcm2835_fsel fsel)
286 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
287 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
289 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
290 bcm2835_functions[cur]);
295 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
296 /* always transition through GPIO_IN */
297 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
298 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
300 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
301 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
302 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
305 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
306 val |= fsel << FSEL_SHIFT(pin);
308 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
309 bcm2835_functions[fsel]);
310 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
313 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
315 return pinctrl_gpio_direction_input(chip->base + offset);
318 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
320 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
322 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
325 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
327 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
330 /* Alternative function doesn't clearly provide a direction */
331 if (fsel > BCM2835_FSEL_GPIO_OUT)
334 if (fsel == BCM2835_FSEL_GPIO_IN)
335 return GPIO_LINE_DIRECTION_IN;
337 return GPIO_LINE_DIRECTION_OUT;
340 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
342 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
344 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
347 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
348 unsigned offset, int value)
350 bcm2835_gpio_set(chip, offset, value);
351 return pinctrl_gpio_direction_output(chip->base + offset);
354 static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
355 struct device_node *np)
357 struct pinctrl_dev *pctldev = of_pinctrl_get(np);
364 gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
370 static const struct gpio_chip bcm2835_gpio_chip = {
371 .label = MODULE_NAME,
372 .owner = THIS_MODULE,
373 .request = gpiochip_generic_request,
374 .free = gpiochip_generic_free,
375 .direction_input = bcm2835_gpio_direction_input,
376 .direction_output = bcm2835_gpio_direction_output,
377 .get_direction = bcm2835_gpio_get_direction,
378 .get = bcm2835_gpio_get,
379 .set = bcm2835_gpio_set,
380 .set_config = gpiochip_generic_config,
382 .ngpio = BCM2835_NUM_GPIOS,
384 .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
387 static const struct gpio_chip bcm2711_gpio_chip = {
388 .label = "pinctrl-bcm2711",
389 .owner = THIS_MODULE,
390 .request = gpiochip_generic_request,
391 .free = gpiochip_generic_free,
392 .direction_input = bcm2835_gpio_direction_input,
393 .direction_output = bcm2835_gpio_direction_output,
394 .get_direction = bcm2835_gpio_get_direction,
395 .get = bcm2835_gpio_get,
396 .set = bcm2835_gpio_set,
397 .set_config = gpiochip_generic_config,
399 .ngpio = BCM2711_NUM_GPIOS,
401 .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
404 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
405 unsigned int bank, u32 mask)
407 unsigned long events;
411 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
413 events &= pc->enabled_irq_map[bank];
414 for_each_set_bit(offset, &events, 32) {
415 gpio = (32 * bank) + offset;
416 generic_handle_domain_irq(pc->gpio_chip.irq.domain,
421 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
423 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
424 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
425 struct irq_chip *host_chip = irq_desc_get_chip(desc);
426 int irq = irq_desc_get_irq(desc);
430 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
431 if (chip->irq.parents[i] == irq) {
436 /* This should not happen, every IRQ has a bank */
437 BUG_ON(i == BCM2835_NUM_IRQS);
439 chained_irq_enter(host_chip, desc);
442 case 0: /* IRQ0 covers GPIOs 0-27 */
443 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
445 case 1: /* IRQ1 covers GPIOs 28-45 */
446 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
447 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
449 case 2: /* IRQ2 covers GPIOs 46-57 */
450 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
454 chained_irq_exit(host_chip, desc);
457 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
462 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
463 unsigned reg, unsigned offset, bool enable)
466 reg += GPIO_REG_OFFSET(offset) * 4;
467 value = bcm2835_gpio_rd(pc, reg);
469 value |= BIT(GPIO_REG_SHIFT(offset));
471 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
472 bcm2835_gpio_wr(pc, reg, value);
475 /* fast path for IRQ handler */
476 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
477 unsigned offset, bool enable)
479 switch (pc->irq_type[offset]) {
480 case IRQ_TYPE_EDGE_RISING:
481 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
484 case IRQ_TYPE_EDGE_FALLING:
485 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
488 case IRQ_TYPE_EDGE_BOTH:
489 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
490 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
493 case IRQ_TYPE_LEVEL_HIGH:
494 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
497 case IRQ_TYPE_LEVEL_LOW:
498 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
503 static void bcm2835_gpio_irq_enable(struct irq_data *data)
505 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
506 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
507 unsigned gpio = irqd_to_hwirq(data);
508 unsigned offset = GPIO_REG_SHIFT(gpio);
509 unsigned bank = GPIO_REG_OFFSET(gpio);
512 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
513 set_bit(offset, &pc->enabled_irq_map[bank]);
514 bcm2835_gpio_irq_config(pc, gpio, true);
515 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
518 static void bcm2835_gpio_irq_disable(struct irq_data *data)
520 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
521 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
522 unsigned gpio = irqd_to_hwirq(data);
523 unsigned offset = GPIO_REG_SHIFT(gpio);
524 unsigned bank = GPIO_REG_OFFSET(gpio);
527 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
528 bcm2835_gpio_irq_config(pc, gpio, false);
529 /* Clear events that were latched prior to clearing event sources */
530 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
531 clear_bit(offset, &pc->enabled_irq_map[bank]);
532 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
535 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
536 unsigned offset, unsigned int type)
540 case IRQ_TYPE_EDGE_RISING:
541 case IRQ_TYPE_EDGE_FALLING:
542 case IRQ_TYPE_EDGE_BOTH:
543 case IRQ_TYPE_LEVEL_HIGH:
544 case IRQ_TYPE_LEVEL_LOW:
545 pc->irq_type[offset] = type;
554 /* slower path for reconfiguring IRQ type */
555 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
556 unsigned offset, unsigned int type)
560 if (pc->irq_type[offset] != type) {
561 bcm2835_gpio_irq_config(pc, offset, false);
562 pc->irq_type[offset] = type;
566 case IRQ_TYPE_EDGE_RISING:
567 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
568 /* RISING already enabled, disable FALLING */
569 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
570 bcm2835_gpio_irq_config(pc, offset, false);
571 pc->irq_type[offset] = type;
572 } else if (pc->irq_type[offset] != type) {
573 bcm2835_gpio_irq_config(pc, offset, false);
574 pc->irq_type[offset] = type;
575 bcm2835_gpio_irq_config(pc, offset, true);
579 case IRQ_TYPE_EDGE_FALLING:
580 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
581 /* FALLING already enabled, disable RISING */
582 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
583 bcm2835_gpio_irq_config(pc, offset, false);
584 pc->irq_type[offset] = type;
585 } else if (pc->irq_type[offset] != type) {
586 bcm2835_gpio_irq_config(pc, offset, false);
587 pc->irq_type[offset] = type;
588 bcm2835_gpio_irq_config(pc, offset, true);
592 case IRQ_TYPE_EDGE_BOTH:
593 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
594 /* RISING already enabled, enable FALLING too */
595 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
596 bcm2835_gpio_irq_config(pc, offset, true);
597 pc->irq_type[offset] = type;
598 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
599 /* FALLING already enabled, enable RISING too */
600 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
601 bcm2835_gpio_irq_config(pc, offset, true);
602 pc->irq_type[offset] = type;
603 } else if (pc->irq_type[offset] != type) {
604 bcm2835_gpio_irq_config(pc, offset, false);
605 pc->irq_type[offset] = type;
606 bcm2835_gpio_irq_config(pc, offset, true);
610 case IRQ_TYPE_LEVEL_HIGH:
611 case IRQ_TYPE_LEVEL_LOW:
612 if (pc->irq_type[offset] != type) {
613 bcm2835_gpio_irq_config(pc, offset, false);
614 pc->irq_type[offset] = type;
615 bcm2835_gpio_irq_config(pc, offset, true);
625 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
627 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
628 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
629 unsigned gpio = irqd_to_hwirq(data);
630 unsigned offset = GPIO_REG_SHIFT(gpio);
631 unsigned bank = GPIO_REG_OFFSET(gpio);
635 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
637 if (test_bit(offset, &pc->enabled_irq_map[bank]))
638 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
640 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
642 if (type & IRQ_TYPE_EDGE_BOTH)
643 irq_set_handler_locked(data, handle_edge_irq);
645 irq_set_handler_locked(data, handle_level_irq);
647 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
652 static void bcm2835_gpio_irq_ack(struct irq_data *data)
654 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
655 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
656 unsigned gpio = irqd_to_hwirq(data);
658 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
661 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
663 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
664 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
665 unsigned gpio = irqd_to_hwirq(data);
666 unsigned int irqgroup;
674 else if (gpio >= 28 && gpio <= 45)
676 else if (gpio >= 46 && gpio <= 57)
682 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
684 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
689 static struct irq_chip bcm2835_gpio_irq_chip = {
691 .irq_enable = bcm2835_gpio_irq_enable,
692 .irq_disable = bcm2835_gpio_irq_disable,
693 .irq_set_type = bcm2835_gpio_irq_set_type,
694 .irq_ack = bcm2835_gpio_irq_ack,
695 .irq_mask = bcm2835_gpio_irq_disable,
696 .irq_unmask = bcm2835_gpio_irq_enable,
697 .irq_set_wake = bcm2835_gpio_irq_set_wake,
698 .flags = IRQCHIP_MASK_ON_SUSPEND,
701 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
703 return BCM2835_NUM_GPIOS;
706 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
709 return bcm2835_gpio_groups[selector];
712 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
714 const unsigned **pins,
717 *pins = &bcm2835_gpio_pins[selector].number;
723 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
727 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
728 struct gpio_chip *chip = &pc->gpio_chip;
729 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
730 const char *fname = bcm2835_functions[fsel];
731 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
732 int irq = irq_find_mapping(chip->irq.domain, offset);
734 seq_printf(s, "function %s in %s; irq %d (%s)",
735 fname, value ? "hi" : "lo",
736 irq, irq_type_names[pc->irq_type[offset]]);
739 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
740 struct pinctrl_map *maps, unsigned num_maps)
744 for (i = 0; i < num_maps; i++)
745 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
746 kfree(maps[i].data.configs.configs);
751 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
752 struct device_node *np, u32 pin, u32 fnum,
753 struct pinctrl_map **maps)
755 struct pinctrl_map *map = *maps;
757 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
758 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
762 map->type = PIN_MAP_TYPE_MUX_GROUP;
763 map->data.mux.group = bcm2835_gpio_groups[pin];
764 map->data.mux.function = bcm2835_functions[fnum];
770 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
771 struct device_node *np, u32 pin, u32 pull,
772 struct pinctrl_map **maps)
774 struct pinctrl_map *map = *maps;
775 unsigned long *configs;
778 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
782 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
785 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
787 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
788 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
789 map->data.configs.configs = configs;
790 map->data.configs.num_configs = 1;
796 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
797 struct device_node *np,
798 struct pinctrl_map **map, unsigned int *num_maps)
800 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
801 struct property *pins, *funcs, *pulls;
802 int num_pins, num_funcs, num_pulls, maps_per_pin;
803 struct pinctrl_map *maps, *cur_map;
807 /* Check for generic binding in this node */
808 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
809 if (err || *num_maps)
812 /* Generic binding did not find anything continue with legacy parse */
813 pins = of_find_property(np, "brcm,pins", NULL);
815 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
819 funcs = of_find_property(np, "brcm,function", NULL);
820 pulls = of_find_property(np, "brcm,pull", NULL);
822 if (!funcs && !pulls) {
824 "%pOF: neither brcm,function nor brcm,pull specified\n",
829 num_pins = pins->length / 4;
830 num_funcs = funcs ? (funcs->length / 4) : 0;
831 num_pulls = pulls ? (pulls->length / 4) : 0;
833 if (num_funcs > 1 && num_funcs != num_pins) {
835 "%pOF: brcm,function must have 1 or %d entries\n",
840 if (num_pulls > 1 && num_pulls != num_pins) {
842 "%pOF: brcm,pull must have 1 or %d entries\n",
852 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
857 for (i = 0; i < num_pins; i++) {
858 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
861 if (pin >= pc->pctl_desc.npins) {
862 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
869 err = of_property_read_u32_index(np, "brcm,function",
870 (num_funcs > 1) ? i : 0, &func);
873 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
879 err = of_property_read_u32_index(np, "brcm,pull",
880 (num_pulls > 1) ? i : 0, &pull);
883 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
891 *num_maps = num_pins * maps_per_pin;
896 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
900 static const struct pinctrl_ops bcm2835_pctl_ops = {
901 .get_groups_count = bcm2835_pctl_get_groups_count,
902 .get_group_name = bcm2835_pctl_get_group_name,
903 .get_group_pins = bcm2835_pctl_get_group_pins,
904 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
905 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
906 .dt_free_map = bcm2835_pctl_dt_free_map,
909 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
912 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
914 /* disable by setting to GPIO_IN */
915 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
919 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
921 return BCM2835_FSEL_COUNT;
924 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
927 return bcm2835_functions[selector];
930 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
932 const char * const **groups,
933 unsigned * const num_groups)
935 /* every pin can do every function */
936 *groups = bcm2835_gpio_groups;
937 *num_groups = BCM2835_NUM_GPIOS;
942 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
943 unsigned func_selector,
944 unsigned group_selector)
946 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
948 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
953 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
954 struct pinctrl_gpio_range *range,
957 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
959 /* disable by setting to GPIO_IN */
960 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
963 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
964 struct pinctrl_gpio_range *range,
968 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
969 enum bcm2835_fsel fsel = input ?
970 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
972 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
977 static const struct pinmux_ops bcm2835_pmx_ops = {
978 .free = bcm2835_pmx_free,
979 .get_functions_count = bcm2835_pmx_get_functions_count,
980 .get_function_name = bcm2835_pmx_get_function_name,
981 .get_function_groups = bcm2835_pmx_get_function_groups,
982 .set_mux = bcm2835_pmx_set,
983 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
984 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
987 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
988 unsigned pin, unsigned long *config)
990 /* No way to read back config in HW */
994 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
995 unsigned int pin, unsigned int arg)
999 off = GPIO_REG_OFFSET(pin);
1000 bit = GPIO_REG_SHIFT(pin);
1002 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1004 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1005 * But the VideoCore firmware delay for this operation
1006 * based nearly on the same amount of VPU cycles and this clock
1010 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1012 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1015 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1016 unsigned int pin, unsigned long *configs,
1017 unsigned int num_configs)
1019 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1023 for (i = 0; i < num_configs; i++) {
1024 param = pinconf_to_config_param(configs[i]);
1025 arg = pinconf_to_config_argument(configs[i]);
1028 /* Set legacy brcm,pull */
1029 case BCM2835_PINCONF_PARAM_PULL:
1030 bcm2835_pull_config_set(pc, pin, arg);
1033 /* Set pull generic bindings */
1034 case PIN_CONFIG_BIAS_DISABLE:
1035 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1038 case PIN_CONFIG_BIAS_PULL_DOWN:
1039 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1042 case PIN_CONFIG_BIAS_PULL_UP:
1043 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1046 /* Set output-high or output-low */
1047 case PIN_CONFIG_OUTPUT:
1048 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1054 } /* switch param type */
1055 } /* for each config */
1060 static const struct pinconf_ops bcm2835_pinconf_ops = {
1062 .pin_config_get = bcm2835_pinconf_get,
1063 .pin_config_set = bcm2835_pinconf_set,
1066 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1067 unsigned int pin, unsigned int arg)
1073 off = PUD_2711_REG_OFFSET(pin);
1074 shifter = PUD_2711_REG_SHIFT(pin);
1076 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1077 value &= ~(PUD_2711_MASK << shifter);
1078 value |= (arg << shifter);
1079 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1082 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1083 unsigned int pin, unsigned long *configs,
1084 unsigned int num_configs)
1086 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1090 for (i = 0; i < num_configs; i++) {
1091 param = pinconf_to_config_param(configs[i]);
1092 arg = pinconf_to_config_argument(configs[i]);
1095 /* convert legacy brcm,pull */
1096 case BCM2835_PINCONF_PARAM_PULL:
1097 if (arg == BCM2835_PUD_UP)
1098 arg = BCM2711_PULL_UP;
1099 else if (arg == BCM2835_PUD_DOWN)
1100 arg = BCM2711_PULL_DOWN;
1102 arg = BCM2711_PULL_NONE;
1104 bcm2711_pull_config_set(pc, pin, arg);
1107 /* Set pull generic bindings */
1108 case PIN_CONFIG_BIAS_DISABLE:
1109 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1111 case PIN_CONFIG_BIAS_PULL_DOWN:
1112 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1114 case PIN_CONFIG_BIAS_PULL_UP:
1115 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1118 /* Set output-high or output-low */
1119 case PIN_CONFIG_OUTPUT:
1120 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1126 } /* for each config */
1131 static const struct pinconf_ops bcm2711_pinconf_ops = {
1133 .pin_config_get = bcm2835_pinconf_get,
1134 .pin_config_set = bcm2711_pinconf_set,
1137 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1138 .name = MODULE_NAME,
1139 .pins = bcm2835_gpio_pins,
1140 .npins = BCM2835_NUM_GPIOS,
1141 .pctlops = &bcm2835_pctl_ops,
1142 .pmxops = &bcm2835_pmx_ops,
1143 .confops = &bcm2835_pinconf_ops,
1144 .owner = THIS_MODULE,
1147 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1148 .name = "pinctrl-bcm2711",
1149 .pins = bcm2835_gpio_pins,
1150 .npins = BCM2711_NUM_GPIOS,
1151 .pctlops = &bcm2835_pctl_ops,
1152 .pmxops = &bcm2835_pmx_ops,
1153 .confops = &bcm2711_pinconf_ops,
1154 .owner = THIS_MODULE,
1157 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1158 .name = MODULE_NAME,
1159 .npins = BCM2835_NUM_GPIOS,
1162 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1163 .name = "pinctrl-bcm2711",
1164 .npins = BCM2711_NUM_GPIOS,
1167 struct bcm_plat_data {
1168 const struct gpio_chip *gpio_chip;
1169 const struct pinctrl_desc *pctl_desc;
1170 const struct pinctrl_gpio_range *gpio_range;
1173 static const struct bcm_plat_data bcm2835_plat_data = {
1174 .gpio_chip = &bcm2835_gpio_chip,
1175 .pctl_desc = &bcm2835_pinctrl_desc,
1176 .gpio_range = &bcm2835_pinctrl_gpio_range,
1179 static const struct bcm_plat_data bcm2711_plat_data = {
1180 .gpio_chip = &bcm2711_gpio_chip,
1181 .pctl_desc = &bcm2711_pinctrl_desc,
1182 .gpio_range = &bcm2711_pinctrl_gpio_range,
1185 static const struct of_device_id bcm2835_pinctrl_match[] = {
1187 .compatible = "brcm,bcm2835-gpio",
1188 .data = &bcm2835_plat_data,
1191 .compatible = "brcm,bcm2711-gpio",
1192 .data = &bcm2711_plat_data,
1195 .compatible = "brcm,bcm7211-gpio",
1196 .data = &bcm2711_plat_data,
1201 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1203 struct device *dev = &pdev->dev;
1204 struct device_node *np = dev->of_node;
1205 const struct bcm_plat_data *pdata;
1206 struct bcm2835_pinctrl *pc;
1207 struct gpio_irq_chip *girq;
1208 struct resource iomem;
1210 const struct of_device_id *match;
1213 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1214 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1216 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1220 platform_set_drvdata(pdev, pc);
1223 err = of_address_to_resource(np, 0, &iomem);
1225 dev_err(dev, "could not get IO memory\n");
1229 pc->base = devm_ioremap_resource(dev, &iomem);
1230 if (IS_ERR(pc->base))
1231 return PTR_ERR(pc->base);
1233 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1237 pdata = match->data;
1238 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1240 pc->gpio_chip = *pdata->gpio_chip;
1241 pc->gpio_chip.parent = dev;
1242 pc->gpio_chip.of_node = np;
1244 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1245 unsigned long events;
1248 /* clear event detection flags */
1249 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1250 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1251 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1252 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1253 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1254 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1256 /* clear all the events */
1257 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1258 for_each_set_bit(offset, &events, 32)
1259 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1261 raw_spin_lock_init(&pc->irq_lock[i]);
1264 pc->pctl_desc = *pdata->pctl_desc;
1265 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1266 if (IS_ERR(pc->pctl_dev)) {
1267 gpiochip_remove(&pc->gpio_chip);
1268 return PTR_ERR(pc->pctl_dev);
1271 pc->gpio_range = *pdata->gpio_range;
1272 pc->gpio_range.base = pc->gpio_chip.base;
1273 pc->gpio_range.gc = &pc->gpio_chip;
1274 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1276 girq = &pc->gpio_chip.irq;
1277 girq->chip = &bcm2835_gpio_irq_chip;
1278 girq->parent_handler = bcm2835_gpio_irq_handler;
1279 girq->num_parents = BCM2835_NUM_IRQS;
1280 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1281 sizeof(*girq->parents),
1283 if (!girq->parents) {
1289 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1290 sizeof(*pc->wake_irq),
1292 if (!pc->wake_irq) {
1299 * Use the same handler for all groups: this is necessary
1300 * since we use one gpiochip to cover all lines - the
1301 * irq handler then needs to figure out which group and
1302 * bank that was firing the IRQ and look up the per-group
1305 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1309 girq->parents[i] = irq_of_parse_and_map(np, i);
1311 if (!girq->parents[i]) {
1312 girq->num_parents = i;
1317 /* Skip over the all banks interrupts */
1318 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1319 BCM2835_NUM_IRQS + 1);
1321 len = strlen(dev_name(pc->dev)) + 16;
1322 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1328 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1330 /* These are optional interrupts */
1331 err = devm_request_irq(dev, pc->wake_irq[i],
1332 bcm2835_gpio_wake_irq_handler,
1333 IRQF_SHARED, name, pc);
1335 dev_warn(dev, "unable to request wake IRQ %d\n",
1339 girq->default_type = IRQ_TYPE_NONE;
1340 girq->handler = handle_level_irq;
1342 err = gpiochip_add_data(&pc->gpio_chip, pc);
1344 dev_err(dev, "could not add GPIO chip\n");
1351 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1355 static struct platform_driver bcm2835_pinctrl_driver = {
1356 .probe = bcm2835_pinctrl_probe,
1358 .name = MODULE_NAME,
1359 .of_match_table = bcm2835_pinctrl_match,
1360 .suppress_bind_attrs = true,
1363 builtin_platform_driver(bcm2835_pinctrl_driver);