2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio/driver.h>
28 #include <linux/irq.h>
29 #include <linux/irqdesc.h>
30 #include <linux/init.h>
31 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/pinctrl/machine.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinctrl.h>
38 #include <linux/pinctrl/pinmux.h>
39 #include <linux/pinctrl/pinconf-generic.h>
40 #include <linux/platform_device.h>
41 #include <linux/seq_file.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/types.h>
45 #include <dt-bindings/pinctrl/bcm2835.h>
47 #define MODULE_NAME "pinctrl-bcm2835"
48 #define BCM2835_NUM_GPIOS 54
49 #define BCM2835_NUM_BANKS 2
50 #define BCM2835_NUM_IRQS 3
52 #define BCM2835_PIN_BITMAP_SZ \
53 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
55 /* GPIO register offsets */
56 #define GPFSEL0 0x0 /* Function Select */
57 #define GPSET0 0x1c /* Pin Output Set */
58 #define GPCLR0 0x28 /* Pin Output Clear */
59 #define GPLEV0 0x34 /* Pin Level */
60 #define GPEDS0 0x40 /* Pin Event Detect Status */
61 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
62 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
63 #define GPHEN0 0x64 /* Pin High Detect Enable */
64 #define GPLEN0 0x70 /* Pin Low Detect Enable */
65 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
66 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
67 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
68 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
70 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
71 #define FSEL_SHIFT(p) (((p) % 10) * 3)
72 #define GPIO_REG_OFFSET(p) ((p) / 32)
73 #define GPIO_REG_SHIFT(p) ((p) % 32)
75 /* argument: bcm2835_pinconf_pull */
76 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
78 struct bcm2835_pinctrl {
81 int irq[BCM2835_NUM_IRQS];
83 /* note: locking assumes each bank will have its own unsigned long */
84 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
85 unsigned int irq_type[BCM2835_NUM_GPIOS];
87 struct pinctrl_dev *pctl_dev;
88 struct gpio_chip gpio_chip;
89 struct pinctrl_gpio_range gpio_range;
91 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
94 /* pins are just named GPIO0..GPIO53 */
95 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
96 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
107 BCM2835_GPIO_PIN(10),
108 BCM2835_GPIO_PIN(11),
109 BCM2835_GPIO_PIN(12),
110 BCM2835_GPIO_PIN(13),
111 BCM2835_GPIO_PIN(14),
112 BCM2835_GPIO_PIN(15),
113 BCM2835_GPIO_PIN(16),
114 BCM2835_GPIO_PIN(17),
115 BCM2835_GPIO_PIN(18),
116 BCM2835_GPIO_PIN(19),
117 BCM2835_GPIO_PIN(20),
118 BCM2835_GPIO_PIN(21),
119 BCM2835_GPIO_PIN(22),
120 BCM2835_GPIO_PIN(23),
121 BCM2835_GPIO_PIN(24),
122 BCM2835_GPIO_PIN(25),
123 BCM2835_GPIO_PIN(26),
124 BCM2835_GPIO_PIN(27),
125 BCM2835_GPIO_PIN(28),
126 BCM2835_GPIO_PIN(29),
127 BCM2835_GPIO_PIN(30),
128 BCM2835_GPIO_PIN(31),
129 BCM2835_GPIO_PIN(32),
130 BCM2835_GPIO_PIN(33),
131 BCM2835_GPIO_PIN(34),
132 BCM2835_GPIO_PIN(35),
133 BCM2835_GPIO_PIN(36),
134 BCM2835_GPIO_PIN(37),
135 BCM2835_GPIO_PIN(38),
136 BCM2835_GPIO_PIN(39),
137 BCM2835_GPIO_PIN(40),
138 BCM2835_GPIO_PIN(41),
139 BCM2835_GPIO_PIN(42),
140 BCM2835_GPIO_PIN(43),
141 BCM2835_GPIO_PIN(44),
142 BCM2835_GPIO_PIN(45),
143 BCM2835_GPIO_PIN(46),
144 BCM2835_GPIO_PIN(47),
145 BCM2835_GPIO_PIN(48),
146 BCM2835_GPIO_PIN(49),
147 BCM2835_GPIO_PIN(50),
148 BCM2835_GPIO_PIN(51),
149 BCM2835_GPIO_PIN(52),
150 BCM2835_GPIO_PIN(53),
153 /* one pin per group */
154 static const char * const bcm2835_gpio_groups[] = {
212 BCM2835_FSEL_COUNT = 8,
213 BCM2835_FSEL_MASK = 0x7,
216 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
217 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
218 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
219 [BCM2835_FSEL_ALT0] = "alt0",
220 [BCM2835_FSEL_ALT1] = "alt1",
221 [BCM2835_FSEL_ALT2] = "alt2",
222 [BCM2835_FSEL_ALT3] = "alt3",
223 [BCM2835_FSEL_ALT4] = "alt4",
224 [BCM2835_FSEL_ALT5] = "alt5",
227 static const char * const irq_type_names[] = {
228 [IRQ_TYPE_NONE] = "none",
229 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
230 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
231 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
232 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
233 [IRQ_TYPE_LEVEL_LOW] = "level-low",
236 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
238 return readl(pc->base + reg);
241 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
244 writel(val, pc->base + reg);
247 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
250 reg += GPIO_REG_OFFSET(bit) * 4;
251 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
254 /* note NOT a read/modify/write cycle */
255 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
256 unsigned reg, unsigned bit)
258 reg += GPIO_REG_OFFSET(bit) * 4;
259 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
262 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
263 struct bcm2835_pinctrl *pc, unsigned pin)
265 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
266 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
268 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
269 bcm2835_functions[status]);
274 static inline void bcm2835_pinctrl_fsel_set(
275 struct bcm2835_pinctrl *pc, unsigned pin,
276 enum bcm2835_fsel fsel)
278 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
279 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
281 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
282 bcm2835_functions[cur]);
287 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
288 /* always transition through GPIO_IN */
289 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
290 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
292 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
293 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
294 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
297 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
298 val |= fsel << FSEL_SHIFT(pin);
300 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
301 bcm2835_functions[fsel]);
302 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
305 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
307 return pinctrl_gpio_direction_input(chip->base + offset);
310 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
312 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
314 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
317 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
319 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
320 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
322 /* Alternative function doesn't clearly provide a direction */
323 if (fsel > BCM2835_FSEL_GPIO_OUT)
326 return (fsel == BCM2835_FSEL_GPIO_IN);
329 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
331 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
333 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
336 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
337 unsigned offset, int value)
339 bcm2835_gpio_set(chip, offset, value);
340 return pinctrl_gpio_direction_output(chip->base + offset);
343 static const struct gpio_chip bcm2835_gpio_chip = {
344 .label = MODULE_NAME,
345 .owner = THIS_MODULE,
346 .request = gpiochip_generic_request,
347 .free = gpiochip_generic_free,
348 .direction_input = bcm2835_gpio_direction_input,
349 .direction_output = bcm2835_gpio_direction_output,
350 .get_direction = bcm2835_gpio_get_direction,
351 .get = bcm2835_gpio_get,
352 .set = bcm2835_gpio_set,
354 .ngpio = BCM2835_NUM_GPIOS,
358 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
359 unsigned int bank, u32 mask)
361 unsigned long events;
365 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
367 events &= pc->enabled_irq_map[bank];
368 for_each_set_bit(offset, &events, 32) {
369 gpio = (32 * bank) + offset;
370 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
375 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
377 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
378 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
379 struct irq_chip *host_chip = irq_desc_get_chip(desc);
380 int irq = irq_desc_get_irq(desc);
384 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
385 if (pc->irq[i] == irq) {
390 /* This should not happen, every IRQ has a bank */
391 if (i == ARRAY_SIZE(pc->irq))
394 chained_irq_enter(host_chip, desc);
397 case 0: /* IRQ0 covers GPIOs 0-27 */
398 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
400 case 1: /* IRQ1 covers GPIOs 28-45 */
401 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
402 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
404 case 2: /* IRQ2 covers GPIOs 46-53 */
405 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
409 chained_irq_exit(host_chip, desc);
412 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
413 unsigned reg, unsigned offset, bool enable)
416 reg += GPIO_REG_OFFSET(offset) * 4;
417 value = bcm2835_gpio_rd(pc, reg);
419 value |= BIT(GPIO_REG_SHIFT(offset));
421 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
422 bcm2835_gpio_wr(pc, reg, value);
425 /* fast path for IRQ handler */
426 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
427 unsigned offset, bool enable)
429 switch (pc->irq_type[offset]) {
430 case IRQ_TYPE_EDGE_RISING:
431 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
434 case IRQ_TYPE_EDGE_FALLING:
435 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
438 case IRQ_TYPE_EDGE_BOTH:
439 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
440 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
443 case IRQ_TYPE_LEVEL_HIGH:
444 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
447 case IRQ_TYPE_LEVEL_LOW:
448 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
453 static void bcm2835_gpio_irq_enable(struct irq_data *data)
455 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
456 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
457 unsigned gpio = irqd_to_hwirq(data);
458 unsigned offset = GPIO_REG_SHIFT(gpio);
459 unsigned bank = GPIO_REG_OFFSET(gpio);
462 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
463 set_bit(offset, &pc->enabled_irq_map[bank]);
464 bcm2835_gpio_irq_config(pc, gpio, true);
465 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
468 static void bcm2835_gpio_irq_disable(struct irq_data *data)
470 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
471 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
472 unsigned gpio = irqd_to_hwirq(data);
473 unsigned offset = GPIO_REG_SHIFT(gpio);
474 unsigned bank = GPIO_REG_OFFSET(gpio);
477 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
478 bcm2835_gpio_irq_config(pc, gpio, false);
479 /* Clear events that were latched prior to clearing event sources */
480 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
481 clear_bit(offset, &pc->enabled_irq_map[bank]);
482 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
485 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
486 unsigned offset, unsigned int type)
490 case IRQ_TYPE_EDGE_RISING:
491 case IRQ_TYPE_EDGE_FALLING:
492 case IRQ_TYPE_EDGE_BOTH:
493 case IRQ_TYPE_LEVEL_HIGH:
494 case IRQ_TYPE_LEVEL_LOW:
495 pc->irq_type[offset] = type;
504 /* slower path for reconfiguring IRQ type */
505 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
506 unsigned offset, unsigned int type)
510 if (pc->irq_type[offset] != type) {
511 bcm2835_gpio_irq_config(pc, offset, false);
512 pc->irq_type[offset] = type;
516 case IRQ_TYPE_EDGE_RISING:
517 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
518 /* RISING already enabled, disable FALLING */
519 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
520 bcm2835_gpio_irq_config(pc, offset, false);
521 pc->irq_type[offset] = type;
522 } else if (pc->irq_type[offset] != type) {
523 bcm2835_gpio_irq_config(pc, offset, false);
524 pc->irq_type[offset] = type;
525 bcm2835_gpio_irq_config(pc, offset, true);
529 case IRQ_TYPE_EDGE_FALLING:
530 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
531 /* FALLING already enabled, disable RISING */
532 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
533 bcm2835_gpio_irq_config(pc, offset, false);
534 pc->irq_type[offset] = type;
535 } else if (pc->irq_type[offset] != type) {
536 bcm2835_gpio_irq_config(pc, offset, false);
537 pc->irq_type[offset] = type;
538 bcm2835_gpio_irq_config(pc, offset, true);
542 case IRQ_TYPE_EDGE_BOTH:
543 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
544 /* RISING already enabled, enable FALLING too */
545 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
546 bcm2835_gpio_irq_config(pc, offset, true);
547 pc->irq_type[offset] = type;
548 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
549 /* FALLING already enabled, enable RISING too */
550 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
551 bcm2835_gpio_irq_config(pc, offset, true);
552 pc->irq_type[offset] = type;
553 } else if (pc->irq_type[offset] != type) {
554 bcm2835_gpio_irq_config(pc, offset, false);
555 pc->irq_type[offset] = type;
556 bcm2835_gpio_irq_config(pc, offset, true);
560 case IRQ_TYPE_LEVEL_HIGH:
561 case IRQ_TYPE_LEVEL_LOW:
562 if (pc->irq_type[offset] != type) {
563 bcm2835_gpio_irq_config(pc, offset, false);
564 pc->irq_type[offset] = type;
565 bcm2835_gpio_irq_config(pc, offset, true);
575 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
577 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
578 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
579 unsigned gpio = irqd_to_hwirq(data);
580 unsigned offset = GPIO_REG_SHIFT(gpio);
581 unsigned bank = GPIO_REG_OFFSET(gpio);
585 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
587 if (test_bit(offset, &pc->enabled_irq_map[bank]))
588 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
590 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
592 if (type & IRQ_TYPE_EDGE_BOTH)
593 irq_set_handler_locked(data, handle_edge_irq);
595 irq_set_handler_locked(data, handle_level_irq);
597 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
602 static void bcm2835_gpio_irq_ack(struct irq_data *data)
604 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
605 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
606 unsigned gpio = irqd_to_hwirq(data);
608 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
611 static struct irq_chip bcm2835_gpio_irq_chip = {
613 .irq_enable = bcm2835_gpio_irq_enable,
614 .irq_disable = bcm2835_gpio_irq_disable,
615 .irq_set_type = bcm2835_gpio_irq_set_type,
616 .irq_ack = bcm2835_gpio_irq_ack,
617 .irq_mask = bcm2835_gpio_irq_disable,
618 .irq_unmask = bcm2835_gpio_irq_enable,
621 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
623 return ARRAY_SIZE(bcm2835_gpio_groups);
626 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
629 return bcm2835_gpio_groups[selector];
632 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
634 const unsigned **pins,
637 *pins = &bcm2835_gpio_pins[selector].number;
643 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
647 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
648 struct gpio_chip *chip = &pc->gpio_chip;
649 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
650 const char *fname = bcm2835_functions[fsel];
651 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
652 int irq = irq_find_mapping(chip->irq.domain, offset);
654 seq_printf(s, "function %s in %s; irq %d (%s)",
655 fname, value ? "hi" : "lo",
656 irq, irq_type_names[pc->irq_type[offset]]);
659 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
660 struct pinctrl_map *maps, unsigned num_maps)
664 for (i = 0; i < num_maps; i++)
665 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
666 kfree(maps[i].data.configs.configs);
671 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
672 struct device_node *np, u32 pin, u32 fnum,
673 struct pinctrl_map **maps)
675 struct pinctrl_map *map = *maps;
677 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
678 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
682 map->type = PIN_MAP_TYPE_MUX_GROUP;
683 map->data.mux.group = bcm2835_gpio_groups[pin];
684 map->data.mux.function = bcm2835_functions[fnum];
690 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
691 struct device_node *np, u32 pin, u32 pull,
692 struct pinctrl_map **maps)
694 struct pinctrl_map *map = *maps;
695 unsigned long *configs;
698 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
702 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
705 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
707 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
708 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
709 map->data.configs.configs = configs;
710 map->data.configs.num_configs = 1;
716 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
717 struct device_node *np,
718 struct pinctrl_map **map, unsigned int *num_maps)
720 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
721 struct property *pins, *funcs, *pulls;
722 int num_pins, num_funcs, num_pulls, maps_per_pin;
723 struct pinctrl_map *maps, *cur_map;
727 /* Check for generic binding in this node */
728 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
729 if (err || *num_maps)
732 /* Generic binding did not find anything continue with legacy parse */
733 pins = of_find_property(np, "brcm,pins", NULL);
735 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
739 funcs = of_find_property(np, "brcm,function", NULL);
740 pulls = of_find_property(np, "brcm,pull", NULL);
742 if (!funcs && !pulls) {
744 "%pOF: neither brcm,function nor brcm,pull specified\n",
749 num_pins = pins->length / 4;
750 num_funcs = funcs ? (funcs->length / 4) : 0;
751 num_pulls = pulls ? (pulls->length / 4) : 0;
753 if (num_funcs > 1 && num_funcs != num_pins) {
755 "%pOF: brcm,function must have 1 or %d entries\n",
760 if (num_pulls > 1 && num_pulls != num_pins) {
762 "%pOF: brcm,pull must have 1 or %d entries\n",
772 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
777 for (i = 0; i < num_pins; i++) {
778 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
781 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
782 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
789 err = of_property_read_u32_index(np, "brcm,function",
790 (num_funcs > 1) ? i : 0, &func);
793 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
799 err = of_property_read_u32_index(np, "brcm,pull",
800 (num_pulls > 1) ? i : 0, &pull);
803 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
811 *num_maps = num_pins * maps_per_pin;
816 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
820 static const struct pinctrl_ops bcm2835_pctl_ops = {
821 .get_groups_count = bcm2835_pctl_get_groups_count,
822 .get_group_name = bcm2835_pctl_get_group_name,
823 .get_group_pins = bcm2835_pctl_get_group_pins,
824 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
825 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
826 .dt_free_map = bcm2835_pctl_dt_free_map,
829 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
832 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
834 /* disable by setting to GPIO_IN */
835 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
839 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
841 return BCM2835_FSEL_COUNT;
844 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
847 return bcm2835_functions[selector];
850 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
852 const char * const **groups,
853 unsigned * const num_groups)
855 /* every pin can do every function */
856 *groups = bcm2835_gpio_groups;
857 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
862 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
863 unsigned func_selector,
864 unsigned group_selector)
866 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
868 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
873 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
874 struct pinctrl_gpio_range *range,
877 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
879 /* disable by setting to GPIO_IN */
880 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
883 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
884 struct pinctrl_gpio_range *range,
888 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
889 enum bcm2835_fsel fsel = input ?
890 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
892 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
897 static const struct pinmux_ops bcm2835_pmx_ops = {
898 .free = bcm2835_pmx_free,
899 .get_functions_count = bcm2835_pmx_get_functions_count,
900 .get_function_name = bcm2835_pmx_get_function_name,
901 .get_function_groups = bcm2835_pmx_get_function_groups,
902 .set_mux = bcm2835_pmx_set,
903 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
904 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
907 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
908 unsigned pin, unsigned long *config)
910 /* No way to read back config in HW */
914 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
915 unsigned int pin, unsigned int arg)
919 off = GPIO_REG_OFFSET(pin);
920 bit = GPIO_REG_SHIFT(pin);
922 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
924 * BCM2835 datasheet say to wait 150 cycles, but not of what.
925 * But the VideoCore firmware delay for this operation
926 * based nearly on the same amount of VPU cycles and this clock
930 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
932 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
935 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
936 unsigned int pin, unsigned long *configs,
937 unsigned int num_configs)
939 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
943 for (i = 0; i < num_configs; i++) {
944 param = pinconf_to_config_param(configs[i]);
945 arg = pinconf_to_config_argument(configs[i]);
948 /* Set legacy brcm,pull */
949 case BCM2835_PINCONF_PARAM_PULL:
950 bcm2835_pull_config_set(pc, pin, arg);
953 /* Set pull generic bindings */
954 case PIN_CONFIG_BIAS_DISABLE:
955 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
958 case PIN_CONFIG_BIAS_PULL_DOWN:
959 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
962 case PIN_CONFIG_BIAS_PULL_UP:
963 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
966 /* Set output-high or output-low */
967 case PIN_CONFIG_OUTPUT:
968 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
974 } /* switch param type */
975 } /* for each config */
980 static const struct pinconf_ops bcm2835_pinconf_ops = {
981 .pin_config_get = bcm2835_pinconf_get,
982 .pin_config_set = bcm2835_pinconf_set,
985 static struct pinctrl_desc bcm2835_pinctrl_desc = {
987 .pins = bcm2835_gpio_pins,
988 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
989 .pctlops = &bcm2835_pctl_ops,
990 .pmxops = &bcm2835_pmx_ops,
991 .confops = &bcm2835_pinconf_ops,
992 .owner = THIS_MODULE,
995 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
997 .npins = BCM2835_NUM_GPIOS,
1000 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1002 struct device *dev = &pdev->dev;
1003 struct device_node *np = dev->of_node;
1004 struct bcm2835_pinctrl *pc;
1005 struct resource iomem;
1007 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
1008 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
1010 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1014 platform_set_drvdata(pdev, pc);
1017 err = of_address_to_resource(np, 0, &iomem);
1019 dev_err(dev, "could not get IO memory\n");
1023 pc->base = devm_ioremap_resource(dev, &iomem);
1024 if (IS_ERR(pc->base))
1025 return PTR_ERR(pc->base);
1027 pc->gpio_chip = bcm2835_gpio_chip;
1028 pc->gpio_chip.parent = dev;
1029 pc->gpio_chip.of_node = np;
1031 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1032 unsigned long events;
1035 /* clear event detection flags */
1036 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1037 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1038 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1039 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1040 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1041 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1043 /* clear all the events */
1044 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1045 for_each_set_bit(offset, &events, 32)
1046 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1048 raw_spin_lock_init(&pc->irq_lock[i]);
1051 err = gpiochip_add_data(&pc->gpio_chip, pc);
1053 dev_err(dev, "could not add GPIO chip\n");
1057 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1058 0, handle_level_irq, IRQ_TYPE_NONE);
1060 dev_info(dev, "could not add irqchip\n");
1064 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1065 pc->irq[i] = irq_of_parse_and_map(np, i);
1067 if (pc->irq[i] == 0)
1071 * Use the same handler for all groups: this is necessary
1072 * since we use one gpiochip to cover all lines - the
1073 * irq handler then needs to figure out which group and
1074 * bank that was firing the IRQ and look up the per-group
1077 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1078 &bcm2835_gpio_irq_chip,
1080 bcm2835_gpio_irq_handler);
1083 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1084 if (IS_ERR(pc->pctl_dev)) {
1085 gpiochip_remove(&pc->gpio_chip);
1086 return PTR_ERR(pc->pctl_dev);
1089 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1090 pc->gpio_range.base = pc->gpio_chip.base;
1091 pc->gpio_range.gc = &pc->gpio_chip;
1092 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1097 static const struct of_device_id bcm2835_pinctrl_match[] = {
1098 { .compatible = "brcm,bcm2835-gpio" },
1102 static struct platform_driver bcm2835_pinctrl_driver = {
1103 .probe = bcm2835_pinctrl_probe,
1105 .name = MODULE_NAME,
1106 .of_match_table = bcm2835_pinctrl_match,
1107 .suppress_bind_attrs = true,
1110 builtin_platform_driver(bcm2835_pinctrl_driver);