1 // SPDX-License-Identifier: GPL-2.0+
3 * OWL SoC's Pinctrl definitions
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12 #ifndef __PINCTRL_OWL_H__
13 #define __PINCTRL_OWL_H__
15 #define OWL_PINCONF_SLEW_SLOW 0
16 #define OWL_PINCONF_SLEW_FAST 1
18 enum owl_pinconf_pull {
20 OWL_PINCONF_PULL_DOWN,
22 OWL_PINCONF_PULL_HOLD,
25 enum owl_pinconf_drv {
32 /* GPIO CTRL Bit Definition */
33 #define OWL_GPIO_CTLR_PENDING 0
34 #define OWL_GPIO_CTLR_ENABLE 1
35 #define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2
37 /* GPIO TYPE Bit Definition */
38 #define OWL_GPIO_INT_LEVEL_HIGH 0
39 #define OWL_GPIO_INT_LEVEL_LOW 1
40 #define OWL_GPIO_INT_EDGE_RISING 2
41 #define OWL_GPIO_INT_EDGE_FALLING 3
42 #define OWL_GPIO_INT_MASK 3
45 * struct owl_pullctl - Actions pad pull control register
46 * @reg: offset to the pull control register
47 * @shift: shift value of the register
48 * @width: width of the register
57 * struct owl_st - Actions pad schmitt trigger enable register
58 * @reg: offset to the schmitt trigger enable register
59 * @shift: shift value of the register
60 * @width: width of the register
69 * struct owl_pingroup - Actions pingroup definition
70 * @name: name of the pin group
71 * @pads: list of pins assigned to this pingroup
72 * @npads: size of @pads array
73 * @funcs: list of pinmux functions for this pingroup
74 * @nfuncs: size of @funcs array
75 * @mfpctl_reg: multiplexing control register offset
76 * @mfpctl_shift: multiplexing control register bit mask
77 * @mfpctl_width: multiplexing control register width
78 * @drv_reg: drive control register offset
79 * @drv_shift: drive control register bit mask
80 * @drv_width: driver control register width
81 * @sr_reg: slew rate control register offset
82 * @sr_shift: slew rate control register bit mask
83 * @sr_width: slew rate control register width
93 unsigned int mfpctl_shift;
94 unsigned int mfpctl_width;
97 unsigned int drv_shift;
98 unsigned int drv_width;
101 unsigned int sr_shift;
102 unsigned int sr_width;
106 * struct owl_padinfo - Actions pinctrl pad info
107 * @pad: pad name of the SoC
108 * @pullctl: pull control register info
109 * @st: schmitt trigger register info
113 struct owl_pullctl *pullctl;
118 * struct owl_pinmux_func - Actions pinctrl mux functions
119 * @name: name of the pinmux function.
120 * @groups: array of pin groups that may select this function.
121 * @ngroups: number of entries in @groups.
123 struct owl_pinmux_func {
125 const char * const *groups;
126 unsigned int ngroups;
130 * struct owl_gpio_port - Actions GPIO port info
131 * @offset: offset of the GPIO port.
132 * @pins: number of pins belongs to the GPIO port.
133 * @outen: offset of the output enable register.
134 * @inen: offset of the input enable register.
135 * @dat: offset of the data register.
136 * @intc_ctl: offset of the interrupt control register.
137 * @intc_pd: offset of the interrupt pending register.
138 * @intc_msk: offset of the interrupt mask register.
139 * @intc_type: offset of the interrupt type register.
141 struct owl_gpio_port {
147 unsigned int intc_ctl;
148 unsigned int intc_pd;
149 unsigned int intc_msk;
150 unsigned int intc_type;
154 * struct owl_pinctrl_soc_data - Actions pin controller driver configuration
155 * @pins: array describing all pins of the pin controller.
156 * @npins: number of entries in @pins.
157 * @functions: array describing all mux functions of this SoC.
158 * @nfunction: number of entries in @functions.
159 * @groups: array describing all pin groups of this SoC.
160 * @ngroups: number of entries in @groups.
161 * @padinfo: array describing the pad info of this SoC.
162 * @ngpios: number of pingroups the driver should expose as GPIOs.
163 * @ports: array describing all GPIO ports of this SoC.
164 * @nports: number of GPIO ports in this SoC.
166 struct owl_pinctrl_soc_data {
167 const struct pinctrl_pin_desc *pins;
169 const struct owl_pinmux_func *functions;
170 unsigned int nfunctions;
171 const struct owl_pingroup *groups;
172 unsigned int ngroups;
173 const struct owl_padinfo *padinfo;
175 const struct owl_gpio_port *ports;
179 int owl_pinctrl_probe(struct platform_device *pdev,
180 struct owl_pinctrl_soc_data *soc_data);
182 #endif /* __PINCTRL_OWL_H__ */