1 // SPDX-License-Identifier: GPL-2.0+
3 * OWL SoC's Pinctrl driver
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
29 #include "../pinctrl-utils.h"
30 #include "pinctrl-owl.h"
33 * struct owl_pinctrl - pinctrl state of the device
35 * @pctrldev: pinctrl handle
37 * @lock: spinlock to protect registers
38 * @soc: reference to soc_data
39 * @base: pinctrl register base address
43 struct pinctrl_dev *pctrldev;
44 struct gpio_chip chip;
47 const struct owl_pinctrl_soc_data *soc;
49 struct irq_chip irq_chip;
54 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
58 reg_val = readl_relaxed(base);
60 reg_val = (reg_val & ~mask) | (val & mask);
62 writel_relaxed(reg_val, base);
65 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
70 tmp = readl_relaxed(pctrl->base + reg);
71 mask = (1 << width) - 1;
73 return (tmp >> bit) & mask;
76 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
81 mask = (1 << width) - 1;
84 owl_update_bits(pctrl->base + reg, mask, (arg << bit));
87 static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
89 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
91 return pctrl->soc->ngroups;
94 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
97 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
99 return pctrl->soc->groups[group].name;
102 static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
104 const unsigned int **pins,
105 unsigned int *num_pins)
107 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
109 *pins = pctrl->soc->groups[group].pads;
110 *num_pins = pctrl->soc->groups[group].npads;
115 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
119 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
121 seq_printf(s, "%s", dev_name(pctrl->dev));
124 static struct pinctrl_ops owl_pinctrl_ops = {
125 .get_groups_count = owl_get_groups_count,
126 .get_group_name = owl_get_group_name,
127 .get_group_pins = owl_get_group_pins,
128 .pin_dbg_show = owl_pin_dbg_show,
129 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
130 .dt_free_map = pinctrl_utils_free_map,
133 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
135 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
137 return pctrl->soc->nfunctions;
140 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
141 unsigned int function)
143 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
145 return pctrl->soc->functions[function].name;
148 static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
149 unsigned int function,
150 const char * const **groups,
151 unsigned int * const num_groups)
153 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
155 *groups = pctrl->soc->functions[function].groups;
156 *num_groups = pctrl->soc->functions[function].ngroups;
161 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
170 for (id = 0; id < g->nfuncs; id++) {
171 if (g->funcs[id] == function)
174 if (WARN_ON(id == g->nfuncs))
177 option_num = (1 << g->mfpctl_width);
181 option_mask = option_num - 1;
182 *mask = (option_mask << g->mfpctl_shift);
183 *val = (id << g->mfpctl_shift);
188 static int owl_set_mux(struct pinctrl_dev *pctrldev,
189 unsigned int function,
192 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
193 const struct owl_pingroup *g;
197 g = &pctrl->soc->groups[group];
199 if (get_group_mfp_mask_val(g, function, &mask, &val))
202 raw_spin_lock_irqsave(&pctrl->lock, flags);
204 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
206 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
211 static struct pinmux_ops owl_pinmux_ops = {
212 .get_functions_count = owl_get_funcs_count,
213 .get_function_name = owl_get_func_name,
214 .get_function_groups = owl_get_func_groups,
215 .set_mux = owl_set_mux,
218 static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
225 case PIN_CONFIG_BIAS_BUS_HOLD:
226 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
227 case PIN_CONFIG_BIAS_PULL_DOWN:
228 case PIN_CONFIG_BIAS_PULL_UP:
231 *reg = info->pullctl->reg;
232 *bit = info->pullctl->shift;
233 *width = info->pullctl->width;
235 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
238 *reg = info->st->reg;
239 *bit = info->st->shift;
240 *width = info->st->width;
249 static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
254 case PIN_CONFIG_BIAS_BUS_HOLD:
255 *arg = OWL_PINCONF_PULL_HOLD;
257 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
258 *arg = OWL_PINCONF_PULL_HIZ;
260 case PIN_CONFIG_BIAS_PULL_DOWN:
261 *arg = OWL_PINCONF_PULL_DOWN;
263 case PIN_CONFIG_BIAS_PULL_UP:
264 *arg = OWL_PINCONF_PULL_UP;
266 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
267 *arg = (*arg >= 1 ? 1 : 0);
276 static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
281 case PIN_CONFIG_BIAS_BUS_HOLD:
282 *arg = *arg == OWL_PINCONF_PULL_HOLD;
284 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
285 *arg = *arg == OWL_PINCONF_PULL_HIZ;
287 case PIN_CONFIG_BIAS_PULL_DOWN:
288 *arg = *arg == OWL_PINCONF_PULL_DOWN;
290 case PIN_CONFIG_BIAS_PULL_UP:
291 *arg = *arg == OWL_PINCONF_PULL_UP;
293 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
303 static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
305 unsigned long *config)
308 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
309 const struct owl_padinfo *info;
310 unsigned int param = pinconf_to_config_param(*config);
311 u32 reg, bit, width, arg;
313 info = &pctrl->soc->padinfo[pin];
315 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
319 arg = owl_read_field(pctrl, reg, bit, width);
321 ret = owl_pad_pinconf_val2arg(info, param, &arg);
325 *config = pinconf_to_config_packed(param, arg);
330 static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
332 unsigned long *configs,
333 unsigned int num_configs)
335 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
336 const struct owl_padinfo *info;
339 u32 reg, bit, width, arg;
342 info = &pctrl->soc->padinfo[pin];
344 for (i = 0; i < num_configs; i++) {
345 param = pinconf_to_config_param(configs[i]);
346 arg = pinconf_to_config_argument(configs[i]);
348 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
352 ret = owl_pad_pinconf_arg2val(info, param, &arg);
356 raw_spin_lock_irqsave(&pctrl->lock, flags);
358 owl_write_field(pctrl, reg, arg, bit, width);
360 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
366 static int owl_group_pinconf_reg(const struct owl_pingroup *g,
373 case PIN_CONFIG_DRIVE_STRENGTH:
378 *width = g->drv_width;
380 case PIN_CONFIG_SLEW_RATE:
385 *width = g->sr_width;
394 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
399 case PIN_CONFIG_DRIVE_STRENGTH:
402 *arg = OWL_PINCONF_DRV_2MA;
405 *arg = OWL_PINCONF_DRV_4MA;
408 *arg = OWL_PINCONF_DRV_8MA;
411 *arg = OWL_PINCONF_DRV_12MA;
417 case PIN_CONFIG_SLEW_RATE:
419 *arg = OWL_PINCONF_SLEW_FAST;
421 *arg = OWL_PINCONF_SLEW_SLOW;
430 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
435 case PIN_CONFIG_DRIVE_STRENGTH:
437 case OWL_PINCONF_DRV_2MA:
440 case OWL_PINCONF_DRV_4MA:
443 case OWL_PINCONF_DRV_8MA:
446 case OWL_PINCONF_DRV_12MA:
453 case PIN_CONFIG_SLEW_RATE:
466 static int owl_group_config_get(struct pinctrl_dev *pctrldev,
468 unsigned long *config)
470 const struct owl_pingroup *g;
471 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
472 unsigned int param = pinconf_to_config_param(*config);
473 u32 reg, bit, width, arg;
476 g = &pctrl->soc->groups[group];
478 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
482 arg = owl_read_field(pctrl, reg, bit, width);
484 ret = owl_group_pinconf_val2arg(g, param, &arg);
488 *config = pinconf_to_config_packed(param, arg);
494 static int owl_group_config_set(struct pinctrl_dev *pctrldev,
496 unsigned long *configs,
497 unsigned int num_configs)
499 const struct owl_pingroup *g;
500 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
503 u32 reg, bit, width, arg;
506 g = &pctrl->soc->groups[group];
508 for (i = 0; i < num_configs; i++) {
509 param = pinconf_to_config_param(configs[i]);
510 arg = pinconf_to_config_argument(configs[i]);
512 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
516 ret = owl_group_pinconf_arg2val(g, param, &arg);
520 /* Update register */
521 raw_spin_lock_irqsave(&pctrl->lock, flags);
523 owl_write_field(pctrl, reg, arg, bit, width);
525 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
531 static const struct pinconf_ops owl_pinconf_ops = {
533 .pin_config_get = owl_pin_config_get,
534 .pin_config_set = owl_pin_config_set,
535 .pin_config_group_get = owl_group_config_get,
536 .pin_config_group_set = owl_group_config_set,
539 static struct pinctrl_desc owl_pinctrl_desc = {
540 .pctlops = &owl_pinctrl_ops,
541 .pmxops = &owl_pinmux_ops,
542 .confops = &owl_pinconf_ops,
543 .owner = THIS_MODULE,
546 static const struct owl_gpio_port *
547 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
549 unsigned int start = 0, i;
551 for (i = 0; i < pctrl->soc->nports; i++) {
552 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
554 if (*pin >= start && *pin < start + port->pins) {
565 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
569 val = readl_relaxed(base);
576 writel_relaxed(val, base);
579 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
581 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
582 const struct owl_gpio_port *port;
583 void __iomem *gpio_base;
586 port = owl_gpio_get_port(pctrl, &offset);
587 if (WARN_ON(port == NULL))
590 gpio_base = pctrl->base + port->offset;
593 * GPIOs have higher priority over other modules, so either setting
594 * them as OUT or IN is sufficient
596 raw_spin_lock_irqsave(&pctrl->lock, flags);
597 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
598 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
603 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
605 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
606 const struct owl_gpio_port *port;
607 void __iomem *gpio_base;
610 port = owl_gpio_get_port(pctrl, &offset);
611 if (WARN_ON(port == NULL))
614 gpio_base = pctrl->base + port->offset;
616 raw_spin_lock_irqsave(&pctrl->lock, flags);
617 /* disable gpio output */
618 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
620 /* disable gpio input */
621 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
622 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
625 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
627 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
628 const struct owl_gpio_port *port;
629 void __iomem *gpio_base;
633 port = owl_gpio_get_port(pctrl, &offset);
634 if (WARN_ON(port == NULL))
637 gpio_base = pctrl->base + port->offset;
639 raw_spin_lock_irqsave(&pctrl->lock, flags);
640 val = readl_relaxed(gpio_base + port->dat);
641 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
643 return !!(val & BIT(offset));
646 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
648 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
649 const struct owl_gpio_port *port;
650 void __iomem *gpio_base;
653 port = owl_gpio_get_port(pctrl, &offset);
654 if (WARN_ON(port == NULL))
657 gpio_base = pctrl->base + port->offset;
659 raw_spin_lock_irqsave(&pctrl->lock, flags);
660 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
661 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
664 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
666 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
667 const struct owl_gpio_port *port;
668 void __iomem *gpio_base;
671 port = owl_gpio_get_port(pctrl, &offset);
672 if (WARN_ON(port == NULL))
675 gpio_base = pctrl->base + port->offset;
677 raw_spin_lock_irqsave(&pctrl->lock, flags);
678 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
679 owl_gpio_update_reg(gpio_base + port->inen, offset, true);
680 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
685 static int owl_gpio_direction_output(struct gpio_chip *chip,
686 unsigned int offset, int value)
688 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
689 const struct owl_gpio_port *port;
690 void __iomem *gpio_base;
693 port = owl_gpio_get_port(pctrl, &offset);
694 if (WARN_ON(port == NULL))
697 gpio_base = pctrl->base + port->offset;
699 raw_spin_lock_irqsave(&pctrl->lock, flags);
700 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
701 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
702 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
703 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
708 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
710 const struct owl_gpio_port *port;
711 void __iomem *gpio_base;
713 unsigned int offset, value, irq_type = 0;
716 case IRQ_TYPE_EDGE_BOTH:
718 * Since the hardware doesn't support interrupts on both edges,
719 * emulate it in the software by setting the single edge
720 * interrupt and switching to the opposite edge while ACKing
723 if (owl_gpio_get(&pctrl->chip, gpio))
724 irq_type = OWL_GPIO_INT_EDGE_FALLING;
726 irq_type = OWL_GPIO_INT_EDGE_RISING;
729 case IRQ_TYPE_EDGE_RISING:
730 irq_type = OWL_GPIO_INT_EDGE_RISING;
733 case IRQ_TYPE_EDGE_FALLING:
734 irq_type = OWL_GPIO_INT_EDGE_FALLING;
737 case IRQ_TYPE_LEVEL_HIGH:
738 irq_type = OWL_GPIO_INT_LEVEL_HIGH;
741 case IRQ_TYPE_LEVEL_LOW:
742 irq_type = OWL_GPIO_INT_LEVEL_LOW;
749 port = owl_gpio_get_port(pctrl, &gpio);
750 if (WARN_ON(port == NULL))
753 gpio_base = pctrl->base + port->offset;
755 raw_spin_lock_irqsave(&pctrl->lock, flags);
757 offset = (gpio < 16) ? 4 : 0;
758 value = readl_relaxed(gpio_base + port->intc_type + offset);
759 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
760 value |= irq_type << ((gpio % 16) * 2);
761 writel_relaxed(value, gpio_base + port->intc_type + offset);
763 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
766 static void owl_gpio_irq_mask(struct irq_data *data)
768 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
769 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
770 const struct owl_gpio_port *port;
771 void __iomem *gpio_base;
773 unsigned int gpio = data->hwirq;
776 port = owl_gpio_get_port(pctrl, &gpio);
777 if (WARN_ON(port == NULL))
780 gpio_base = pctrl->base + port->offset;
782 raw_spin_lock_irqsave(&pctrl->lock, flags);
784 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
786 /* disable port interrupt if no interrupt pending bit is active */
787 val = readl_relaxed(gpio_base + port->intc_msk);
789 owl_gpio_update_reg(gpio_base + port->intc_ctl,
790 OWL_GPIO_CTLR_ENABLE, false);
792 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
795 static void owl_gpio_irq_unmask(struct irq_data *data)
797 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
798 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
799 const struct owl_gpio_port *port;
800 void __iomem *gpio_base;
802 unsigned int gpio = data->hwirq;
805 port = owl_gpio_get_port(pctrl, &gpio);
806 if (WARN_ON(port == NULL))
809 gpio_base = pctrl->base + port->offset;
810 raw_spin_lock_irqsave(&pctrl->lock, flags);
812 /* enable port interrupt */
813 value = readl_relaxed(gpio_base + port->intc_ctl);
814 value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
815 writel_relaxed(value, gpio_base + port->intc_ctl);
817 /* enable GPIO interrupt */
818 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
820 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
823 static void owl_gpio_irq_ack(struct irq_data *data)
825 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
826 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
827 const struct owl_gpio_port *port;
828 void __iomem *gpio_base;
830 unsigned int gpio = data->hwirq;
833 * Switch the interrupt edge to the opposite edge of the interrupt
834 * which got triggered for the case of emulating both edges
836 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
837 if (owl_gpio_get(gc, gpio))
838 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
840 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
843 port = owl_gpio_get_port(pctrl, &gpio);
844 if (WARN_ON(port == NULL))
847 gpio_base = pctrl->base + port->offset;
849 raw_spin_lock_irqsave(&pctrl->lock, flags);
851 owl_gpio_update_reg(gpio_base + port->intc_ctl,
852 OWL_GPIO_CTLR_PENDING, true);
854 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
857 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
859 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
860 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
862 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
863 irq_set_handler_locked(data, handle_level_irq);
865 irq_set_handler_locked(data, handle_edge_irq);
867 irq_set_type(pctrl, data->hwirq, type);
872 static void owl_gpio_irq_handler(struct irq_desc *desc)
874 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
875 struct irq_chip *chip = irq_desc_get_chip(desc);
876 struct irq_domain *domain = pctrl->chip.irq.domain;
877 unsigned int parent = irq_desc_get_irq(desc);
878 const struct owl_gpio_port *port;
880 unsigned int pin, irq, offset = 0, i;
881 unsigned long pending_irq;
883 chained_irq_enter(chip, desc);
885 for (i = 0; i < pctrl->soc->nports; i++) {
886 port = &pctrl->soc->ports[i];
887 base = pctrl->base + port->offset;
889 /* skip ports that are not associated with this irq */
890 if (parent != pctrl->irq[i])
893 pending_irq = readl_relaxed(base + port->intc_pd);
895 for_each_set_bit(pin, &pending_irq, port->pins) {
896 irq = irq_find_mapping(domain, offset + pin);
897 generic_handle_irq(irq);
899 /* clear pending interrupt */
900 owl_gpio_update_reg(base + port->intc_pd, pin, true);
904 offset += port->pins;
907 chained_irq_exit(chip, desc);
910 static int owl_gpio_init(struct owl_pinctrl *pctrl)
912 struct gpio_chip *chip;
913 struct gpio_irq_chip *gpio_irq;
914 int ret, i, j, offset;
918 chip->ngpio = pctrl->soc->ngpios;
919 chip->label = dev_name(pctrl->dev);
920 chip->parent = pctrl->dev;
921 chip->owner = THIS_MODULE;
922 chip->of_node = pctrl->dev->of_node;
924 pctrl->irq_chip.name = chip->of_node->name;
925 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
926 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
927 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
928 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
930 gpio_irq = &chip->irq;
931 gpio_irq->chip = &pctrl->irq_chip;
932 gpio_irq->handler = handle_simple_irq;
933 gpio_irq->default_type = IRQ_TYPE_NONE;
934 gpio_irq->parent_handler = owl_gpio_irq_handler;
935 gpio_irq->parent_handler_data = pctrl;
936 gpio_irq->num_parents = pctrl->num_irq;
937 gpio_irq->parents = pctrl->irq;
939 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
940 sizeof(*gpio_irq->map), GFP_KERNEL);
944 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
945 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
947 for (j = 0; j < port->pins; j++)
948 gpio_irq->map[offset + j] = gpio_irq->parents[i];
950 offset += port->pins;
953 ret = gpiochip_add_data(&pctrl->chip, pctrl);
955 dev_err(pctrl->dev, "failed to register gpiochip\n");
962 int owl_pinctrl_probe(struct platform_device *pdev,
963 struct owl_pinctrl_soc_data *soc_data)
965 struct resource *res;
966 struct owl_pinctrl *pctrl;
969 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
973 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
974 pctrl->base = devm_ioremap_resource(&pdev->dev, res);
975 if (IS_ERR(pctrl->base))
976 return PTR_ERR(pctrl->base);
978 /* enable GPIO/MFP clock */
979 pctrl->clk = devm_clk_get(&pdev->dev, NULL);
980 if (IS_ERR(pctrl->clk)) {
981 dev_err(&pdev->dev, "no clock defined\n");
982 return PTR_ERR(pctrl->clk);
985 ret = clk_prepare_enable(pctrl->clk);
987 dev_err(&pdev->dev, "clk enable failed\n");
991 raw_spin_lock_init(&pctrl->lock);
993 owl_pinctrl_desc.name = dev_name(&pdev->dev);
994 owl_pinctrl_desc.pins = soc_data->pins;
995 owl_pinctrl_desc.npins = soc_data->npins;
997 pctrl->chip.direction_input = owl_gpio_direction_input;
998 pctrl->chip.direction_output = owl_gpio_direction_output;
999 pctrl->chip.get = owl_gpio_get;
1000 pctrl->chip.set = owl_gpio_set;
1001 pctrl->chip.request = owl_gpio_request;
1002 pctrl->chip.free = owl_gpio_free;
1004 pctrl->soc = soc_data;
1005 pctrl->dev = &pdev->dev;
1007 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
1008 &owl_pinctrl_desc, pctrl);
1009 if (IS_ERR(pctrl->pctrldev)) {
1010 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
1011 ret = PTR_ERR(pctrl->pctrldev);
1015 ret = platform_irq_count(pdev);
1019 pctrl->num_irq = ret;
1021 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
1022 sizeof(*pctrl->irq), GFP_KERNEL);
1028 for (i = 0; i < pctrl->num_irq ; i++) {
1029 ret = platform_get_irq(pdev, i);
1032 pctrl->irq[i] = ret;
1035 ret = owl_gpio_init(pctrl);
1039 platform_set_drvdata(pdev, pctrl);
1044 clk_disable_unprepare(pctrl->clk);