1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * This driver is tested for USB, SATA and Display Port currently.
12 * Other controllers PCIe and SGMII should also work but that is
13 * experimental as of now.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
33 #define L0_TX_ANA_TM_18 0x0048
34 #define L0_TX_ANA_TM_118 0x01d8
35 #define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
37 /* DN Resistor calibration code parameters */
38 #define L0_TXPMA_ST_3 0x0b0c
39 #define L0_DN_CALIB_CODE 0x3f
41 /* PMA control parameters */
42 #define L0_TXPMD_TM_45 0x0cb4
43 #define L0_TXPMD_TM_48 0x0cc0
44 #define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
45 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
46 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
47 #define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
48 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
49 #define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
51 /* PCS control parameters */
52 #define L0_TM_DIG_6 0x106c
53 #define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
54 #define L0_TX_DIG_61 0x00f4
55 #define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f
57 /* PLL Test Mode register parameters */
58 #define L0_TM_PLL_DIG_37 0x2094
59 #define L0_TM_COARSE_CODE_LIMIT 0x10
61 /* PLL SSC step size offsets */
62 #define L0_PLL_SS_STEPS_0_LSB 0x2368
63 #define L0_PLL_SS_STEPS_1_MSB 0x236c
64 #define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
65 #define L0_PLL_SS_STEP_SIZE_1 0x2374
66 #define L0_PLL_SS_STEP_SIZE_2 0x2378
67 #define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
68 #define L0_PLL_STATUS_READ_1 0x23e4
70 /* SSC step size parameters */
71 #define STEP_SIZE_0_MASK 0xff
72 #define STEP_SIZE_1_MASK 0xff
73 #define STEP_SIZE_2_MASK 0xff
74 #define STEP_SIZE_3_MASK 0x3
75 #define STEP_SIZE_SHIFT 8
76 #define FORCE_STEP_SIZE 0x10
77 #define FORCE_STEPS 0x20
78 #define STEPS_0_MASK 0xff
79 #define STEPS_1_MASK 0x07
81 /* Reference clock selection parameters */
82 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
83 #define L0_REF_CLK_SEL_MASK 0x8f
85 /* Calibration digital logic parameters */
86 #define L3_TM_CALIB_DIG19 0xec4c
87 #define L3_CALIB_DONE_STATUS 0xef14
88 #define L3_TM_CALIB_DIG18 0xec48
89 #define L3_TM_CALIB_DIG19_NSW 0x07
90 #define L3_TM_CALIB_DIG18_NSW 0xe0
91 #define L3_TM_OVERRIDE_NSW_CODE 0x20
92 #define L3_CALIB_DONE 0x02
93 #define L3_NSW_SHIFT 5
94 #define L3_NSW_PIPE_SHIFT 4
95 #define L3_NSW_CALIB_SHIFT 3
97 #define PHY_REG_OFFSET 0x4000
103 /* Refclk selection parameters */
104 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
105 #define PLL_FREQ_MASK 0x1f
106 #define PLL_STATUS_LOCKED 0x10
108 /* Inter Connect Matrix parameters */
109 #define ICM_CFG0 0x10010
110 #define ICM_CFG1 0x10014
111 #define ICM_CFG0_L0_MASK 0x07
112 #define ICM_CFG0_L1_MASK 0x70
113 #define ICM_CFG1_L2_MASK 0x07
114 #define ICM_CFG2_L3_MASK 0x70
115 #define ICM_CFG_SHIFT 4
117 /* Inter Connect Matrix allowed protocols */
118 #define ICM_PROTOCOL_PD 0x0
119 #define ICM_PROTOCOL_PCIE 0x1
120 #define ICM_PROTOCOL_SATA 0x2
121 #define ICM_PROTOCOL_USB 0x3
122 #define ICM_PROTOCOL_DP 0x4
123 #define ICM_PROTOCOL_SGMII 0x5
125 /* Test Mode common reset control parameters */
126 #define TM_CMN_RST 0x10018
127 #define TM_CMN_RST_EN 0x1
128 #define TM_CMN_RST_SET 0x2
129 #define TM_CMN_RST_MASK 0x3
131 /* Bus width parameters */
132 #define TX_PROT_BUS_WIDTH 0x10040
133 #define RX_PROT_BUS_WIDTH 0x10044
134 #define PROT_BUS_WIDTH_10 0x0
135 #define PROT_BUS_WIDTH_20 0x1
136 #define PROT_BUS_WIDTH_40 0x2
137 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
138 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
140 /* Number of GT lanes */
143 /* SIOU SATA control register */
144 #define SATA_CONTROL_OFFSET 0x0100
146 /* Total number of controllers */
147 #define CONTROLLERS_PER_LANE 5
149 /* Protocol Type parameters */
150 #define XPSGTR_TYPE_USB0 0 /* USB controller 0 */
151 #define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
153 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
154 #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
155 #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
156 #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
157 #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
158 #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
159 #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
160 #define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
161 #define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
162 #define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */
163 #define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */
166 #define TIMEOUT_US 1000
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
172 * @refclk_rate: PLL reference clock frequency
173 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
174 * @steps: number of steps of SSC (Spread Spectrum Clock)
175 * @step_size: step size of each step
185 * struct xpsgtr_phy - representation of a lane
186 * @phy: pointer to the kernel PHY device
187 * @type: controller which uses this lane
189 * @protocol: protocol in which the lane operates
190 * @skip_phy_init: skip phy_init() if true
191 * @dev: pointer to the xpsgtr_dev instance
192 * @refclk: reference clock index
200 struct xpsgtr_dev *dev;
205 * struct xpsgtr_dev - representation of a ZynMP GT device
206 * @dev: pointer to device
207 * @serdes: serdes base address
208 * @siou: siou base address
209 * @gtr_mutex: mutex for locking
211 * @refclk_sscs: spread spectrum settings for the reference clocks
212 * @tx_term_fix: fix for GT issue
213 * @saved_icm_cfg0: stored value of ICM CFG0 register
214 * @saved_icm_cfg1: stored value of ICM CFG1 register
218 void __iomem *serdes;
220 struct mutex gtr_mutex; /* mutex for locking */
221 struct xpsgtr_phy phys[NUM_LANES];
222 const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
224 unsigned int saved_icm_cfg0;
225 unsigned int saved_icm_cfg1;
232 /* lookup table to hold all settings needed for a ref clock frequency */
233 static const struct xpsgtr_ssc ssc_lookup[] = {
234 { 19200000, 0x05, 608, 264020 },
235 { 20000000, 0x06, 634, 243454 },
236 { 24000000, 0x07, 760, 168973 },
237 { 26000000, 0x08, 824, 143860 },
238 { 27000000, 0x09, 856, 86551 },
239 { 38400000, 0x0a, 1218, 65896 },
240 { 40000000, 0x0b, 634, 243454 },
241 { 52000000, 0x0c, 824, 143860 },
242 { 100000000, 0x0d, 1058, 87533 },
243 { 108000000, 0x0e, 856, 86551 },
244 { 125000000, 0x0f, 992, 119497 },
245 { 135000000, 0x10, 1070, 55393 },
246 { 150000000, 0x11, 792, 187091 }
253 static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
255 return readl(gtr_dev->serdes + reg);
258 static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
260 writel(value, gtr_dev->serdes + reg);
263 static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
266 u32 value = xpsgtr_read(gtr_dev, reg);
270 xpsgtr_write(gtr_dev, reg, value);
273 static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
275 void __iomem *addr = gtr_phy->dev->serdes
276 + gtr_phy->lane * PHY_REG_OFFSET + reg;
281 static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
284 void __iomem *addr = gtr_phy->dev->serdes
285 + gtr_phy->lane * PHY_REG_OFFSET + reg;
290 static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
291 u32 reg, u32 clr, u32 set)
293 void __iomem *addr = gtr_phy->dev->serdes
294 + gtr_phy->lane * PHY_REG_OFFSET + reg;
296 writel((readl(addr) & ~clr) | set, addr);
300 * Hardware Configuration
303 /* Wait for the PLL to lock (with a timeout). */
304 static int xpsgtr_wait_pll_lock(struct phy *phy)
306 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
307 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
308 unsigned int timeout = TIMEOUT_US;
311 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
314 u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
316 if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
321 if (--timeout == 0) {
329 if (ret == -ETIMEDOUT)
330 dev_err(gtr_dev->dev,
331 "lane %u (type %u, protocol %u): PLL lock timeout\n",
332 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
337 /* Configure PLL and spread-sprectrum clock. */
338 static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
340 const struct xpsgtr_ssc *ssc;
343 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
344 step_size = ssc->step_size;
346 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
347 PLL_FREQ_MASK, ssc->pll_ref_clk);
349 /* Enable lane clock sharing, if required */
350 if (gtr_phy->refclk != gtr_phy->lane) {
351 /* Lane3 Ref Clock Selection Register */
352 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
353 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
356 /* SSC step size [7:0] */
357 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
358 STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
360 /* SSC step size [15:8] */
361 step_size >>= STEP_SIZE_SHIFT;
362 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
363 STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
365 /* SSC step size [23:16] */
366 step_size >>= STEP_SIZE_SHIFT;
367 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
368 STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
370 /* SSC steps [7:0] */
371 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
372 STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
374 /* SSC steps [10:8] */
375 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
377 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
379 /* SSC step size [24:25] */
380 step_size >>= STEP_SIZE_SHIFT;
381 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
382 STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
383 FORCE_STEP_SIZE | FORCE_STEPS);
386 /* Configure the lane protocol. */
387 static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
389 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
390 u8 protocol = gtr_phy->protocol;
392 switch (gtr_phy->lane) {
394 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
397 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
398 protocol << ICM_CFG_SHIFT);
401 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
404 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
405 protocol << ICM_CFG_SHIFT);
408 /* We already checked 0 <= lane <= 3 */
413 /* Bypass (de)scrambler and 8b/10b decoder and encoder. */
414 static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
416 xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
417 xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
420 /* DP-specific initialization. */
421 static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
423 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
424 L0_TXPMD_TM_45_OVER_DP_MAIN |
425 L0_TXPMD_TM_45_ENABLE_DP_MAIN |
426 L0_TXPMD_TM_45_OVER_DP_POST1 |
427 L0_TXPMD_TM_45_OVER_DP_POST2 |
428 L0_TXPMD_TM_45_ENABLE_DP_POST2);
429 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
430 L0_TX_ANA_TM_118_FORCE_17_0);
433 /* SATA-specific initialization. */
434 static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
436 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
438 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
440 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
443 /* SGMII-specific initialization. */
444 static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
446 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
447 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
448 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
450 /* Set SGMII protocol TX and RX bus width to 10 bits. */
451 xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
452 xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
454 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
457 /* Configure TX de-emphasis and margining for DP. */
458 static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
459 unsigned int voltage)
461 static const u8 voltage_swing[4][4] = {
462 { 0x2a, 0x27, 0x24, 0x20 },
463 { 0x27, 0x23, 0x20, 0xff },
464 { 0x24, 0x20, 0xff, 0xff },
465 { 0xff, 0xff, 0xff, 0xff }
467 static const u8 pre_emphasis[4][4] = {
468 { 0x02, 0x02, 0x02, 0x02 },
469 { 0x01, 0x01, 0x01, 0xff },
470 { 0x00, 0x00, 0xff, 0xff },
471 { 0xff, 0xff, 0xff, 0xff }
474 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
475 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
482 static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
485 * As USB may save the snapshot of the states during hibernation, doing
486 * phy_init() will put the USB controller into reset, resulting in the
487 * losing of the saved snapshot. So try to avoid phy_init() for USB
488 * except when gtr_phy->skip_phy_init is false (this happens when FPD is
489 * shutdown during suspend or when gt lane is changed from current one)
491 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
498 * There is a functional issue in the GT. The TX termination resistance can be
499 * out of spec due to a issue in the calibration logic. This is the workaround
500 * to fix it, required for XCZU9EG silicon.
502 static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
504 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
505 u32 timeout = TIMEOUT_US;
508 /* Enabling Test Mode control for CMN Rest */
509 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
511 /* Set Test Mode reset */
512 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
514 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
515 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
518 * As a part of work around sequence for PMOS calibration fix,
519 * we need to configure any lane ICM_CFG to valid protocol. This
520 * will deassert the CMN_Resetn signal.
522 xpsgtr_lane_set_protocol(gtr_phy);
524 /* Clear Test Mode reset */
525 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
527 dev_dbg(gtr_dev->dev, "calibrating...\n");
530 u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
532 if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
536 dev_err(gtr_dev->dev, "calibration time out\n");
541 } while (timeout > 0);
543 dev_dbg(gtr_dev->dev, "calibration done\n");
545 /* Reading NMOS Register Code */
546 nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
548 /* Set Test Mode reset */
549 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
551 /* Writing NMOS register values back [5:3] */
552 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
554 /* Writing NMOS register value [2:0] */
555 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
556 ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
557 (1 << L3_NSW_PIPE_SHIFT));
559 /* Clear Test Mode reset */
560 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
565 static int xpsgtr_phy_init(struct phy *phy)
567 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
568 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
571 mutex_lock(>r_dev->gtr_mutex);
573 /* Skip initialization if not required. */
574 if (!xpsgtr_phy_init_required(gtr_phy))
577 if (gtr_dev->tx_term_fix) {
578 ret = xpsgtr_phy_tx_term_fix(gtr_phy);
582 gtr_dev->tx_term_fix = false;
585 /* Enable coarse code saturation limiting logic. */
586 xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
589 * Configure the PLL, the lane protocol, and perform protocol-specific
592 xpsgtr_configure_pll(gtr_phy);
593 xpsgtr_lane_set_protocol(gtr_phy);
595 switch (gtr_phy->protocol) {
596 case ICM_PROTOCOL_DP:
597 xpsgtr_phy_init_dp(gtr_phy);
600 case ICM_PROTOCOL_SATA:
601 xpsgtr_phy_init_sata(gtr_phy);
604 case ICM_PROTOCOL_SGMII:
605 xpsgtr_phy_init_sgmii(gtr_phy);
610 mutex_unlock(>r_dev->gtr_mutex);
614 static int xpsgtr_phy_exit(struct phy *phy)
616 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
618 gtr_phy->skip_phy_init = false;
623 static int xpsgtr_phy_power_on(struct phy *phy)
625 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
629 * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
630 * cumulating waits for both lanes. The user is expected to initialize
633 if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
634 gtr_phy->type == XPSGTR_TYPE_DP_0)
635 ret = xpsgtr_wait_pll_lock(phy);
640 static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
642 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
644 if (gtr_phy->protocol != ICM_PROTOCOL_DP)
647 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
652 static const struct phy_ops xpsgtr_phyops = {
653 .init = xpsgtr_phy_init,
654 .exit = xpsgtr_phy_exit,
655 .power_on = xpsgtr_phy_power_on,
656 .configure = xpsgtr_phy_configure,
657 .owner = THIS_MODULE,
664 /* Set the lane type and protocol based on the PHY type and instance number. */
665 static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
666 unsigned int phy_instance)
668 unsigned int num_phy_types;
669 const int *phy_types;
672 case PHY_TYPE_SATA: {
673 static const int types[] = {
679 num_phy_types = ARRAY_SIZE(types);
680 gtr_phy->protocol = ICM_PROTOCOL_SATA;
683 case PHY_TYPE_USB3: {
684 static const int types[] = {
690 num_phy_types = ARRAY_SIZE(types);
691 gtr_phy->protocol = ICM_PROTOCOL_USB;
695 static const int types[] = {
701 num_phy_types = ARRAY_SIZE(types);
702 gtr_phy->protocol = ICM_PROTOCOL_DP;
705 case PHY_TYPE_PCIE: {
706 static const int types[] = {
714 num_phy_types = ARRAY_SIZE(types);
715 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
718 case PHY_TYPE_SGMII: {
719 static const int types[] = {
727 num_phy_types = ARRAY_SIZE(types);
728 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
735 if (phy_instance >= num_phy_types)
738 gtr_phy->type = phy_types[phy_instance];
743 * Valid combinations of controllers and lanes (Interconnect Matrix).
745 static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
746 { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
747 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
748 { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
749 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
750 { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
751 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
752 { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
753 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
756 /* Translate OF phandle and args to PHY instance. */
757 static struct phy *xpsgtr_xlate(struct device *dev,
758 struct of_phandle_args *args)
760 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
761 struct xpsgtr_phy *gtr_phy;
762 unsigned int phy_instance;
763 unsigned int phy_lane;
764 unsigned int phy_type;
769 if (args->args_count != 4) {
770 dev_err(dev, "Invalid number of cells in 'phy' property\n");
771 return ERR_PTR(-EINVAL);
775 * Get the PHY parameters from the OF arguments and derive the lane
778 phy_lane = args->args[0];
779 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
780 dev_err(dev, "Invalid lane number %u\n", phy_lane);
781 return ERR_PTR(-ENODEV);
784 gtr_phy = >r_dev->phys[phy_lane];
785 phy_type = args->args[1];
786 phy_instance = args->args[2];
788 ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
790 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
794 refclk = args->args[3];
795 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
796 !gtr_dev->refclk_sscs[refclk]) {
797 dev_err(dev, "Invalid reference clock number %u\n", refclk);
798 return ERR_PTR(-EINVAL);
801 gtr_phy->refclk = refclk;
804 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
805 * is allowed to operate on the lane.
807 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
808 if (icm_matrix[phy_lane][i] == gtr_phy->type)
812 return ERR_PTR(-EINVAL);
819 static int __maybe_unused xpsgtr_suspend(struct device *dev)
821 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
823 /* Save the snapshot ICM_CFG registers. */
824 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
825 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
830 static int __maybe_unused xpsgtr_resume(struct device *dev)
832 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
833 unsigned int icm_cfg0, icm_cfg1;
837 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
838 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
840 /* Return if no GT lanes got configured before suspend. */
841 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
844 /* Check if the ICM configurations changed after suspend. */
845 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
846 icm_cfg1 == gtr_dev->saved_icm_cfg1)
847 skip_phy_init = true;
849 skip_phy_init = false;
851 /* Update the skip_phy_init for all gtr_phy instances. */
852 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
853 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
858 static const struct dev_pm_ops xpsgtr_pm_ops = {
859 SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume)
863 * Probe & Platform Driver
866 static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
870 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {
876 snprintf(name, sizeof(name), "ref%u", refclk);
877 clk = devm_clk_get_optional(gtr_dev->dev, name);
879 if (PTR_ERR(clk) != -EPROBE_DEFER)
880 dev_err(gtr_dev->dev,
881 "Failed to get reference clock %u: %ld\n",
882 refclk, PTR_ERR(clk));
890 * Get the spread spectrum (SSC) settings for the reference
893 rate = clk_get_rate(clk);
895 for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
896 if (rate == ssc_lookup[i].refclk_rate) {
897 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
902 if (i == ARRAY_SIZE(ssc_lookup)) {
903 dev_err(gtr_dev->dev,
904 "Invalid rate %lu for reference clock %u\n",
913 static int xpsgtr_probe(struct platform_device *pdev)
915 struct device_node *np = pdev->dev.of_node;
916 struct xpsgtr_dev *gtr_dev;
917 struct phy_provider *provider;
921 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
925 gtr_dev->dev = &pdev->dev;
926 platform_set_drvdata(pdev, gtr_dev);
928 mutex_init(>r_dev->gtr_mutex);
930 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
931 gtr_dev->tx_term_fix =
932 of_property_read_bool(np, "xlnx,tx-termination-fix");
934 /* Acquire resources. */
935 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
936 if (IS_ERR(gtr_dev->serdes))
937 return PTR_ERR(gtr_dev->serdes);
939 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
940 if (IS_ERR(gtr_dev->siou))
941 return PTR_ERR(gtr_dev->siou);
943 ret = xpsgtr_get_ref_clocks(gtr_dev);
948 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
949 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port];
952 gtr_phy->lane = port;
953 gtr_phy->dev = gtr_dev;
955 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
957 dev_err(&pdev->dev, "failed to create PHY\n");
962 phy_set_drvdata(phy, gtr_phy);
965 /* Register the PHY provider. */
966 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
967 if (IS_ERR(provider)) {
968 dev_err(&pdev->dev, "registering provider failed\n");
969 return PTR_ERR(provider);
974 static const struct of_device_id xpsgtr_of_match[] = {
975 { .compatible = "xlnx,zynqmp-psgtr", },
976 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
979 MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
981 static struct platform_driver xpsgtr_driver = {
982 .probe = xpsgtr_probe,
984 .name = "xilinx-psgtr",
985 .of_match_table = xpsgtr_of_match,
986 .pm = &xpsgtr_pm_ops,
990 module_platform_driver(xpsgtr_driver);
992 MODULE_AUTHOR("Xilinx Inc.");
993 MODULE_LICENSE("GPL v2");
994 MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");