1 // SPDX-License-Identifier: GPL-2.0
3 * Wrapper driver for SERDES used in J721E
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/gpio.h>
13 #include <linux/gpio/consumer.h>
15 #include <linux/module.h>
16 #include <linux/mux/consumer.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/reset-controller.h>
24 #define WIZ_SERDES_CTRL 0x404
25 #define WIZ_SERDES_TOP_CTRL 0x408
26 #define WIZ_SERDES_RST 0x40c
27 #define WIZ_SERDES_TYPEC 0x410
28 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
30 #define WIZ_MAX_LANES 4
31 #define WIZ_MUX_NUM_CLOCKS 3
32 #define WIZ_DIV_NUM_CLOCKS_16G 2
33 #define WIZ_DIV_NUM_CLOCKS_10G 1
35 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
37 enum wiz_lane_standard_mode {
44 enum wiz_refclk_mux_sel {
50 enum wiz_refclk_div_sel {
55 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
56 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
57 static const struct reg_field pll1_refclk_mux_sel =
58 REG_FIELD(WIZ_SERDES_RST, 29, 29);
59 static const struct reg_field pll0_refclk_mux_sel =
60 REG_FIELD(WIZ_SERDES_RST, 28, 28);
61 static const struct reg_field refclk_dig_sel_16g =
62 REG_FIELD(WIZ_SERDES_RST, 24, 25);
63 static const struct reg_field refclk_dig_sel_10g =
64 REG_FIELD(WIZ_SERDES_RST, 24, 24);
65 static const struct reg_field pma_cmn_refclk_int_mode =
66 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
67 static const struct reg_field pma_cmn_refclk_mode =
68 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
69 static const struct reg_field pma_cmn_refclk_dig_div =
70 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
71 static const struct reg_field pma_cmn_refclk1_dig_div =
72 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
74 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
75 REG_FIELD(WIZ_LANECTL(0), 30, 31),
76 REG_FIELD(WIZ_LANECTL(1), 30, 31),
77 REG_FIELD(WIZ_LANECTL(2), 30, 31),
78 REG_FIELD(WIZ_LANECTL(3), 30, 31),
81 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
83 static const struct reg_field p_align[WIZ_MAX_LANES] = {
84 REG_FIELD(WIZ_LANECTL(0), 29, 29),
85 REG_FIELD(WIZ_LANECTL(1), 29, 29),
86 REG_FIELD(WIZ_LANECTL(2), 29, 29),
87 REG_FIELD(WIZ_LANECTL(3), 29, 29),
90 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
91 REG_FIELD(WIZ_LANECTL(0), 28, 28),
92 REG_FIELD(WIZ_LANECTL(1), 28, 28),
93 REG_FIELD(WIZ_LANECTL(2), 28, 28),
94 REG_FIELD(WIZ_LANECTL(3), 28, 28),
97 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
98 REG_FIELD(WIZ_LANECTL(0), 24, 25),
99 REG_FIELD(WIZ_LANECTL(1), 24, 25),
100 REG_FIELD(WIZ_LANECTL(2), 24, 25),
101 REG_FIELD(WIZ_LANECTL(3), 24, 25),
104 static const struct reg_field typec_ln10_swap =
105 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
109 struct regmap_field *field;
111 struct clk_init_data clk_data;
114 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
116 struct wiz_clk_divider {
118 struct regmap_field *field;
119 const struct clk_div_table *table;
120 struct clk_init_data clk_data;
123 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
125 struct wiz_clk_mux_sel {
126 struct regmap_field *field;
128 const char *node_name;
131 struct wiz_clk_div_sel {
132 struct regmap_field *field;
133 const struct clk_div_table *table;
134 const char *node_name;
137 static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
140 * Mux value to be configured for each of the input clocks
141 * in the order populated in device tree
144 .node_name = "pll0-refclk",
148 .node_name = "pll1-refclk",
151 .table = { 1, 3, 0, 2 },
152 .node_name = "refclk-dig",
156 static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
159 * Mux value to be configured for each of the input clocks
160 * in the order populated in device tree
163 .node_name = "pll0-refclk",
167 .node_name = "pll1-refclk",
171 .node_name = "refclk-dig",
175 static const struct clk_div_table clk_div_table[] = {
176 { .val = 0, .div = 1, },
177 { .val = 1, .div = 2, },
178 { .val = 2, .div = 4, },
179 { .val = 3, .div = 8, },
183 static struct wiz_clk_div_sel clk_div_sel[] = {
185 .table = clk_div_table,
186 .node_name = "cmn-refclk-dig-div",
189 .table = clk_div_table,
190 .node_name = "cmn-refclk1-dig-div",
199 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
200 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
203 struct regmap *regmap;
205 struct wiz_clk_mux_sel *clk_mux_sel;
206 struct wiz_clk_div_sel *clk_div_sel;
207 unsigned int clk_div_sel_num;
208 struct regmap_field *por_en;
209 struct regmap_field *phy_reset_n;
210 struct regmap_field *p_enable[WIZ_MAX_LANES];
211 struct regmap_field *p_align[WIZ_MAX_LANES];
212 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
213 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
214 struct regmap_field *pma_cmn_refclk_int_mode;
215 struct regmap_field *pma_cmn_refclk_mode;
216 struct regmap_field *pma_cmn_refclk_dig_div;
217 struct regmap_field *pma_cmn_refclk1_dig_div;
218 struct regmap_field *typec_ln10_swap;
222 struct platform_device *serdes_pdev;
223 struct reset_controller_dev wiz_phy_reset_dev;
224 struct gpio_desc *gpio_typec_dir;
226 u32 lane_phy_type[WIZ_MAX_LANES];
229 static int wiz_reset(struct wiz *wiz)
233 ret = regmap_field_write(wiz->por_en, 0x1);
239 ret = regmap_field_write(wiz->por_en, 0x0);
246 static int wiz_mode_select(struct wiz *wiz)
248 u32 num_lanes = wiz->num_lanes;
249 enum wiz_lane_standard_mode mode;
253 for (i = 0; i < num_lanes; i++) {
254 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
255 mode = LANE_MODE_GEN1;
257 mode = LANE_MODE_GEN4;
259 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
267 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
269 u32 num_lanes = wiz->num_lanes;
273 for (i = 0; i < num_lanes; i++) {
274 ret = regmap_field_write(wiz->p_align[i], enable);
278 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
286 static int wiz_init(struct wiz *wiz)
288 struct device *dev = wiz->dev;
291 ret = wiz_reset(wiz);
293 dev_err(dev, "WIZ reset failed\n");
297 ret = wiz_mode_select(wiz);
299 dev_err(dev, "WIZ mode select failed\n");
303 ret = wiz_init_raw_interface(wiz, true);
305 dev_err(dev, "WIZ interface initialization failed\n");
312 static int wiz_regfield_init(struct wiz *wiz)
314 struct wiz_clk_mux_sel *clk_mux_sel;
315 struct wiz_clk_div_sel *clk_div_sel;
316 struct regmap *regmap = wiz->regmap;
317 int num_lanes = wiz->num_lanes;
318 struct device *dev = wiz->dev;
321 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
322 if (IS_ERR(wiz->por_en)) {
323 dev_err(dev, "POR_EN reg field init failed\n");
324 return PTR_ERR(wiz->por_en);
327 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
329 if (IS_ERR(wiz->phy_reset_n)) {
330 dev_err(dev, "PHY_RESET_N reg field init failed\n");
331 return PTR_ERR(wiz->phy_reset_n);
334 wiz->pma_cmn_refclk_int_mode =
335 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
336 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
337 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
338 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
341 wiz->pma_cmn_refclk_mode =
342 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
343 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
344 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
345 return PTR_ERR(wiz->pma_cmn_refclk_mode);
348 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV];
349 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap,
350 pma_cmn_refclk_dig_div);
351 if (IS_ERR(clk_div_sel->field)) {
352 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
353 return PTR_ERR(clk_div_sel->field);
356 if (wiz->type == J721E_WIZ_16G) {
357 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV];
359 devm_regmap_field_alloc(dev, regmap,
360 pma_cmn_refclk1_dig_div);
361 if (IS_ERR(clk_div_sel->field)) {
362 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
363 return PTR_ERR(clk_div_sel->field);
367 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK];
368 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
369 pll0_refclk_mux_sel);
370 if (IS_ERR(clk_mux_sel->field)) {
371 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
372 return PTR_ERR(clk_mux_sel->field);
375 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK];
376 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
377 pll1_refclk_mux_sel);
378 if (IS_ERR(clk_mux_sel->field)) {
379 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
380 return PTR_ERR(clk_mux_sel->field);
383 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
384 if (wiz->type == J721E_WIZ_10G)
386 devm_regmap_field_alloc(dev, regmap,
390 devm_regmap_field_alloc(dev, regmap,
393 if (IS_ERR(clk_mux_sel->field)) {
394 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
395 return PTR_ERR(clk_mux_sel->field);
398 for (i = 0; i < num_lanes; i++) {
399 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
401 if (IS_ERR(wiz->p_enable[i])) {
402 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
403 return PTR_ERR(wiz->p_enable[i]);
406 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
408 if (IS_ERR(wiz->p_align[i])) {
409 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
410 return PTR_ERR(wiz->p_align[i]);
413 wiz->p_raw_auto_start[i] =
414 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
415 if (IS_ERR(wiz->p_raw_auto_start[i])) {
416 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
418 return PTR_ERR(wiz->p_raw_auto_start[i]);
421 wiz->p_standard_mode[i] =
422 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
423 if (IS_ERR(wiz->p_standard_mode[i])) {
424 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
426 return PTR_ERR(wiz->p_standard_mode[i]);
430 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
432 if (IS_ERR(wiz->typec_ln10_swap)) {
433 dev_err(dev, "LN10_SWAP reg field init failed\n");
434 return PTR_ERR(wiz->typec_ln10_swap);
440 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
442 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
443 struct regmap_field *field = mux->field;
446 regmap_field_read(field, &val);
447 return clk_mux_val_to_index(hw, mux->table, 0, val);
450 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
452 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
453 struct regmap_field *field = mux->field;
456 val = mux->table[index];
457 return regmap_field_write(field, val);
460 static const struct clk_ops wiz_clk_mux_ops = {
461 .set_parent = wiz_clk_mux_set_parent,
462 .get_parent = wiz_clk_mux_get_parent,
465 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,
466 struct regmap_field *field, u32 *table)
468 struct device *dev = wiz->dev;
469 struct clk_init_data *init;
470 const char **parent_names;
471 unsigned int num_parents;
472 struct wiz_clk_mux *mux;
477 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
481 num_parents = of_clk_get_parent_count(node);
482 if (num_parents < 2) {
483 dev_err(dev, "SERDES clock must have parents\n");
487 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
492 of_clk_parent_fill(node, parent_names, num_parents);
494 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
497 init = &mux->clk_data;
499 init->ops = &wiz_clk_mux_ops;
500 init->flags = CLK_SET_RATE_NO_REPARENT;
501 init->parent_names = parent_names;
502 init->num_parents = num_parents;
503 init->name = clk_name;
509 clk = devm_clk_register(dev, &mux->hw);
513 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
515 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
520 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
521 unsigned long parent_rate)
523 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
524 struct regmap_field *field = div->field;
527 regmap_field_read(field, &val);
529 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
532 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
533 unsigned long *prate)
535 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
537 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
540 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
541 unsigned long parent_rate)
543 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
544 struct regmap_field *field = div->field;
547 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
551 return regmap_field_write(field, val);
554 static const struct clk_ops wiz_clk_div_ops = {
555 .recalc_rate = wiz_clk_div_recalc_rate,
556 .round_rate = wiz_clk_div_round_rate,
557 .set_rate = wiz_clk_div_set_rate,
560 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
561 struct regmap_field *field,
562 const struct clk_div_table *table)
564 struct device *dev = wiz->dev;
565 struct wiz_clk_divider *div;
566 struct clk_init_data *init;
567 const char **parent_names;
572 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
576 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
579 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
583 of_clk_parent_fill(node, parent_names, 1);
585 init = &div->clk_data;
587 init->ops = &wiz_clk_div_ops;
589 init->parent_names = parent_names;
590 init->num_parents = 1;
591 init->name = clk_name;
597 clk = devm_clk_register(dev, &div->hw);
601 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
603 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
608 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
610 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
611 struct device_node *clk_node;
614 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
615 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
616 of_clk_del_provider(clk_node);
617 of_node_put(clk_node);
620 for (i = 0; i < wiz->clk_div_sel_num; i++) {
621 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
622 of_clk_del_provider(clk_node);
623 of_node_put(clk_node);
627 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
629 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
630 struct device *dev = wiz->dev;
631 struct device_node *clk_node;
632 const char *node_name;
638 clk = devm_clk_get(dev, "core_ref_clk");
640 dev_err(dev, "core_ref_clk clock not found\n");
645 rate = clk_get_rate(clk);
646 if (rate >= 100000000)
647 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
649 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
651 clk = devm_clk_get(dev, "ext_ref_clk");
653 dev_err(dev, "ext_ref_clk clock not found\n");
658 rate = clk_get_rate(clk);
659 if (rate >= 100000000)
660 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
662 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
664 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
665 node_name = clk_mux_sel[i].node_name;
666 clk_node = of_get_child_by_name(node, node_name);
668 dev_err(dev, "Unable to get %s node\n", node_name);
673 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,
674 clk_mux_sel[i].table);
676 dev_err(dev, "Failed to register %s clock\n",
678 of_node_put(clk_node);
682 of_node_put(clk_node);
685 for (i = 0; i < wiz->clk_div_sel_num; i++) {
686 node_name = clk_div_sel[i].node_name;
687 clk_node = of_get_child_by_name(node, node_name);
689 dev_err(dev, "Unable to get %s node\n", node_name);
694 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,
695 clk_div_sel[i].table);
697 dev_err(dev, "Failed to register %s clock\n",
699 of_node_put(clk_node);
703 of_node_put(clk_node);
708 wiz_clock_cleanup(wiz, node);
713 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
716 struct device *dev = rcdev->dev;
717 struct wiz *wiz = dev_get_drvdata(dev);
721 ret = regmap_field_write(wiz->phy_reset_n, false);
725 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
729 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
732 struct device *dev = rcdev->dev;
733 struct wiz *wiz = dev_get_drvdata(dev);
736 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
737 if (id == 0 && wiz->gpio_typec_dir) {
738 if (wiz->typec_dir_delay)
739 msleep_interruptible(wiz->typec_dir_delay);
741 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
742 regmap_field_write(wiz->typec_ln10_swap, 1);
744 regmap_field_write(wiz->typec_ln10_swap, 0);
748 ret = regmap_field_write(wiz->phy_reset_n, true);
752 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
753 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
755 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
760 static const struct reset_control_ops wiz_phy_reset_ops = {
761 .assert = wiz_phy_reset_assert,
762 .deassert = wiz_phy_reset_deassert,
765 static const struct regmap_config wiz_regmap_config = {
772 static const struct of_device_id wiz_id_table[] = {
774 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
777 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
781 MODULE_DEVICE_TABLE(of, wiz_id_table);
783 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
785 struct device_node *serdes, *subnode;
787 serdes = of_get_child_by_name(dev->of_node, "serdes");
789 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
793 for_each_child_of_node(serdes, subnode) {
794 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
797 ret = of_property_read_u32(subnode, "reg", ®);
800 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
801 __func__, subnode->name, ret);
804 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
805 of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
807 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
808 reg, reg + num_lanes - 1, phy_type);
810 for (i = reg; i < reg + num_lanes; i++)
811 wiz->lane_phy_type[i] = phy_type;
817 static int wiz_probe(struct platform_device *pdev)
819 struct reset_controller_dev *phy_reset_dev;
820 struct device *dev = &pdev->dev;
821 struct device_node *node = dev->of_node;
822 struct platform_device *serdes_pdev;
823 struct device_node *child_node;
824 struct regmap *regmap;
831 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
835 wiz->type = (enum wiz_type)of_device_get_match_data(dev);
837 child_node = of_get_child_by_name(node, "serdes");
839 dev_err(dev, "Failed to get SERDES child DT node\n");
843 ret = of_address_to_resource(child_node, 0, &res);
845 dev_err(dev, "Failed to get memory resource\n");
846 goto err_addr_to_resource;
849 base = devm_ioremap(dev, res.start, resource_size(&res));
852 goto err_addr_to_resource;
855 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
856 if (IS_ERR(regmap)) {
857 dev_err(dev, "Failed to initialize regmap\n");
858 ret = PTR_ERR(regmap);
859 goto err_addr_to_resource;
862 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
864 dev_err(dev, "Failed to read num-lanes property\n");
865 goto err_addr_to_resource;
868 if (num_lanes > WIZ_MAX_LANES) {
869 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
871 goto err_addr_to_resource;
874 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
876 if (IS_ERR(wiz->gpio_typec_dir)) {
877 ret = PTR_ERR(wiz->gpio_typec_dir);
878 if (ret != -EPROBE_DEFER)
879 dev_err(dev, "Failed to request typec-dir gpio: %d\n",
881 goto err_addr_to_resource;
884 if (wiz->gpio_typec_dir) {
885 ret = of_property_read_u32(node, "typec-dir-debounce-ms",
886 &wiz->typec_dir_delay);
887 if (ret && ret != -EINVAL) {
888 dev_err(dev, "Invalid typec-dir-debounce property\n");
889 goto err_addr_to_resource;
892 /* use min. debounce from Type-C spec if not provided in DT */
894 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
896 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
897 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
899 dev_err(dev, "Invalid typec-dir-debounce property\n");
900 goto err_addr_to_resource;
904 ret = wiz_get_lane_phy_types(dev, wiz);
909 wiz->regmap = regmap;
910 wiz->num_lanes = num_lanes;
911 if (wiz->type == J721E_WIZ_10G)
912 wiz->clk_mux_sel = clk_mux_sel_10g;
914 wiz->clk_mux_sel = clk_mux_sel_16g;
916 wiz->clk_div_sel = clk_div_sel;
918 if (wiz->type == J721E_WIZ_10G)
919 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
921 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
923 platform_set_drvdata(pdev, wiz);
925 ret = wiz_regfield_init(wiz);
927 dev_err(dev, "Failed to initialize regfields\n");
928 goto err_addr_to_resource;
931 phy_reset_dev = &wiz->wiz_phy_reset_dev;
932 phy_reset_dev->dev = dev;
933 phy_reset_dev->ops = &wiz_phy_reset_ops,
934 phy_reset_dev->owner = THIS_MODULE,
935 phy_reset_dev->of_node = node;
936 /* Reset for each of the lane and one for the entire SERDES */
937 phy_reset_dev->nr_resets = num_lanes + 1;
939 ret = devm_reset_controller_register(dev, phy_reset_dev);
941 dev_warn(dev, "Failed to register reset controller\n");
942 goto err_addr_to_resource;
945 pm_runtime_enable(dev);
946 ret = pm_runtime_get_sync(dev);
948 dev_err(dev, "pm_runtime_get_sync failed\n");
952 ret = wiz_clock_init(wiz, node);
954 dev_warn(dev, "Failed to initialize clocks\n");
960 dev_err(dev, "WIZ initialization failed\n");
964 serdes_pdev = of_platform_device_create(child_node, NULL, dev);
966 dev_WARN(dev, "Unable to create SERDES platform device\n");
970 wiz->serdes_pdev = serdes_pdev;
972 of_node_put(child_node);
976 wiz_clock_cleanup(wiz, node);
980 pm_runtime_disable(dev);
982 err_addr_to_resource:
983 of_node_put(child_node);
988 static int wiz_remove(struct platform_device *pdev)
990 struct device *dev = &pdev->dev;
991 struct device_node *node = dev->of_node;
992 struct platform_device *serdes_pdev;
995 wiz = dev_get_drvdata(dev);
996 serdes_pdev = wiz->serdes_pdev;
998 of_platform_device_destroy(&serdes_pdev->dev, NULL);
999 wiz_clock_cleanup(wiz, node);
1000 pm_runtime_put(dev);
1001 pm_runtime_disable(dev);
1006 static struct platform_driver wiz_driver = {
1008 .remove = wiz_remove,
1011 .of_match_table = wiz_id_table,
1014 module_platform_driver(wiz_driver);
1016 MODULE_AUTHOR("Texas Instruments Inc.");
1017 MODULE_DESCRIPTION("TI J721E WIZ driver");
1018 MODULE_LICENSE("GPL v2");