1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/delay.h>
8 #include <linux/module.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/slab.h>
16 #include <soc/tegra/fuse.h>
20 /* FUSE USB_CALIB registers */
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK 0x3f
23 #define HS_TERM_RANGE_ADJ_SHIFT 7
24 #define HS_TERM_RANGE_ADJ_MASK 0xf
25 #define HS_SQUELCH_SHIFT 29
26 #define HS_SQUELCH_MASK 0x7
28 #define RPD_CTRL_SHIFT 0
29 #define RPD_CTRL_MASK 0x1f
31 /* XUSB PADCTL registers */
32 #define XUSB_PADCTL_USB2_PAD_MUX 0x4
33 #define USB2_PORT_SHIFT(x) ((x) * 2)
34 #define USB2_PORT_MASK 0x3
36 #define HSIC_PORT_SHIFT(x) ((x) + 20)
37 #define HSIC_PORT_MASK 0x1
40 #define XUSB_PADCTL_USB2_PORT_CAP 0x8
41 #define XUSB_PADCTL_SS_PORT_CAP 0xc
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
43 #define PORT_CAP_MASK 0x3
44 #define PORT_CAP_DISABLED 0x0
45 #define PORT_CAP_HOST 0x1
46 #define PORT_CAP_DEVICE 0x2
47 #define PORT_CAP_OTG 0x3
49 #define XUSB_PADCTL_ELPG_PROGRAM 0x20
50 #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51 #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52 #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53 #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54 #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55 #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56 #define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
62 #define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66 #define XUSB_PADCTL_SS_PORT_CFG 0x2c
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68 #define PORTX_SPEED_SUPPORT_MASK (0x3)
69 #define PORT_SPEED_SUPPORT_GEN1 (0x0)
71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72 #define HS_CURR_LEVEL(x) ((x) & 0x3f)
73 #define TERM_SEL BIT(25)
74 #define USB2_OTG_PD BIT(26)
75 #define USB2_OTG_PD2 BIT(27)
76 #define USB2_OTG_PD2_OVRD_EN BIT(28)
77 #define USB2_OTG_PD_ZI BIT(29)
79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80 #define USB2_OTG_PD_DR BIT(2)
81 #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82 #define RPD_CTRL(x) (((x) & 0x1f) << 26)
84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85 #define BIAS_PAD_PD BIT(11)
86 #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89 #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90 #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91 #define USB2_PD_TRK BIT(26)
93 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
94 #define HSIC_PD_TX_DATA0 BIT(1)
95 #define HSIC_PD_TX_STROBE BIT(3)
96 #define HSIC_PD_RX_DATA0 BIT(4)
97 #define HSIC_PD_RX_STROBE BIT(6)
98 #define HSIC_PD_ZI_DATA0 BIT(7)
99 #define HSIC_PD_ZI_STROBE BIT(9)
100 #define HSIC_RPD_DATA0 BIT(13)
101 #define HSIC_RPD_STROBE BIT(15)
102 #define HSIC_RPU_DATA0 BIT(16)
103 #define HSIC_RPU_STROBE BIT(18)
105 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
106 #define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
107 #define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
108 #define HSIC_PD_TRK BIT(19)
110 #define USB2_VBUS_ID 0x360
111 #define VBUS_OVERRIDE BIT(14)
112 #define ID_OVERRIDE(x) (((x) & 0xf) << 18)
113 #define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
114 #define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
116 /* XUSB AO registers */
117 #define XUSB_AO_USB_DEBOUNCE_DEL (0x4)
118 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
119 #define UTMIP_LINE_DEB_CNT(x) ((x) & 0xf)
121 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
122 #define CLR_WALK_PTR BIT(0)
123 #define CAP_CFG BIT(1)
124 #define CLR_WAKE_ALARM BIT(3)
126 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
127 #define HSIC_CLR_WALK_PTR BIT(0)
128 #define HSIC_CLR_WAKE_ALARM BIT(3)
129 #define HSIC_CAP_CFG BIT(4)
131 #define XUSB_AO_UTMIP_SAVED_STATE(x) (0x70 + (x) * 4)
132 #define SPEED(x) ((x) & 0x3)
133 #define UTMI_HS SPEED(0)
134 #define UTMI_FS SPEED(1)
135 #define UTMI_LS SPEED(2)
136 #define UTMI_RST SPEED(3)
138 #define XUSB_AO_UHSIC_SAVED_STATE(x) (0x90 + (x) * 4)
139 #define MODE(x) ((x) & 0x1)
140 #define MODE_HS MODE(0)
141 #define MODE_RST MODE(1)
143 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
144 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
145 #define FAKE_USBOP_VAL BIT(0)
146 #define FAKE_USBON_VAL BIT(1)
147 #define FAKE_USBOP_EN BIT(2)
148 #define FAKE_USBON_EN BIT(3)
149 #define FAKE_STROBE_VAL BIT(0)
150 #define FAKE_DATA_VAL BIT(1)
151 #define FAKE_STROBE_EN BIT(2)
152 #define FAKE_DATA_EN BIT(3)
153 #define WAKE_WALK_EN BIT(14)
154 #define MASTER_ENABLE BIT(15)
155 #define LINEVAL_WALK_EN BIT(16)
156 #define WAKE_VAL(x) (((x) & 0xf) << 17)
157 #define WAKE_VAL_NONE WAKE_VAL(12)
158 #define WAKE_VAL_ANY WAKE_VAL(15)
159 #define WAKE_VAL_DS10 WAKE_VAL(2)
160 #define LINE_WAKEUP_EN BIT(21)
161 #define MASTER_CFG_SEL BIT(22)
163 #define XUSB_AO_UTMIP_SLEEPWALK(x) (0x100 + (x) * 4)
165 #define USBOP_RPD_A BIT(0)
166 #define USBON_RPD_A BIT(1)
169 #define HIGHZ_A BIT(6)
171 #define USBOP_RPD_B BIT(8)
172 #define USBON_RPD_B BIT(9)
175 #define HIGHZ_B BIT(14)
177 #define USBOP_RPD_C BIT(16)
178 #define USBON_RPD_C BIT(17)
181 #define HIGHZ_C BIT(22)
183 #define USBOP_RPD_D BIT(24)
184 #define USBON_RPD_D BIT(25)
187 #define HIGHZ_D BIT(30)
189 #define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
191 #define RPD_STROBE_A BIT(0)
192 #define RPD_DATA0_A BIT(1)
193 #define RPU_STROBE_A BIT(2)
194 #define RPU_DATA0_A BIT(3)
196 #define RPD_STROBE_B BIT(8)
197 #define RPD_DATA0_B BIT(9)
198 #define RPU_STROBE_B BIT(10)
199 #define RPU_DATA0_B BIT(11)
201 #define RPD_STROBE_C BIT(16)
202 #define RPD_DATA0_C BIT(17)
203 #define RPU_STROBE_C BIT(18)
204 #define RPU_DATA0_C BIT(19)
206 #define RPD_STROBE_D BIT(24)
207 #define RPD_DATA0_D BIT(25)
208 #define RPU_STROBE_D BIT(26)
209 #define RPU_DATA0_D BIT(27)
211 #define XUSB_AO_UTMIP_PAD_CFG(x) (0x130 + (x) * 4)
212 #define FSLS_USE_XUSB_AO BIT(3)
213 #define TRK_CTRL_USE_XUSB_AO BIT(4)
214 #define RPD_CTRL_USE_XUSB_AO BIT(5)
215 #define RPU_USE_XUSB_AO BIT(6)
216 #define VREG_USE_XUSB_AO BIT(7)
217 #define USBOP_VAL_PD BIT(8)
218 #define USBON_VAL_PD BIT(9)
219 #define E_DPD_OVRD_EN BIT(10)
220 #define E_DPD_OVRD_VAL BIT(11)
222 #define XUSB_AO_UHSIC_PAD_CFG(x) (0x150 + (x) * 4)
223 #define STROBE_VAL_PD BIT(0)
224 #define DATA0_VAL_PD BIT(1)
225 #define USE_XUSB_AO BIT(4)
227 #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
233 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
234 .funcs = tegra186_##_type##_functions, \
237 struct tegra_xusb_fuse_calibration {
240 u32 hs_term_range_adj;
244 struct tegra186_xusb_padctl_context {
251 struct tegra186_xusb_padctl {
252 struct tegra_xusb_padctl base;
253 void __iomem *ao_regs;
255 struct tegra_xusb_fuse_calibration calib;
257 /* UTMI bias and tracking */
258 struct clk *usb2_trk_clk;
259 unsigned int bias_pad_enable;
262 struct tegra186_xusb_padctl_context context;
265 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset)
267 writel(value, priv->ao_regs + offset);
270 static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset)
272 return readl(priv->ao_regs + offset);
275 static inline struct tegra186_xusb_padctl *
276 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
278 return container_of(padctl, struct tegra186_xusb_padctl, base);
281 /* USB 2.0 UTMI PHY support */
282 static struct tegra_xusb_lane *
283 tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
286 struct tegra_xusb_usb2_lane *usb2;
289 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
291 return ERR_PTR(-ENOMEM);
293 INIT_LIST_HEAD(&usb2->base.list);
294 usb2->base.soc = &pad->soc->lanes[index];
295 usb2->base.index = index;
296 usb2->base.pad = pad;
299 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
308 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
310 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
315 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
316 enum usb_device_speed speed)
318 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
319 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
320 unsigned int index = lane->index;
323 mutex_lock(&padctl->lock);
325 /* ensure sleepwalk logic is disabled */
326 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
327 value &= ~MASTER_ENABLE;
328 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
330 /* ensure sleepwalk logics are in low power mode */
331 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
332 value |= MASTER_CFG_SEL;
333 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
335 /* set debounce time */
336 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
337 value &= ~UTMIP_LINE_DEB_CNT(~0);
338 value |= UTMIP_LINE_DEB_CNT(1);
339 ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
341 /* ensure fake events of sleepwalk logic are desiabled */
342 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
343 value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
344 FAKE_USBOP_EN | FAKE_USBON_EN);
345 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
347 /* ensure wake events of sleepwalk logic are not latched */
348 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
349 value &= ~LINE_WAKEUP_EN;
350 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
352 /* disable wake event triggers of sleepwalk logic */
353 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
354 value &= ~WAKE_VAL(~0);
355 value |= WAKE_VAL_NONE;
356 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
358 /* power down the line state detectors of the pad */
359 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
360 value |= (USBOP_VAL_PD | USBON_VAL_PD);
361 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
363 /* save state per speed */
364 value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
385 ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
387 /* enable the trigger of the sleepwalk logic */
388 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
389 value |= LINEVAL_WALK_EN;
390 value &= ~WAKE_WALK_EN;
391 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
393 /* reset the walk pointer and clear the alarm of the sleepwalk logic,
394 * as well as capture the configuration of the USB2.0 pad
396 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
397 value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
398 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
400 /* setup the pull-ups and pull-downs of the signals during the four
401 * stages of sleepwalk.
402 * if device is connected, program sleepwalk logic to maintain a J and
403 * keep driving K upon seeing remote wake.
405 value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D;
406 value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D;
411 /* J state: D+/D- = high/low, K state: D+/D- = low/high */
414 value |= AN_B | AN_C | AN_D;
418 /* J state: D+/D- = low/high, K state: D+/D- = high/low */
421 value |= AP_B | AP_C | AP_D;
425 value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D;
429 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
431 /* power up the line state detectors of the pad */
432 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
433 value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
434 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
436 usleep_range(150, 200);
438 /* switch the electric control of the USB2.0 pad to XUSB_AO */
439 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
440 value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
441 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO;
442 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
444 /* set the wake signaling trigger events */
445 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
446 value &= ~WAKE_VAL(~0);
447 value |= WAKE_VAL_ANY;
448 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
450 /* enable the wake detection */
451 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
452 value |= MASTER_ENABLE | LINE_WAKEUP_EN;
453 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
455 mutex_unlock(&padctl->lock);
460 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
462 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
463 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
464 unsigned int index = lane->index;
467 mutex_lock(&padctl->lock);
469 /* disable the wake detection */
470 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
471 value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
472 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
474 /* switch the electric control of the USB2.0 pad to XUSB vcore logic */
475 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
476 value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
477 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
478 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
480 /* disable wake event triggers of sleepwalk logic */
481 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
482 value &= ~WAKE_VAL(~0);
483 value |= WAKE_VAL_NONE;
484 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
486 /* power down the line state detectors of the port */
487 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
488 value |= USBOP_VAL_PD | USBON_VAL_PD;
489 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
491 /* clear alarm of the sleepwalk logic */
492 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
493 value |= CLR_WAKE_ALARM;
494 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
496 mutex_unlock(&padctl->lock);
501 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
503 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
504 unsigned int index = lane->index;
507 mutex_lock(&padctl->lock);
509 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
510 value &= ~ALL_WAKE_EVENTS;
511 value |= USB2_PORT_WAKEUP_EVENT(index);
512 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
514 usleep_range(10, 20);
516 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
517 value &= ~ALL_WAKE_EVENTS;
518 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
519 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
521 mutex_unlock(&padctl->lock);
526 static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
528 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
529 unsigned int index = lane->index;
532 mutex_lock(&padctl->lock);
534 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
535 value &= ~ALL_WAKE_EVENTS;
536 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
537 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
539 usleep_range(10, 20);
541 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
542 value &= ~ALL_WAKE_EVENTS;
543 value |= USB2_PORT_WAKEUP_EVENT(index);
544 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
546 mutex_unlock(&padctl->lock);
551 static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
553 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
554 unsigned int index = lane->index;
557 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
558 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
559 (value & USB2_PORT_WAKEUP_EVENT(index)))
565 static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
566 .probe = tegra186_usb2_lane_probe,
567 .remove = tegra186_usb2_lane_remove,
568 .enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk,
569 .disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk,
570 .enable_phy_wake = tegra186_utmi_enable_phy_wake,
571 .disable_phy_wake = tegra186_utmi_disable_phy_wake,
572 .remote_wake_detected = tegra186_utmi_phy_remote_wake_detected,
575 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
577 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
578 struct device *dev = padctl->dev;
582 mutex_lock(&padctl->lock);
584 if (priv->bias_pad_enable++ > 0) {
585 mutex_unlock(&padctl->lock);
589 err = clk_prepare_enable(priv->usb2_trk_clk);
591 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
593 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
594 value &= ~USB2_TRK_START_TIMER(~0);
595 value |= USB2_TRK_START_TIMER(0x1e);
596 value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
597 value |= USB2_TRK_DONE_RESET_TIMER(0xa);
598 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
600 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
601 value &= ~BIAS_PAD_PD;
602 value &= ~HS_SQUELCH_LEVEL(~0);
603 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
604 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
608 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
609 value &= ~USB2_PD_TRK;
610 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
612 mutex_unlock(&padctl->lock);
615 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
617 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
620 mutex_lock(&padctl->lock);
622 if (WARN_ON(priv->bias_pad_enable == 0)) {
623 mutex_unlock(&padctl->lock);
627 if (--priv->bias_pad_enable > 0) {
628 mutex_unlock(&padctl->lock);
632 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
633 value |= USB2_PD_TRK;
634 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
636 clk_disable_unprepare(priv->usb2_trk_clk);
638 mutex_unlock(&padctl->lock);
641 static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
643 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
644 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
645 struct tegra_xusb_usb2_port *port;
646 struct device *dev = padctl->dev;
647 unsigned int index = lane->index;
653 port = tegra_xusb_find_usb2_port(padctl, index);
655 dev_err(dev, "no port found for USB2 lane %u\n", index);
659 tegra186_utmi_bias_pad_power_on(padctl);
663 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
664 value &= ~USB2_OTG_PD;
665 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
667 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
668 value &= ~USB2_OTG_PD_DR;
669 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
672 static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
674 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
675 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
676 unsigned int index = lane->index;
682 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
683 value |= USB2_OTG_PD;
684 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
686 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
687 value |= USB2_OTG_PD_DR;
688 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
692 tegra186_utmi_bias_pad_power_off(padctl);
695 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
700 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
702 value = padctl_readl(padctl, USB2_VBUS_ID);
705 value |= VBUS_OVERRIDE;
706 value &= ~ID_OVERRIDE(~0);
707 value |= ID_OVERRIDE_FLOATING;
709 value &= ~VBUS_OVERRIDE;
712 padctl_writel(padctl, value, USB2_VBUS_ID);
717 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
722 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
724 value = padctl_readl(padctl, USB2_VBUS_ID);
727 if (value & VBUS_OVERRIDE) {
728 value &= ~VBUS_OVERRIDE;
729 padctl_writel(padctl, value, USB2_VBUS_ID);
730 usleep_range(1000, 2000);
732 value = padctl_readl(padctl, USB2_VBUS_ID);
735 value &= ~ID_OVERRIDE(~0);
736 value |= ID_OVERRIDE_GROUNDED;
738 value &= ~ID_OVERRIDE(~0);
739 value |= ID_OVERRIDE_FLOATING;
742 padctl_writel(padctl, value, USB2_VBUS_ID);
747 static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
750 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
751 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
752 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
756 mutex_lock(&padctl->lock);
758 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
760 if (mode == PHY_MODE_USB_OTG) {
761 if (submode == USB_ROLE_HOST) {
762 tegra186_xusb_padctl_id_override(padctl, true);
764 err = regulator_enable(port->supply);
765 } else if (submode == USB_ROLE_DEVICE) {
766 tegra186_xusb_padctl_vbus_override(padctl, true);
767 } else if (submode == USB_ROLE_NONE) {
769 * When port is peripheral only or role transitions to
770 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
773 if (regulator_is_enabled(port->supply))
774 regulator_disable(port->supply);
776 tegra186_xusb_padctl_id_override(padctl, false);
777 tegra186_xusb_padctl_vbus_override(padctl, false);
781 mutex_unlock(&padctl->lock);
786 static int tegra186_utmi_phy_power_on(struct phy *phy)
788 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
789 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
790 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
791 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
792 struct tegra_xusb_usb2_port *port;
793 unsigned int index = lane->index;
794 struct device *dev = padctl->dev;
797 port = tegra_xusb_find_usb2_port(padctl, index);
799 dev_err(dev, "no port found for USB2 lane %u\n", index);
803 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
804 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
805 value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
806 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
808 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
809 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
811 if (port->mode == USB_DR_MODE_UNKNOWN)
812 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
813 else if (port->mode == USB_DR_MODE_PERIPHERAL)
814 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
815 else if (port->mode == USB_DR_MODE_HOST)
816 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
817 else if (port->mode == USB_DR_MODE_OTG)
818 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
820 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
822 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
823 value &= ~USB2_OTG_PD_ZI;
825 value &= ~HS_CURR_LEVEL(~0);
827 if (usb2->hs_curr_level_offset) {
828 int hs_current_level;
830 hs_current_level = (int)priv->calib.hs_curr_level[index] +
831 usb2->hs_curr_level_offset;
833 if (hs_current_level < 0)
834 hs_current_level = 0;
835 if (hs_current_level > 0x3f)
836 hs_current_level = 0x3f;
838 value |= HS_CURR_LEVEL(hs_current_level);
840 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
843 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
845 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
846 value &= ~TERM_RANGE_ADJ(~0);
847 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
848 value &= ~RPD_CTRL(~0);
849 value |= RPD_CTRL(priv->calib.rpd_ctrl);
850 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
852 /* TODO: pad power saving */
853 tegra_phy_xusb_utmi_pad_power_on(phy);
857 static int tegra186_utmi_phy_power_off(struct phy *phy)
859 /* TODO: pad power saving */
860 tegra_phy_xusb_utmi_pad_power_down(phy);
865 static int tegra186_utmi_phy_init(struct phy *phy)
867 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
868 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
869 struct tegra_xusb_usb2_port *port;
870 unsigned int index = lane->index;
871 struct device *dev = padctl->dev;
874 port = tegra_xusb_find_usb2_port(padctl, index);
876 dev_err(dev, "no port found for USB2 lane %u\n", index);
880 if (port->supply && port->mode == USB_DR_MODE_HOST) {
881 err = regulator_enable(port->supply);
883 dev_err(dev, "failed to enable port %u VBUS: %d\n",
892 static int tegra186_utmi_phy_exit(struct phy *phy)
894 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
895 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
896 struct tegra_xusb_usb2_port *port;
897 unsigned int index = lane->index;
898 struct device *dev = padctl->dev;
901 port = tegra_xusb_find_usb2_port(padctl, index);
903 dev_err(dev, "no port found for USB2 lane %u\n", index);
907 if (port->supply && port->mode == USB_DR_MODE_HOST) {
908 err = regulator_disable(port->supply);
910 dev_err(dev, "failed to disable port %u VBUS: %d\n",
919 static const struct phy_ops utmi_phy_ops = {
920 .init = tegra186_utmi_phy_init,
921 .exit = tegra186_utmi_phy_exit,
922 .power_on = tegra186_utmi_phy_power_on,
923 .power_off = tegra186_utmi_phy_power_off,
924 .set_mode = tegra186_utmi_phy_set_mode,
925 .owner = THIS_MODULE,
928 static struct tegra_xusb_pad *
929 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
930 const struct tegra_xusb_pad_soc *soc,
931 struct device_node *np)
933 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
934 struct tegra_xusb_usb2_pad *usb2;
935 struct tegra_xusb_pad *pad;
938 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
940 return ERR_PTR(-ENOMEM);
943 pad->ops = &tegra186_usb2_lane_ops;
946 err = tegra_xusb_pad_init(pad, padctl, np);
952 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
953 if (IS_ERR(priv->usb2_trk_clk)) {
954 err = PTR_ERR(priv->usb2_trk_clk);
955 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
959 err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
963 dev_set_drvdata(&pad->dev, pad);
968 device_unregister(&pad->dev);
973 static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
975 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
980 static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
981 .probe = tegra186_usb2_pad_probe,
982 .remove = tegra186_usb2_pad_remove,
985 static const char * const tegra186_usb2_functions[] = {
989 static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
994 static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
998 static struct tegra_xusb_lane *
999 tegra186_usb2_port_map(struct tegra_xusb_port *port)
1001 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1004 static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
1005 .release = tegra_xusb_usb2_port_release,
1006 .remove = tegra_xusb_usb2_port_remove,
1007 .enable = tegra186_usb2_port_enable,
1008 .disable = tegra186_usb2_port_disable,
1009 .map = tegra186_usb2_port_map,
1012 /* SuperSpeed PHY support */
1013 static struct tegra_xusb_lane *
1014 tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1017 struct tegra_xusb_usb3_lane *usb3;
1020 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1022 return ERR_PTR(-ENOMEM);
1024 INIT_LIST_HEAD(&usb3->base.list);
1025 usb3->base.soc = &pad->soc->lanes[index];
1026 usb3->base.index = index;
1027 usb3->base.pad = pad;
1030 err = tegra_xusb_lane_parse_dt(&usb3->base, np);
1033 return ERR_PTR(err);
1039 static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
1041 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
1046 static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1047 enum usb_device_speed speed)
1049 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1050 unsigned int index = lane->index;
1053 mutex_lock(&padctl->lock);
1055 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1056 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1057 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1059 usleep_range(100, 200);
1061 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1062 value |= SSPX_ELPG_CLAMP_EN(index);
1063 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1065 usleep_range(250, 350);
1067 mutex_unlock(&padctl->lock);
1072 static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1074 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1075 unsigned int index = lane->index;
1078 mutex_lock(&padctl->lock);
1080 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1081 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1082 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1084 usleep_range(100, 200);
1086 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1087 value &= ~SSPX_ELPG_CLAMP_EN(index);
1088 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1090 mutex_unlock(&padctl->lock);
1095 static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1097 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1098 unsigned int index = lane->index;
1101 mutex_lock(&padctl->lock);
1103 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1104 value &= ~ALL_WAKE_EVENTS;
1105 value |= SS_PORT_WAKEUP_EVENT(index);
1106 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1108 usleep_range(10, 20);
1110 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1111 value &= ~ALL_WAKE_EVENTS;
1112 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1113 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1115 mutex_unlock(&padctl->lock);
1120 static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1122 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1123 unsigned int index = lane->index;
1126 mutex_lock(&padctl->lock);
1128 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1129 value &= ~ALL_WAKE_EVENTS;
1130 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1131 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1133 usleep_range(10, 20);
1135 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1136 value &= ~ALL_WAKE_EVENTS;
1137 value |= SS_PORT_WAKEUP_EVENT(index);
1138 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1140 mutex_unlock(&padctl->lock);
1145 static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1147 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1148 unsigned int index = lane->index;
1151 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1152 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1158 static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
1159 .probe = tegra186_usb3_lane_probe,
1160 .remove = tegra186_usb3_lane_remove,
1161 .enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk,
1162 .disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk,
1163 .enable_phy_wake = tegra186_usb3_enable_phy_wake,
1164 .disable_phy_wake = tegra186_usb3_disable_phy_wake,
1165 .remote_wake_detected = tegra186_usb3_phy_remote_wake_detected,
1168 static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
1173 static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
1177 static struct tegra_xusb_lane *
1178 tegra186_usb3_port_map(struct tegra_xusb_port *port)
1180 return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1183 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
1184 .release = tegra_xusb_usb3_port_release,
1185 .remove = tegra_xusb_usb3_port_remove,
1186 .enable = tegra186_usb3_port_enable,
1187 .disable = tegra186_usb3_port_disable,
1188 .map = tegra186_usb3_port_map,
1191 static int tegra186_usb3_phy_power_on(struct phy *phy)
1193 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1194 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1195 struct tegra_xusb_usb3_port *port;
1196 struct tegra_xusb_usb2_port *usb2;
1197 unsigned int index = lane->index;
1198 struct device *dev = padctl->dev;
1201 port = tegra_xusb_find_usb3_port(padctl, index);
1203 dev_err(dev, "no port found for USB3 lane %u\n", index);
1207 usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1209 dev_err(dev, "no companion port found for USB3 lane %u\n",
1214 mutex_lock(&padctl->lock);
1216 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1217 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
1219 if (usb2->mode == USB_DR_MODE_UNKNOWN)
1220 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
1221 else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
1222 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
1223 else if (usb2->mode == USB_DR_MODE_HOST)
1224 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
1225 else if (usb2->mode == USB_DR_MODE_OTG)
1226 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
1228 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1230 if (padctl->soc->supports_gen2 && port->disable_gen2) {
1231 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1232 value &= ~(PORTX_SPEED_SUPPORT_MASK <<
1233 PORTX_SPEED_SUPPORT_SHIFT(index));
1234 value |= (PORT_SPEED_SUPPORT_GEN1 <<
1235 PORTX_SPEED_SUPPORT_SHIFT(index));
1236 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1239 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1240 value &= ~SSPX_ELPG_VCORE_DOWN(index);
1241 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1243 usleep_range(100, 200);
1245 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1246 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1247 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1249 usleep_range(100, 200);
1251 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1252 value &= ~SSPX_ELPG_CLAMP_EN(index);
1253 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1255 mutex_unlock(&padctl->lock);
1260 static int tegra186_usb3_phy_power_off(struct phy *phy)
1262 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1263 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1264 struct tegra_xusb_usb3_port *port;
1265 unsigned int index = lane->index;
1266 struct device *dev = padctl->dev;
1269 port = tegra_xusb_find_usb3_port(padctl, index);
1271 dev_err(dev, "no port found for USB3 lane %u\n", index);
1275 mutex_lock(&padctl->lock);
1277 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1278 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1279 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1281 usleep_range(100, 200);
1283 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1284 value |= SSPX_ELPG_CLAMP_EN(index);
1285 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1287 usleep_range(250, 350);
1289 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1290 value |= SSPX_ELPG_VCORE_DOWN(index);
1291 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1293 mutex_unlock(&padctl->lock);
1298 static int tegra186_usb3_phy_init(struct phy *phy)
1303 static int tegra186_usb3_phy_exit(struct phy *phy)
1308 static const struct phy_ops usb3_phy_ops = {
1309 .init = tegra186_usb3_phy_init,
1310 .exit = tegra186_usb3_phy_exit,
1311 .power_on = tegra186_usb3_phy_power_on,
1312 .power_off = tegra186_usb3_phy_power_off,
1313 .owner = THIS_MODULE,
1316 static struct tegra_xusb_pad *
1317 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1318 const struct tegra_xusb_pad_soc *soc,
1319 struct device_node *np)
1321 struct tegra_xusb_usb3_pad *usb3;
1322 struct tegra_xusb_pad *pad;
1325 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1327 return ERR_PTR(-ENOMEM);
1330 pad->ops = &tegra186_usb3_lane_ops;
1333 err = tegra_xusb_pad_init(pad, padctl, np);
1339 err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
1343 dev_set_drvdata(&pad->dev, pad);
1348 device_unregister(&pad->dev);
1350 return ERR_PTR(err);
1353 static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
1355 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1360 static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
1361 .probe = tegra186_usb3_pad_probe,
1362 .remove = tegra186_usb3_pad_remove,
1365 static const char * const tegra186_usb3_functions[] = {
1370 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1372 struct device *dev = padctl->base.dev;
1373 unsigned int i, count;
1377 count = padctl->base.soc->ports.usb2.count;
1379 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
1383 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
1385 if (err != -EPROBE_DEFER)
1386 dev_err(dev, "failed to read calibration fuse: %d\n",
1391 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
1393 for (i = 0; i < count; i++)
1394 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
1395 HS_CURR_LEVEL_PAD_MASK;
1397 padctl->calib.hs_curr_level = level;
1399 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1401 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1402 HS_TERM_RANGE_ADJ_MASK;
1404 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
1406 dev_err(dev, "failed to read calibration fuse: %d\n", err);
1410 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
1412 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1417 static struct tegra_xusb_padctl *
1418 tegra186_xusb_padctl_probe(struct device *dev,
1419 const struct tegra_xusb_padctl_soc *soc)
1421 struct platform_device *pdev = to_platform_device(dev);
1422 struct tegra186_xusb_padctl *priv;
1423 struct resource *res;
1426 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1428 return ERR_PTR(-ENOMEM);
1430 priv->base.dev = dev;
1431 priv->base.soc = soc;
1433 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
1434 priv->ao_regs = devm_ioremap_resource(dev, res);
1435 if (IS_ERR(priv->ao_regs))
1436 return ERR_CAST(priv->ao_regs);
1438 err = tegra186_xusb_read_fuse_calibration(priv);
1440 return ERR_PTR(err);
1445 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1447 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1449 priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1450 priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1451 priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1452 priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1455 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1457 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1459 padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1460 padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1461 padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1462 padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1465 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1467 tegra186_xusb_padctl_save(padctl);
1472 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1474 tegra186_xusb_padctl_restore(padctl);
1479 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
1483 static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
1484 .probe = tegra186_xusb_padctl_probe,
1485 .remove = tegra186_xusb_padctl_remove,
1486 .suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
1487 .resume_noirq = tegra186_xusb_padctl_resume_noirq,
1488 .vbus_override = tegra186_xusb_padctl_vbus_override,
1491 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1492 static const char * const tegra186_xusb_padctl_supply_names[] = {
1499 static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
1500 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1501 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1502 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1505 static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
1507 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
1508 .lanes = tegra186_usb2_lanes,
1509 .ops = &tegra186_usb2_pad_ops,
1512 static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
1513 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1514 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1515 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1518 static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
1520 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
1521 .lanes = tegra186_usb3_lanes,
1522 .ops = &tegra186_usb3_pad_ops,
1525 static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
1528 #if 0 /* TODO implement */
1533 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
1534 .num_pads = ARRAY_SIZE(tegra186_pads),
1535 .pads = tegra186_pads,
1538 .ops = &tegra186_usb2_port_ops,
1541 #if 0 /* TODO implement */
1543 .ops = &tegra186_hsic_port_ops,
1548 .ops = &tegra186_usb3_port_ops,
1552 .ops = &tegra186_xusb_padctl_ops,
1553 .supply_names = tegra186_xusb_padctl_supply_names,
1554 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1556 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1559 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
1560 static const char * const tegra194_xusb_padctl_supply_names[] = {
1565 static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1566 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1567 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1568 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1569 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1572 static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1574 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1575 .lanes = tegra194_usb2_lanes,
1576 .ops = &tegra186_usb2_pad_ops,
1579 static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1580 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1581 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1582 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1583 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1586 static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1588 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1589 .lanes = tegra194_usb3_lanes,
1590 .ops = &tegra186_usb3_pad_ops,
1593 static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1598 const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1599 .num_pads = ARRAY_SIZE(tegra194_pads),
1600 .pads = tegra194_pads,
1603 .ops = &tegra186_usb2_port_ops,
1607 .ops = &tegra186_usb3_port_ops,
1611 .ops = &tegra186_xusb_padctl_ops,
1612 .supply_names = tegra194_xusb_padctl_supply_names,
1613 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1614 .supports_gen2 = true,
1616 EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1619 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1620 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1621 MODULE_LICENSE("GPL v2");