1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/delay.h>
8 #include <linux/module.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/slab.h>
16 #include <soc/tegra/fuse.h>
20 /* FUSE USB_CALIB registers */
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK 0x3f
23 #define HS_TERM_RANGE_ADJ_SHIFT 7
24 #define HS_TERM_RANGE_ADJ_MASK 0xf
25 #define HS_SQUELCH_SHIFT 29
26 #define HS_SQUELCH_MASK 0x7
28 #define RPD_CTRL_SHIFT 0
29 #define RPD_CTRL_MASK 0x1f
31 /* XUSB PADCTL registers */
32 #define XUSB_PADCTL_USB2_PAD_MUX 0x4
33 #define USB2_PORT_SHIFT(x) ((x) * 2)
34 #define USB2_PORT_MASK 0x3
36 #define HSIC_PORT_SHIFT(x) ((x) + 20)
37 #define HSIC_PORT_MASK 0x1
40 #define XUSB_PADCTL_USB2_PORT_CAP 0x8
41 #define XUSB_PADCTL_SS_PORT_CAP 0xc
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
43 #define PORT_CAP_MASK 0x3
44 #define PORT_CAP_DISABLED 0x0
45 #define PORT_CAP_HOST 0x1
46 #define PORT_CAP_DEVICE 0x2
47 #define PORT_CAP_OTG 0x3
49 #define XUSB_PADCTL_ELPG_PROGRAM 0x20
50 #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51 #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52 #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53 #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54 #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55 #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56 #define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
62 #define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66 #define XUSB_PADCTL_SS_PORT_CFG 0x2c
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68 #define PORTX_SPEED_SUPPORT_MASK (0x3)
69 #define PORT_SPEED_SUPPORT_GEN1 (0x0)
71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72 #define HS_CURR_LEVEL(x) ((x) & 0x3f)
73 #define TERM_SEL BIT(25)
74 #define USB2_OTG_PD BIT(26)
75 #define USB2_OTG_PD2 BIT(27)
76 #define USB2_OTG_PD2_OVRD_EN BIT(28)
77 #define USB2_OTG_PD_ZI BIT(29)
79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80 #define USB2_OTG_PD_DR BIT(2)
81 #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82 #define RPD_CTRL(x) (((x) & 0x1f) << 26)
84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85 #define BIAS_PAD_PD BIT(11)
86 #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89 #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90 #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91 #define USB2_PD_TRK BIT(26)
93 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
94 #define HSIC_PD_TX_DATA0 BIT(1)
95 #define HSIC_PD_TX_STROBE BIT(3)
96 #define HSIC_PD_RX_DATA0 BIT(4)
97 #define HSIC_PD_RX_STROBE BIT(6)
98 #define HSIC_PD_ZI_DATA0 BIT(7)
99 #define HSIC_PD_ZI_STROBE BIT(9)
100 #define HSIC_RPD_DATA0 BIT(13)
101 #define HSIC_RPD_STROBE BIT(15)
102 #define HSIC_RPU_DATA0 BIT(16)
103 #define HSIC_RPU_STROBE BIT(18)
105 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
106 #define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
107 #define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
108 #define HSIC_PD_TRK BIT(19)
110 #define USB2_VBUS_ID 0x360
111 #define VBUS_OVERRIDE BIT(14)
112 #define ID_OVERRIDE(x) (((x) & 0xf) << 18)
113 #define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
114 #define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
116 #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
122 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
123 .funcs = tegra186_##_type##_functions, \
126 struct tegra_xusb_fuse_calibration {
129 u32 hs_term_range_adj;
133 struct tegra186_xusb_padctl {
134 struct tegra_xusb_padctl base;
136 struct tegra_xusb_fuse_calibration calib;
138 /* UTMI bias and tracking */
139 struct clk *usb2_trk_clk;
140 unsigned int bias_pad_enable;
143 static inline struct tegra186_xusb_padctl *
144 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
146 return container_of(padctl, struct tegra186_xusb_padctl, base);
149 /* USB 2.0 UTMI PHY support */
150 static struct tegra_xusb_lane *
151 tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
154 struct tegra_xusb_usb2_lane *usb2;
157 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
159 return ERR_PTR(-ENOMEM);
161 INIT_LIST_HEAD(&usb2->base.list);
162 usb2->base.soc = &pad->soc->lanes[index];
163 usb2->base.index = index;
164 usb2->base.pad = pad;
167 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
176 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
178 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
183 static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
184 .probe = tegra186_usb2_lane_probe,
185 .remove = tegra186_usb2_lane_remove,
188 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
190 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
191 struct device *dev = padctl->dev;
195 mutex_lock(&padctl->lock);
197 if (priv->bias_pad_enable++ > 0) {
198 mutex_unlock(&padctl->lock);
202 err = clk_prepare_enable(priv->usb2_trk_clk);
204 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
206 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
207 value &= ~USB2_TRK_START_TIMER(~0);
208 value |= USB2_TRK_START_TIMER(0x1e);
209 value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
210 value |= USB2_TRK_DONE_RESET_TIMER(0xa);
211 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
213 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
214 value &= ~BIAS_PAD_PD;
215 value &= ~HS_SQUELCH_LEVEL(~0);
216 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
217 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
221 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
222 value &= ~USB2_PD_TRK;
223 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
225 mutex_unlock(&padctl->lock);
228 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
230 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
233 mutex_lock(&padctl->lock);
235 if (WARN_ON(priv->bias_pad_enable == 0)) {
236 mutex_unlock(&padctl->lock);
240 if (--priv->bias_pad_enable > 0) {
241 mutex_unlock(&padctl->lock);
245 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
246 value |= USB2_PD_TRK;
247 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
249 clk_disable_unprepare(priv->usb2_trk_clk);
251 mutex_unlock(&padctl->lock);
254 static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
256 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
257 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
258 struct tegra_xusb_usb2_port *port;
259 struct device *dev = padctl->dev;
260 unsigned int index = lane->index;
266 port = tegra_xusb_find_usb2_port(padctl, index);
268 dev_err(dev, "no port found for USB2 lane %u\n", index);
272 tegra186_utmi_bias_pad_power_on(padctl);
276 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
277 value &= ~USB2_OTG_PD;
278 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
280 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
281 value &= ~USB2_OTG_PD_DR;
282 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
285 static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
287 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
288 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
289 unsigned int index = lane->index;
295 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
296 value |= USB2_OTG_PD;
297 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
299 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
300 value |= USB2_OTG_PD_DR;
301 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
305 tegra186_utmi_bias_pad_power_off(padctl);
308 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
313 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
315 value = padctl_readl(padctl, USB2_VBUS_ID);
318 value |= VBUS_OVERRIDE;
319 value &= ~ID_OVERRIDE(~0);
320 value |= ID_OVERRIDE_FLOATING;
322 value &= ~VBUS_OVERRIDE;
325 padctl_writel(padctl, value, USB2_VBUS_ID);
330 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
335 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
337 value = padctl_readl(padctl, USB2_VBUS_ID);
340 if (value & VBUS_OVERRIDE) {
341 value &= ~VBUS_OVERRIDE;
342 padctl_writel(padctl, value, USB2_VBUS_ID);
343 usleep_range(1000, 2000);
345 value = padctl_readl(padctl, USB2_VBUS_ID);
348 value &= ~ID_OVERRIDE(~0);
349 value |= ID_OVERRIDE_GROUNDED;
351 value &= ~ID_OVERRIDE(~0);
352 value |= ID_OVERRIDE_FLOATING;
355 padctl_writel(padctl, value, USB2_VBUS_ID);
360 static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
363 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
364 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
365 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
369 mutex_lock(&padctl->lock);
371 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
373 if (mode == PHY_MODE_USB_OTG) {
374 if (submode == USB_ROLE_HOST) {
375 tegra186_xusb_padctl_id_override(padctl, true);
377 err = regulator_enable(port->supply);
378 } else if (submode == USB_ROLE_DEVICE) {
379 tegra186_xusb_padctl_vbus_override(padctl, true);
380 } else if (submode == USB_ROLE_NONE) {
382 * When port is peripheral only or role transitions to
383 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
386 if (regulator_is_enabled(port->supply))
387 regulator_disable(port->supply);
389 tegra186_xusb_padctl_id_override(padctl, false);
390 tegra186_xusb_padctl_vbus_override(padctl, false);
394 mutex_unlock(&padctl->lock);
399 static int tegra186_utmi_phy_power_on(struct phy *phy)
401 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
402 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
403 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
404 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
405 struct tegra_xusb_usb2_port *port;
406 unsigned int index = lane->index;
407 struct device *dev = padctl->dev;
410 port = tegra_xusb_find_usb2_port(padctl, index);
412 dev_err(dev, "no port found for USB2 lane %u\n", index);
416 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
417 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
418 value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
419 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
421 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
422 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
424 if (port->mode == USB_DR_MODE_UNKNOWN)
425 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
426 else if (port->mode == USB_DR_MODE_PERIPHERAL)
427 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
428 else if (port->mode == USB_DR_MODE_HOST)
429 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
430 else if (port->mode == USB_DR_MODE_OTG)
431 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
433 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
435 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
436 value &= ~USB2_OTG_PD_ZI;
438 value &= ~HS_CURR_LEVEL(~0);
440 if (usb2->hs_curr_level_offset) {
441 int hs_current_level;
443 hs_current_level = (int)priv->calib.hs_curr_level[index] +
444 usb2->hs_curr_level_offset;
446 if (hs_current_level < 0)
447 hs_current_level = 0;
448 if (hs_current_level > 0x3f)
449 hs_current_level = 0x3f;
451 value |= HS_CURR_LEVEL(hs_current_level);
453 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
456 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
458 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
459 value &= ~TERM_RANGE_ADJ(~0);
460 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
461 value &= ~RPD_CTRL(~0);
462 value |= RPD_CTRL(priv->calib.rpd_ctrl);
463 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
465 /* TODO: pad power saving */
466 tegra_phy_xusb_utmi_pad_power_on(phy);
470 static int tegra186_utmi_phy_power_off(struct phy *phy)
472 /* TODO: pad power saving */
473 tegra_phy_xusb_utmi_pad_power_down(phy);
478 static int tegra186_utmi_phy_init(struct phy *phy)
480 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
481 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
482 struct tegra_xusb_usb2_port *port;
483 unsigned int index = lane->index;
484 struct device *dev = padctl->dev;
487 port = tegra_xusb_find_usb2_port(padctl, index);
489 dev_err(dev, "no port found for USB2 lane %u\n", index);
493 if (port->supply && port->mode == USB_DR_MODE_HOST) {
494 err = regulator_enable(port->supply);
496 dev_err(dev, "failed to enable port %u VBUS: %d\n",
505 static int tegra186_utmi_phy_exit(struct phy *phy)
507 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
508 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
509 struct tegra_xusb_usb2_port *port;
510 unsigned int index = lane->index;
511 struct device *dev = padctl->dev;
514 port = tegra_xusb_find_usb2_port(padctl, index);
516 dev_err(dev, "no port found for USB2 lane %u\n", index);
520 if (port->supply && port->mode == USB_DR_MODE_HOST) {
521 err = regulator_disable(port->supply);
523 dev_err(dev, "failed to disable port %u VBUS: %d\n",
532 static const struct phy_ops utmi_phy_ops = {
533 .init = tegra186_utmi_phy_init,
534 .exit = tegra186_utmi_phy_exit,
535 .power_on = tegra186_utmi_phy_power_on,
536 .power_off = tegra186_utmi_phy_power_off,
537 .set_mode = tegra186_utmi_phy_set_mode,
538 .owner = THIS_MODULE,
541 static struct tegra_xusb_pad *
542 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
543 const struct tegra_xusb_pad_soc *soc,
544 struct device_node *np)
546 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
547 struct tegra_xusb_usb2_pad *usb2;
548 struct tegra_xusb_pad *pad;
551 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
553 return ERR_PTR(-ENOMEM);
556 pad->ops = &tegra186_usb2_lane_ops;
559 err = tegra_xusb_pad_init(pad, padctl, np);
565 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
566 if (IS_ERR(priv->usb2_trk_clk)) {
567 err = PTR_ERR(priv->usb2_trk_clk);
568 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
572 err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
576 dev_set_drvdata(&pad->dev, pad);
581 device_unregister(&pad->dev);
586 static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
588 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
593 static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
594 .probe = tegra186_usb2_pad_probe,
595 .remove = tegra186_usb2_pad_remove,
598 static const char * const tegra186_usb2_functions[] = {
602 static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
607 static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
611 static struct tegra_xusb_lane *
612 tegra186_usb2_port_map(struct tegra_xusb_port *port)
614 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
617 static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
618 .release = tegra_xusb_usb2_port_release,
619 .remove = tegra_xusb_usb2_port_remove,
620 .enable = tegra186_usb2_port_enable,
621 .disable = tegra186_usb2_port_disable,
622 .map = tegra186_usb2_port_map,
625 /* SuperSpeed PHY support */
626 static struct tegra_xusb_lane *
627 tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
630 struct tegra_xusb_usb3_lane *usb3;
633 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
635 return ERR_PTR(-ENOMEM);
637 INIT_LIST_HEAD(&usb3->base.list);
638 usb3->base.soc = &pad->soc->lanes[index];
639 usb3->base.index = index;
640 usb3->base.pad = pad;
643 err = tegra_xusb_lane_parse_dt(&usb3->base, np);
652 static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
654 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
659 static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
660 .probe = tegra186_usb3_lane_probe,
661 .remove = tegra186_usb3_lane_remove,
663 static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
668 static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
672 static struct tegra_xusb_lane *
673 tegra186_usb3_port_map(struct tegra_xusb_port *port)
675 return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
678 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
679 .release = tegra_xusb_usb3_port_release,
680 .remove = tegra_xusb_usb3_port_remove,
681 .enable = tegra186_usb3_port_enable,
682 .disable = tegra186_usb3_port_disable,
683 .map = tegra186_usb3_port_map,
686 static int tegra186_usb3_phy_power_on(struct phy *phy)
688 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
689 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
690 struct tegra_xusb_usb3_port *port;
691 struct tegra_xusb_usb2_port *usb2;
692 unsigned int index = lane->index;
693 struct device *dev = padctl->dev;
696 port = tegra_xusb_find_usb3_port(padctl, index);
698 dev_err(dev, "no port found for USB3 lane %u\n", index);
702 usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
704 dev_err(dev, "no companion port found for USB3 lane %u\n",
709 mutex_lock(&padctl->lock);
711 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
712 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
714 if (usb2->mode == USB_DR_MODE_UNKNOWN)
715 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
716 else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
717 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
718 else if (usb2->mode == USB_DR_MODE_HOST)
719 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
720 else if (usb2->mode == USB_DR_MODE_OTG)
721 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
723 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
725 if (padctl->soc->supports_gen2 && port->disable_gen2) {
726 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
727 value &= ~(PORTX_SPEED_SUPPORT_MASK <<
728 PORTX_SPEED_SUPPORT_SHIFT(index));
729 value |= (PORT_SPEED_SUPPORT_GEN1 <<
730 PORTX_SPEED_SUPPORT_SHIFT(index));
731 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
734 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
735 value &= ~SSPX_ELPG_VCORE_DOWN(index);
736 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
738 usleep_range(100, 200);
740 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
741 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
742 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
744 usleep_range(100, 200);
746 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
747 value &= ~SSPX_ELPG_CLAMP_EN(index);
748 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
750 mutex_unlock(&padctl->lock);
755 static int tegra186_usb3_phy_power_off(struct phy *phy)
757 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
758 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
759 struct tegra_xusb_usb3_port *port;
760 unsigned int index = lane->index;
761 struct device *dev = padctl->dev;
764 port = tegra_xusb_find_usb3_port(padctl, index);
766 dev_err(dev, "no port found for USB3 lane %u\n", index);
770 mutex_lock(&padctl->lock);
772 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
773 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
774 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
776 usleep_range(100, 200);
778 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
779 value |= SSPX_ELPG_CLAMP_EN(index);
780 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
782 usleep_range(250, 350);
784 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
785 value |= SSPX_ELPG_VCORE_DOWN(index);
786 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
788 mutex_unlock(&padctl->lock);
793 static int tegra186_usb3_phy_init(struct phy *phy)
798 static int tegra186_usb3_phy_exit(struct phy *phy)
803 static const struct phy_ops usb3_phy_ops = {
804 .init = tegra186_usb3_phy_init,
805 .exit = tegra186_usb3_phy_exit,
806 .power_on = tegra186_usb3_phy_power_on,
807 .power_off = tegra186_usb3_phy_power_off,
808 .owner = THIS_MODULE,
811 static struct tegra_xusb_pad *
812 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
813 const struct tegra_xusb_pad_soc *soc,
814 struct device_node *np)
816 struct tegra_xusb_usb3_pad *usb3;
817 struct tegra_xusb_pad *pad;
820 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
822 return ERR_PTR(-ENOMEM);
825 pad->ops = &tegra186_usb3_lane_ops;
828 err = tegra_xusb_pad_init(pad, padctl, np);
834 err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
838 dev_set_drvdata(&pad->dev, pad);
843 device_unregister(&pad->dev);
848 static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
850 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
855 static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
856 .probe = tegra186_usb3_pad_probe,
857 .remove = tegra186_usb3_pad_remove,
860 static const char * const tegra186_usb3_functions[] = {
865 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
867 struct device *dev = padctl->base.dev;
868 unsigned int i, count;
872 count = padctl->base.soc->ports.usb2.count;
874 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
878 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
880 if (err != -EPROBE_DEFER)
881 dev_err(dev, "failed to read calibration fuse: %d\n",
886 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
888 for (i = 0; i < count; i++)
889 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
890 HS_CURR_LEVEL_PAD_MASK;
892 padctl->calib.hs_curr_level = level;
894 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
896 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
897 HS_TERM_RANGE_ADJ_MASK;
899 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
901 dev_err(dev, "failed to read calibration fuse: %d\n", err);
905 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
907 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
912 static struct tegra_xusb_padctl *
913 tegra186_xusb_padctl_probe(struct device *dev,
914 const struct tegra_xusb_padctl_soc *soc)
916 struct tegra186_xusb_padctl *priv;
919 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
921 return ERR_PTR(-ENOMEM);
923 priv->base.dev = dev;
924 priv->base.soc = soc;
926 err = tegra186_xusb_read_fuse_calibration(priv);
933 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
937 static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
938 .probe = tegra186_xusb_padctl_probe,
939 .remove = tegra186_xusb_padctl_remove,
940 .vbus_override = tegra186_xusb_padctl_vbus_override,
943 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
944 static const char * const tegra186_xusb_padctl_supply_names[] = {
951 static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
952 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
953 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
954 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
957 static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
959 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
960 .lanes = tegra186_usb2_lanes,
961 .ops = &tegra186_usb2_pad_ops,
964 static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
965 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
966 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
967 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
970 static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
972 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
973 .lanes = tegra186_usb3_lanes,
974 .ops = &tegra186_usb3_pad_ops,
977 static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
980 #if 0 /* TODO implement */
985 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
986 .num_pads = ARRAY_SIZE(tegra186_pads),
987 .pads = tegra186_pads,
990 .ops = &tegra186_usb2_port_ops,
993 #if 0 /* TODO implement */
995 .ops = &tegra186_hsic_port_ops,
1000 .ops = &tegra186_usb3_port_ops,
1004 .ops = &tegra186_xusb_padctl_ops,
1005 .supply_names = tegra186_xusb_padctl_supply_names,
1006 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1008 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1011 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
1012 static const char * const tegra194_xusb_padctl_supply_names[] = {
1017 static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1018 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1019 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1020 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1021 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1024 static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1026 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1027 .lanes = tegra194_usb2_lanes,
1028 .ops = &tegra186_usb2_pad_ops,
1031 static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1032 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1033 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1034 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1035 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1038 static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1040 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1041 .lanes = tegra194_usb3_lanes,
1042 .ops = &tegra186_usb3_pad_ops,
1045 static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1050 const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1051 .num_pads = ARRAY_SIZE(tegra194_pads),
1052 .pads = tegra194_pads,
1055 .ops = &tegra186_usb2_port_ops,
1059 .ops = &tegra186_usb3_port_ops,
1063 .ops = &tegra186_xusb_padctl_ops,
1064 .supply_names = tegra194_xusb_padctl_supply_names,
1065 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1066 .supports_gen2 = true,
1068 EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1071 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1072 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1073 MODULE_LICENSE("GPL v2");