1 // SPDX-License-Identifier: GPL-2.0
3 * STMicroelectronics STM32 USB PHY Controller driver
5 * Copyright (C) 2018 STMicroelectronics
6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
8 #include <linux/bitfield.h>
10 #include <linux/delay.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/phy/phy.h>
16 #include <linux/reset.h>
18 #define STM32_USBPHYC_PLL 0x0
19 #define STM32_USBPHYC_MISC 0x8
20 #define STM32_USBPHYC_VERSION 0x3F4
22 /* STM32_USBPHYC_PLL bit fields */
23 #define PLLNDIV GENMASK(6, 0)
24 #define PLLFRACIN GENMASK(25, 10)
26 #define PLLSTRB BIT(27)
27 #define PLLSTRBYP BIT(28)
28 #define PLLFRACCTL BIT(29)
29 #define PLLDITHEN0 BIT(30)
30 #define PLLDITHEN1 BIT(31)
32 /* STM32_USBPHYC_MISC bit fields */
33 #define SWITHOST BIT(0)
35 /* STM32_USBPHYC_VERSION bit fields */
36 #define MINREV GENMASK(3, 0)
37 #define MAJREV GENMASK(7, 4)
39 static const char * const supplies_names[] = {
44 #define NUM_SUPPLIES ARRAY_SIZE(supplies_names)
46 #define PLL_LOCK_TIME_US 100
47 #define PLL_PWR_DOWN_TIME_US 5
48 #define PLL_FVCO_MHZ 2880
49 #define PLL_INFF_MIN_RATE_HZ 19200000
50 #define PLL_INFF_MAX_RATE_HZ 38400000
51 #define HZ_PER_MHZ 1000000L
58 struct stm32_usbphyc_phy {
60 struct stm32_usbphyc *usbphyc;
61 struct regulator_bulk_data supplies[NUM_SUPPLIES];
66 struct stm32_usbphyc {
70 struct reset_control *rst;
71 struct stm32_usbphyc_phy **phys;
76 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
78 writel_relaxed(readl_relaxed(reg) | bits, reg);
81 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
83 writel_relaxed(readl_relaxed(reg) & ~bits, reg);
86 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
87 struct pll_params *pll_params)
89 unsigned long long fvco, ndiv, frac;
92 * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
95 * | NDIV = integer part of input bits to set the LDF
96 * |_FRACT = fractional part of input bits to set the LDF
97 * => PLLNDIV = integer part of (FVCO / (INFF*2))
98 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
99 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
101 fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
104 do_div(ndiv, (clk_rate * 2));
105 pll_params->ndiv = (u8)ndiv;
107 frac = fvco * (1 << 16);
108 do_div(frac, (clk_rate * 2));
109 frac = frac - (ndiv * (1 << 16));
110 pll_params->frac = (u16)frac;
113 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
115 struct pll_params pll_params;
116 u32 clk_rate = clk_get_rate(usbphyc->clk);
120 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
121 (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
122 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
127 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
128 ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
129 frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
131 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
134 usbphyc_pll |= PLLFRACCTL | frac;
136 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
138 dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
139 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
140 FIELD_GET(PLLFRACIN, usbphyc_pll));
145 static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
149 for (i = 0; i < usbphyc->nphys; i++)
150 if (usbphyc->phys[i]->active)
156 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
158 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
159 bool pllen = (readl_relaxed(pll_reg) & PLLEN);
162 /* Check if one phy port has already configured the pll */
163 if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
167 stm32_usbphyc_clr_bits(pll_reg, PLLEN);
168 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
169 udelay(PLL_PWR_DOWN_TIME_US);
172 ret = stm32_usbphyc_pll_init(usbphyc);
176 stm32_usbphyc_set_bits(pll_reg, PLLEN);
178 /* Wait for maximum lock time */
179 udelay(PLL_LOCK_TIME_US);
181 if (!(readl_relaxed(pll_reg) & PLLEN)) {
182 dev_err(usbphyc->dev, "PLLEN not set\n");
189 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
191 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
193 /* Check if other phy port active */
194 if (stm32_usbphyc_has_one_phy_active(usbphyc))
197 stm32_usbphyc_clr_bits(pll_reg, PLLEN);
198 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
199 udelay(PLL_PWR_DOWN_TIME_US);
201 if (readl_relaxed(pll_reg) & PLLEN) {
202 dev_err(usbphyc->dev, "PLL not reset\n");
209 static int stm32_usbphyc_phy_init(struct phy *phy)
211 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
212 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
215 ret = stm32_usbphyc_pll_enable(usbphyc);
219 usbphyc_phy->active = true;
224 static int stm32_usbphyc_phy_exit(struct phy *phy)
226 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
227 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
229 usbphyc_phy->active = false;
231 return stm32_usbphyc_pll_disable(usbphyc);
234 static int stm32_usbphyc_phy_power_on(struct phy *phy)
236 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
238 return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
241 static int stm32_usbphyc_phy_power_off(struct phy *phy)
243 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
245 return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
248 static const struct phy_ops stm32_usbphyc_phy_ops = {
249 .init = stm32_usbphyc_phy_init,
250 .exit = stm32_usbphyc_phy_exit,
251 .power_on = stm32_usbphyc_phy_power_on,
252 .power_off = stm32_usbphyc_phy_power_off,
253 .owner = THIS_MODULE,
256 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
260 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
263 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
265 usbphyc->switch_setup = utmi_switch;
268 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
269 struct of_phandle_args *args)
271 struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
272 struct stm32_usbphyc_phy *usbphyc_phy = NULL;
273 struct device_node *phynode = args->np;
276 for (port = 0; port < usbphyc->nphys; port++) {
277 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
278 usbphyc_phy = usbphyc->phys[port];
283 dev_err(dev, "failed to find phy\n");
284 return ERR_PTR(-EINVAL);
287 if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
288 ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
289 dev_err(dev, "invalid number of cells for phy port%d\n",
291 return ERR_PTR(-EINVAL);
294 /* Configure the UTMI switch for PHY port#2 */
295 if (usbphyc_phy->index == 1) {
296 if (usbphyc->switch_setup < 0) {
297 stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
299 if (args->args[0] != usbphyc->switch_setup) {
300 dev_err(dev, "phy port1 already used\n");
301 return ERR_PTR(-EBUSY);
306 return usbphyc_phy->phy;
309 static int stm32_usbphyc_probe(struct platform_device *pdev)
311 struct stm32_usbphyc *usbphyc;
312 struct device *dev = &pdev->dev;
313 struct device_node *child, *np = dev->of_node;
314 struct resource *res;
315 struct phy_provider *phy_provider;
319 usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
323 dev_set_drvdata(dev, usbphyc);
325 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
326 usbphyc->base = devm_ioremap_resource(dev, res);
327 if (IS_ERR(usbphyc->base))
328 return PTR_ERR(usbphyc->base);
330 usbphyc->clk = devm_clk_get(dev, NULL);
331 if (IS_ERR(usbphyc->clk)) {
332 ret = PTR_ERR(usbphyc->clk);
333 dev_err(dev, "clk get failed: %d\n", ret);
337 ret = clk_prepare_enable(usbphyc->clk);
339 dev_err(dev, "clk enable failed: %d\n", ret);
343 usbphyc->rst = devm_reset_control_get(dev, NULL);
344 if (!IS_ERR(usbphyc->rst)) {
345 reset_control_assert(usbphyc->rst);
347 reset_control_deassert(usbphyc->rst);
350 usbphyc->switch_setup = -EINVAL;
351 usbphyc->nphys = of_get_child_count(np);
352 usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
353 sizeof(*usbphyc->phys), GFP_KERNEL);
354 if (!usbphyc->phys) {
359 for_each_child_of_node(np, child) {
360 struct stm32_usbphyc_phy *usbphyc_phy;
365 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
368 if (ret != -EPROBE_DEFER)
369 dev_err(dev, "failed to create phy%d: %d\n",
374 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
381 for (i = 0; i < NUM_SUPPLIES; i++)
382 usbphyc_phy->supplies[i].supply = supplies_names[i];
384 ret = devm_regulator_bulk_get(&phy->dev, NUM_SUPPLIES,
385 usbphyc_phy->supplies);
387 if (ret != -EPROBE_DEFER)
389 "failed to get regulators: %d\n", ret);
393 ret = of_property_read_u32(child, "reg", &index);
394 if (ret || index > usbphyc->nphys) {
395 dev_err(&phy->dev, "invalid reg property: %d\n", ret);
401 usbphyc->phys[port] = usbphyc_phy;
402 phy_set_bus_width(phy, 8);
403 phy_set_drvdata(phy, usbphyc_phy);
405 usbphyc->phys[port]->phy = phy;
406 usbphyc->phys[port]->usbphyc = usbphyc;
407 usbphyc->phys[port]->index = index;
408 usbphyc->phys[port]->active = false;
413 phy_provider = devm_of_phy_provider_register(dev,
414 stm32_usbphyc_of_xlate);
415 if (IS_ERR(phy_provider)) {
416 ret = PTR_ERR(phy_provider);
417 dev_err(dev, "failed to register phy provider: %d\n", ret);
421 version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
422 dev_info(dev, "registered rev:%lu.%lu\n",
423 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
430 clk_disable_unprepare(usbphyc->clk);
435 static int stm32_usbphyc_remove(struct platform_device *pdev)
437 struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
439 clk_disable_unprepare(usbphyc->clk);
444 static const struct of_device_id stm32_usbphyc_of_match[] = {
445 { .compatible = "st,stm32mp1-usbphyc", },
448 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
450 static struct platform_driver stm32_usbphyc_driver = {
451 .probe = stm32_usbphyc_probe,
452 .remove = stm32_usbphyc_remove,
454 .of_match_table = stm32_usbphyc_of_match,
455 .name = "stm32-usbphyc",
458 module_platform_driver(stm32_usbphyc_driver);
460 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
461 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
462 MODULE_LICENSE("GPL v2");